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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[POWERPC] 4xx: PLB to PCI 2.x support
This adds to the previous patch the support for the 4xx PCI 2.x bridges. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Benjamin Herrenschmidt
Josh Boyer
parent
5738ec6d00
commit
c839e0eff5
@ -21,6 +21,36 @@ static int dma_offset_set;
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/* Move that to a useable header */
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extern unsigned long total_memory;
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static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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int i;
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if (dev->devfn != 0 || dev->bus->self != NULL)
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return;
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hose = pci_bus_to_host(dev->bus);
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if (hose == NULL)
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return;
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if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
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!of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
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!of_device_is_compatible(hose->dn, "ibm,plb-pci"))
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return;
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/* Hide the PCI host BARs from the kernel as their content doesn't
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* fit well in the resource management
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*/
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
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pci_name(dev));
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
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static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
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void __iomem *reg,
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struct resource *res)
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@ -126,9 +156,157 @@ static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
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/*
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* 4xx PCI 2.x part
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*/
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static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
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void __iomem *reg)
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{
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u32 la, ma, pcila, pciha;
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int i, j;
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/* Setup outbound memory windows */
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for (i = j = 0; i < 3; i++) {
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struct resource *res = &hose->mem_resources[i];
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/* we only care about memory windows */
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if (!(res->flags & IORESOURCE_MEM))
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continue;
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if (j > 2) {
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printk(KERN_WARNING "%s: Too many ranges\n",
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hose->dn->full_name);
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break;
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}
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/* Calculate register values */
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la = res->start;
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#ifdef CONFIG_RESOURCES_64BIT
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pciha = (res->start - hose->pci_mem_offset) >> 32;
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pcila = (res->start - hose->pci_mem_offset) & 0xffffffffu;
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#else
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pciha = 0;
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pcila = res->start - hose->pci_mem_offset;
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#endif
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ma = res->end + 1 - res->start;
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if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
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printk(KERN_WARNING "%s: Resource out of range\n",
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hose->dn->full_name);
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continue;
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}
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ma = (0xffffffffu << ilog2(ma)) | 0x1;
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if (res->flags & IORESOURCE_PREFETCH)
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ma |= 0x2;
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/* Program register values */
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writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
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writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
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writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
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writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
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j++;
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}
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}
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static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
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void __iomem *reg,
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const struct resource *res)
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{
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resource_size_t size = res->end - res->start + 1;
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u32 sa;
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/* Calculate window size */
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sa = (0xffffffffu << ilog2(size)) | 1;
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sa |= 0x1;
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/* RAM is always at 0 local for now */
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writel(0, reg + PCIL0_PTM1LA);
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writel(sa, reg + PCIL0_PTM1MS);
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/* Map on PCI side */
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early_write_config_dword(hose, hose->first_busno, 0,
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PCI_BASE_ADDRESS_1, res->start);
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early_write_config_dword(hose, hose->first_busno, 0,
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PCI_BASE_ADDRESS_2, 0x00000000);
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early_write_config_word(hose, hose->first_busno, 0,
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PCI_COMMAND, 0x0006);
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}
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static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
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{
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/* NYI */
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struct resource rsrc_cfg;
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struct resource rsrc_reg;
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struct resource dma_window;
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struct pci_controller *hose = NULL;
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void __iomem *reg = NULL;
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const int *bus_range;
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int primary = 0;
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/* Fetch config space registers address */
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if (of_address_to_resource(np, 0, &rsrc_cfg)) {
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printk(KERN_ERR "%s:Can't get PCI config register base !",
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np->full_name);
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return;
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}
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/* Fetch host bridge internal registers address */
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if (of_address_to_resource(np, 3, &rsrc_reg)) {
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printk(KERN_ERR "%s: Can't get PCI internal register base !",
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np->full_name);
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return;
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}
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/* Check if primary bridge */
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if (of_get_property(np, "primary", NULL))
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primary = 1;
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/* Get bus range if any */
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bus_range = of_get_property(np, "bus-range", NULL);
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/* Map registers */
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reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
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if (reg == NULL) {
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printk(KERN_ERR "%s: Can't map registers !", np->full_name);
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goto fail;
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}
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/* Allocate the host controller data structure */
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hose = pcibios_alloc_controller(np);
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if (!hose)
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goto fail;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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/* Setup config space */
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setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
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/* Disable all windows */
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writel(0, reg + PCIL0_PMM0MA);
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writel(0, reg + PCIL0_PMM1MA);
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writel(0, reg + PCIL0_PMM2MA);
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writel(0, reg + PCIL0_PTM1MS);
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writel(0, reg + PCIL0_PTM2MS);
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/* Parse outbound mapping resources */
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pci_process_bridge_OF_ranges(hose, np, primary);
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/* Parse inbound mapping resources */
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if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
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goto fail;
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/* Configure outbound ranges POMs */
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ppc4xx_configure_pci_PMMs(hose, reg);
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/* Configure inbound ranges PIMs */
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ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
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/* We don't need the registers anymore */
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iounmap(reg);
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return;
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fail:
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if (hose)
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pcibios_free_controller(hose);
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if (reg)
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iounmap(reg);
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}
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/*
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@ -155,7 +333,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
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}
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/* Calculate register values */
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#ifdef CONFIG_PTE_64BIT
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#ifdef CONFIG_RESOURCES_64BIT
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lah = res->start >> 32;
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lal = res->start & 0xffffffffu;
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pciah = (res->start - hose->pci_mem_offset) >> 32;
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@ -101,6 +101,25 @@
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#define PCIX0_MSGOH 0x10c
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#define PCIX0_IM 0x1f8
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/*
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* 4xx PCI bridge register definitions
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*/
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#define PCIL0_PMM0LA 0x00
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#define PCIL0_PMM0MA 0x04
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#define PCIL0_PMM0PCILA 0x08
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#define PCIL0_PMM0PCIHA 0x0c
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#define PCIL0_PMM1LA 0x10
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#define PCIL0_PMM1MA 0x14
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#define PCIL0_PMM1PCILA 0x18
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#define PCIL0_PMM1PCIHA 0x1c
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#define PCIL0_PMM2LA 0x20
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#define PCIL0_PMM2MA 0x24
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#define PCIL0_PMM2PCILA 0x28
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#define PCIL0_PMM2PCIHA 0x2c
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#define PCIL0_PTM1MS 0x30
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#define PCIL0_PTM1LA 0x34
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#define PCIL0_PTM2MS 0x38
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#define PCIL0_PTM2LA 0x3c
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#endif /* __PPC4XX_PCI_H__ */
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