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i2c: img-scb: add handle for Master halt interrupt

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Master halt is issued after each byte of a transaction is processed in
IP version 3.3.
Master halt will stall the bus by holding the SCK line low until the
halt bit in the scb_general_control is cleared.

After the last byte of a transfer is processed we can use the Master
Halt interrupt to facilitate a repeated start transfer without
issuing a stop bit.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
Reviewed-by: James Hartley <james.hartley@imgtec.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Sifan Naeem 2015-11-19 09:35:16 +00:00 committed by Wolfram Sang
parent dd29207e6c
commit c7b0a7c107
1 changed files with 14 additions and 3 deletions
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17
drivers/i2c/busses/i2c-img-scb.c
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@ -151,6 +151,7 @@
#define INT_FIFO_EMPTYING BIT(12) #define INT_FIFO_EMPTYING BIT(12)
#define INT_TRANSACTION_DONE BIT(15) #define INT_TRANSACTION_DONE BIT(15)
#define INT_SLAVE_EVENT BIT(16) #define INT_SLAVE_EVENT BIT(16)
#define INT_MASTER_HALTED BIT(17)
#define INT_TIMING BIT(18) #define INT_TIMING BIT(18)
#define INT_STOP_DETECTED BIT(19) #define INT_STOP_DETECTED BIT(19)
@ -177,6 +178,7 @@
INT_FIFO_FULL | \ INT_FIFO_FULL | \
INT_FIFO_FILLING | \ INT_FIFO_FILLING | \
INT_FIFO_EMPTY | \ INT_FIFO_EMPTY | \
INT_MASTER_HALTED | \
INT_STOP_DETECTED) INT_STOP_DETECTED)
#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
@ -875,18 +877,27 @@ static unsigned int img_i2c_auto(struct img_i2c *i2c,
} }
if (i2c->msg.flags & I2C_M_RD) { if (i2c->msg.flags & I2C_M_RD) {
if (int_status & INT_FIFO_FULL_FILLING) { if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) {
img_i2c_read_fifo(i2c); img_i2c_read_fifo(i2c);
if (i2c->msg.len == 0) if (i2c->msg.len == 0)
return ISR_WAITSTOP; return ISR_WAITSTOP;
} }
} else { } else {
if (int_status & INT_FIFO_EMPTY) { if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) {
if (i2c->msg.len == 0) if ((int_status & INT_FIFO_EMPTY) &&
i2c->msg.len == 0)
return ISR_WAITSTOP; return ISR_WAITSTOP;
img_i2c_write_fifo(i2c); img_i2c_write_fifo(i2c);
} }
} }
if (int_status & INT_MASTER_HALTED) {
/*
* Release and then enable transaction halt, to
* allow only a single byte to proceed.
*/
img_i2c_transaction_halt(i2c, false);
img_i2c_transaction_halt(i2c, !i2c->last_msg);
}
return 0; return 0;
} }