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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'pci/trivial'
- Cleanup PCI register definitions, typos, etc (Bjorn Helgaas) - Remove unnecessary use of user-space types in CPER (Bjorn Helgaas) - Cleanup setup-bus.c comments & whitespace (Nicholas Johnson) * pci/trivial: PCI: Cleanup setup-bus.c comments and whitespace CPER: Remove unnecessary use of user-space types CPER: Add UEFI spec references PCI: Fix comment typos PCI: Cleanup register definition width and whitespace # Conflicts: # drivers/pci/pci.c # drivers/pci/setup-bus.c
This commit is contained in:
Bjorn Helgaas
commit
c7a1c2bbb6
@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Simple, generic PCI host controller driver targetting firmware-initialised
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* Simple, generic PCI host controller driver targeting firmware-initialised
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* systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
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*
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* Copyright (C) 2014 ARM Limited
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@ -367,7 +367,7 @@ static void iproc_msi_handler(struct irq_desc *desc)
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/*
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* Now go read the tail pointer again to see if there are new
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* oustanding events that came in during the above window.
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* outstanding events that came in during the above window.
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*/
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} while (true);
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@ -425,7 +425,7 @@ static int __pci_bus_find_cap_start(struct pci_bus *bus,
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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* support it. Possible values for @cap include:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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@ -454,7 +454,7 @@ EXPORT_SYMBOL(pci_find_capability);
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* @devfn: PCI device to query
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* @cap: capability code
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*
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* Like pci_find_capability() but works for pci devices that do not have a
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* Like pci_find_capability() but works for PCI devices that do not have a
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* pci_dev structure set up yet.
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*
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* Returns the address of the requested capability structure within the
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@ -535,7 +535,7 @@ EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
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*
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* Returns the address of the requested extended capability structure
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* within the device's PCI configuration space or 0 if the device does
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* not support it. Possible values for @cap:
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* not support it. Possible values for @cap include:
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*
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* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
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* %PCI_EXT_CAP_ID_VC Virtual Channel
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@ -618,12 +618,13 @@ int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
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EXPORT_SYMBOL_GPL(pci_find_ht_capability);
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/**
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* pci_find_parent_resource - return resource region of parent bus of given region
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* pci_find_parent_resource - return resource region of parent bus of given
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* region
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* @dev: PCI device structure contains resources to be searched
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* @res: child resource record for which parent is sought
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*
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* For given resource region of given device, return the resource
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* region of parent bus the given region is contained in.
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* For given resource region of given device, return the resource region of
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* parent bus the given region is contained in.
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*/
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struct resource *pci_find_parent_resource(const struct pci_dev *dev,
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struct resource *res)
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@ -826,7 +827,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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if (state < PCI_D0 || state > PCI_D3hot)
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return -EINVAL;
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/* Validate current state:
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/*
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* Validate current state:
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* Can enter D0 from any state, but if we can only go deeper
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* to sleep if we're already in a low power state
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*/
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@ -837,14 +839,15 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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return -EINVAL;
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}
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/* check if this device supports the desired state */
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/* Check if this device supports the desired state */
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if ((state == PCI_D1 && !dev->d1_support)
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|| (state == PCI_D2 && !dev->d2_support))
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return -EIO;
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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/* If we're (effectively) in D3, force entire word to 0.
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/*
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* If we're (effectively) in D3, force entire word to 0.
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* This doesn't affect PME_Status, disables PME_En, and
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* sets PowerState to 0.
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*/
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@ -867,11 +870,13 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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break;
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}
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/* enter specified state */
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/* Enter specified state */
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pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
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/* Mandatory power management transition delays */
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/* see PCI PM 1.1 5.6.1 table 18 */
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/*
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* Mandatory power management transition delays; see PCI PM 1.1
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* 5.6.1 table 18
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*/
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if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
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pci_dev_d3_sleep(dev);
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else if (state == PCI_D2 || dev->current_state == PCI_D2)
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@ -1085,16 +1090,18 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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int error;
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/* bound the state we're entering */
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/* Bound the state we're entering */
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if (state > PCI_D3cold)
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state = PCI_D3cold;
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else if (state < PCI_D0)
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state = PCI_D0;
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else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
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/*
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* If the device or the parent bridge do not support PCI PM,
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* ignore the request if we're doing anything other than putting
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* it into D0 (which would only happen on boot).
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* If the device or the parent bridge do not support PCI
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* PM, ignore the request if we're doing anything other
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* than putting it into D0 (which would only happen on
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* boot).
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*/
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return 0;
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@ -1104,8 +1111,10 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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__pci_start_power_transition(dev, state);
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/* This device is quirked not to be put into D3, so
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don't put it in D3 */
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/*
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* This device is quirked not to be put into D3, so don't put it in
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* D3
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*/
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if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
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return 0;
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@ -1132,7 +1141,6 @@ EXPORT_SYMBOL(pci_set_power_state);
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* Returns PCI power state suitable for given device and given system
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* message.
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*/
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pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
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{
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pci_power_t ret;
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@ -1310,8 +1318,9 @@ static void pci_restore_ltr_state(struct pci_dev *dev)
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}
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/**
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* pci_save_state - save the PCI configuration space of a device before suspending
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* @dev: - PCI device that we're dealing with
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* pci_save_state - save the PCI configuration space of a device before
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* suspending
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* @dev: PCI device that we're dealing with
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*/
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int pci_save_state(struct pci_dev *dev)
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{
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@ -1422,7 +1431,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev)
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/**
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* pci_restore_state - Restore the saved state of a PCI device
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* @dev: - PCI device that we're dealing with
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* @dev: PCI device that we're dealing with
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*/
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void pci_restore_state(struct pci_dev *dev)
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{
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@ -1599,7 +1608,7 @@ static int do_pci_enable_device(struct pci_dev *dev, int bars)
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* pci_reenable_device - Resume abandoned device
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* @dev: PCI device to be resumed
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*
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* Note this function is a backend of pci_default_resume and is not supposed
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* NOTE: This function is a backend of pci_default_resume() and is not supposed
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* to be called by normal code, write proper resume handler and use it instead.
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*/
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int pci_reenable_device(struct pci_dev *dev)
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@ -1717,8 +1726,8 @@ int pci_enable_device(struct pci_dev *dev)
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EXPORT_SYMBOL(pci_enable_device);
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/*
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* Managed PCI resources. This manages device on/off, intx/msi/msix
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* on/off and BAR regions. pci_dev itself records msi/msix status, so
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* Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
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* on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
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* there's no need to track it separately. pci_devres is initialized
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* when a device is enabled using managed PCI device enable interface.
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*/
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@ -1836,7 +1845,8 @@ int __weak pcibios_add_device(struct pci_dev *dev)
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}
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/**
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* pcibios_release_device - provide arch specific hooks when releasing device dev
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* pcibios_release_device - provide arch specific hooks when releasing
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* device dev
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* @dev: the PCI device being released
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*
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* Permits the platform to provide architecture specific functionality when
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@ -1927,8 +1937,7 @@ EXPORT_SYMBOL(pci_disable_device);
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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*
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*
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* Sets the PCIe reset state for the device. This is the default
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* Set the PCIe reset state for the device. This is the default
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* implementation. Architecture implementations can override this.
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*/
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int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
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@ -1942,7 +1951,6 @@ int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
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* @dev: the PCIe device reset
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* @state: Reset state to enter into
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*
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*
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* Sets the PCI reset state for the device.
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*/
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int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
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@ -2339,7 +2347,8 @@ static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
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}
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/**
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* pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
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* pci_prepare_to_sleep - prepare PCI device for system-wide transition
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* into a sleep state
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* @dev: Device to handle.
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*
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* Choose the power state appropriate for the device depending on whether
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@ -2367,7 +2376,8 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
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EXPORT_SYMBOL(pci_prepare_to_sleep);
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/**
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* pci_back_from_sleep - turn PCI device on during system-wide transition into working state
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* pci_back_from_sleep - turn PCI device on during system-wide transition
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* into working state
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* @dev: Device to handle.
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*
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* Disable device's system wake-up capability and put it into D0.
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@ -3186,7 +3196,7 @@ static void pci_disable_acs_redir(struct pci_dev *dev)
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}
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/**
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* pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
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* pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
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* @dev: the PCI device
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*/
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static void pci_std_enable_acs(struct pci_dev *dev)
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@ -3610,11 +3620,12 @@ EXPORT_SYMBOL_GPL(pci_common_swizzle);
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/**
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* pci_release_region - Release a PCI bar
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* @pdev: PCI device whose resources were previously reserved by pci_request_region
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* @pdev: PCI device whose resources were previously reserved by
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* pci_request_region()
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* @bar: BAR to release
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*
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* Releases the PCI I/O and memory resources previously reserved by a
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* successful call to pci_request_region. Call this function only
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* successful call to pci_request_region(). Call this function only
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* after all use of the PCI regions has ceased.
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*/
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void pci_release_region(struct pci_dev *pdev, int bar)
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@ -3643,7 +3654,7 @@ EXPORT_SYMBOL(pci_release_region);
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* @res_name: Name to be associated with resource.
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* @exclusive: whether the region access is exclusive or not
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*
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* Mark the PCI region associated with PCI device @pdev BR @bar as
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* Mark the PCI region associated with PCI device @pdev BAR @bar as
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* being reserved by owner @res_name. Do not access any
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* address inside the PCI regions unless this call returns
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* successfully.
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@ -3767,10 +3778,11 @@ EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
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/**
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* pci_release_regions - Release reserved PCI I/O and memory resources
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* @pdev: PCI device whose resources were previously reserved by pci_request_regions
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* @pdev: PCI device whose resources were previously reserved by
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* pci_request_regions()
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*
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* Releases all PCI I/O and memory resources previously reserved by a
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* successful call to pci_request_regions. Call this function only
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* successful call to pci_request_regions(). Call this function only
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* after all use of the PCI regions has ceased.
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*/
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@ -3781,7 +3793,7 @@ void pci_release_regions(struct pci_dev *pdev)
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EXPORT_SYMBOL(pci_release_regions);
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/**
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* pci_request_regions - Reserved PCI I/O and memory resources
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* pci_request_regions - Reserve PCI I/O and memory resources
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* @pdev: PCI device whose resources are to be reserved
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* @res_name: Name to be associated with resource.
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*
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@ -3800,20 +3812,19 @@ int pci_request_regions(struct pci_dev *pdev, const char *res_name)
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EXPORT_SYMBOL(pci_request_regions);
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/**
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* pci_request_regions_exclusive - Reserved PCI I/O and memory resources
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* pci_request_regions_exclusive - Reserve PCI I/O and memory resources
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* @pdev: PCI device whose resources are to be reserved
|
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* @res_name: Name to be associated with resource.
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*
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* Mark all PCI regions associated with PCI device @pdev as
|
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* being reserved by owner @res_name. Do not access any
|
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* address inside the PCI regions unless this call returns
|
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* successfully.
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* Mark all PCI regions associated with PCI device @pdev as being reserved
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* by owner @res_name. Do not access any address inside the PCI regions
|
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* unless this call returns successfully.
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*
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* pci_request_regions_exclusive() will mark the region so that
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* /dev/mem and the sysfs MMIO access will not be allowed.
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* pci_request_regions_exclusive() will mark the region so that /dev/mem
|
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* and the sysfs MMIO access will not be allowed.
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*
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* Returns 0 on success, or %EBUSY on error. A warning
|
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* message is also printed on failure.
|
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* Returns 0 on success, or %EBUSY on error. A warning message is also
|
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* printed on failure.
|
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*/
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int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
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{
|
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@ -3824,7 +3835,7 @@ EXPORT_SYMBOL(pci_request_regions_exclusive);
|
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|
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/*
|
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* Record the PCI IO range (expressed as CPU physical address + size).
|
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* Return a negative value if an error has occured, zero otherwise
|
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* Return a negative value if an error has occurred, zero otherwise
|
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*/
|
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int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
|
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resource_size_t size)
|
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@ -3884,10 +3895,10 @@ unsigned long __weak pci_address_to_pio(phys_addr_t address)
|
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* @res: Resource describing the I/O space
|
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* @phys_addr: physical address of range to be mapped
|
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*
|
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* Remap the memory mapped I/O space described by the @res
|
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* and the CPU physical address @phys_addr into virtual address space.
|
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* Only architectures that have memory mapped IO functions defined
|
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* (and the PCI_IOBASE value defined) should call this function.
|
||||
* Remap the memory mapped I/O space described by the @res and the CPU
|
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* physical address @phys_addr into virtual address space. Only
|
||||
* architectures that have memory mapped IO functions defined (and the
|
||||
* PCI_IOBASE value defined) should call this function.
|
||||
*/
|
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int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
|
||||
{
|
||||
@ -3903,8 +3914,10 @@ int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
|
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return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
|
||||
pgprot_device(PAGE_KERNEL));
|
||||
#else
|
||||
/* this architecture does not have memory mapped I/O space,
|
||||
so this function should never be called */
|
||||
/*
|
||||
* This architecture does not have memory mapped I/O space,
|
||||
* so this function should never be called
|
||||
*/
|
||||
WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
|
||||
return -ENODEV;
|
||||
#endif
|
||||
@ -3915,9 +3928,9 @@ EXPORT_SYMBOL(pci_remap_iospace);
|
||||
* pci_unmap_iospace - Unmap the memory mapped I/O space
|
||||
* @res: resource to be unmapped
|
||||
*
|
||||
* Unmap the CPU virtual address @res from virtual address space.
|
||||
* Only architectures that have memory mapped IO functions defined
|
||||
* (and the PCI_IOBASE value defined) should call this function.
|
||||
* Unmap the CPU virtual address @res from virtual address space. Only
|
||||
* architectures that have memory mapped IO functions defined (and the
|
||||
* PCI_IOBASE value defined) should call this function.
|
||||
*/
|
||||
void pci_unmap_iospace(struct resource *res)
|
||||
{
|
||||
@ -4263,7 +4276,7 @@ EXPORT_SYMBOL(pci_clear_mwi);
|
||||
* @pdev: the PCI device to operate on
|
||||
* @enable: boolean: whether to enable or disable PCI INTx
|
||||
*
|
||||
* Enables/disables PCI INTx for device dev
|
||||
* Enables/disables PCI INTx for device @pdev
|
||||
*/
|
||||
void pci_intx(struct pci_dev *pdev, int enable)
|
||||
{
|
||||
@ -4339,9 +4352,8 @@ static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
|
||||
* pci_check_and_mask_intx - mask INTx on pending interrupt
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* Check if the device dev has its INTx line asserted, mask it and
|
||||
* return true in that case. False is returned if no interrupt was
|
||||
* pending.
|
||||
* Check if the device dev has its INTx line asserted, mask it and return
|
||||
* true in that case. False is returned if no interrupt was pending.
|
||||
*/
|
||||
bool pci_check_and_mask_intx(struct pci_dev *dev)
|
||||
{
|
||||
@ -4353,9 +4365,9 @@ EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
|
||||
* pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* Check if the device dev has its INTx line asserted, unmask it if not
|
||||
* and return true. False is returned and the mask remains active if
|
||||
* there was still an interrupt pending.
|
||||
* Check if the device dev has its INTx line asserted, unmask it if not and
|
||||
* return true. False is returned and the mask remains active if there was
|
||||
* still an interrupt pending.
|
||||
*/
|
||||
bool pci_check_and_unmask_intx(struct pci_dev *dev)
|
||||
{
|
||||
@ -4364,7 +4376,7 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev)
|
||||
EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
|
||||
|
||||
/**
|
||||
* pci_wait_for_pending_transaction - waits for pending transaction
|
||||
* pci_wait_for_pending_transaction - wait for pending transaction
|
||||
* @dev: the PCI device to operate on
|
||||
*
|
||||
* Return 0 if transaction is pending 1 otherwise.
|
||||
@ -4785,6 +4797,7 @@ static void pci_dev_restore(struct pci_dev *dev)
|
||||
*
|
||||
* The device function is presumed to be unused and the caller is holding
|
||||
* the device mutex lock when this function is called.
|
||||
*
|
||||
* Resetting the device will make the contents of PCI configuration space
|
||||
* random, so any caller of this must be prepared to reinitialise the
|
||||
* device including MSI, bus mastering, BARs, decoding IO and memory spaces,
|
||||
@ -5348,8 +5361,8 @@ EXPORT_SYMBOL_GPL(pci_reset_bus);
|
||||
* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Returns mmrbc: maximum designed memory read count in bytes
|
||||
* or appropriate error value.
|
||||
* Returns mmrbc: maximum designed memory read count in bytes or
|
||||
* appropriate error value.
|
||||
*/
|
||||
int pcix_get_max_mmrbc(struct pci_dev *dev)
|
||||
{
|
||||
@ -5371,8 +5384,8 @@ EXPORT_SYMBOL(pcix_get_max_mmrbc);
|
||||
* pcix_get_mmrbc - get PCI-X maximum memory read byte count
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Returns mmrbc: maximum memory read count in bytes
|
||||
* or appropriate error value.
|
||||
* Returns mmrbc: maximum memory read count in bytes or appropriate error
|
||||
* value.
|
||||
*/
|
||||
int pcix_get_mmrbc(struct pci_dev *dev)
|
||||
{
|
||||
@ -5396,7 +5409,7 @@ EXPORT_SYMBOL(pcix_get_mmrbc);
|
||||
* @mmrbc: maximum memory read count in bytes
|
||||
* valid values are 512, 1024, 2048, 4096
|
||||
*
|
||||
* If possible sets maximum memory read byte count, some bridges have erratas
|
||||
* If possible sets maximum memory read byte count, some bridges have errata
|
||||
* that prevent this.
|
||||
*/
|
||||
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
|
||||
@ -5441,8 +5454,7 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
|
||||
* pcie_get_readrq - get PCI Express read request size
|
||||
* @dev: PCI device to query
|
||||
*
|
||||
* Returns maximum memory read request in bytes
|
||||
* or appropriate error value.
|
||||
* Returns maximum memory read request in bytes or appropriate error value.
|
||||
*/
|
||||
int pcie_get_readrq(struct pci_dev *dev)
|
||||
{
|
||||
@ -5470,10 +5482,9 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* If using the "performance" PCIe config, we clamp the
|
||||
* read rq size to the max packet size to prevent the
|
||||
* host bridge generating requests larger than we can
|
||||
* cope with
|
||||
* If using the "performance" PCIe config, we clamp the read rq
|
||||
* size to the max packet size to keep the host bridge from
|
||||
* generating requests larger than we can cope with.
|
||||
*/
|
||||
if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
|
||||
int mps = pcie_get_mps(dev);
|
||||
@ -6119,6 +6130,7 @@ static int of_pci_bus_find_domain_nr(struct device *parent)
|
||||
|
||||
if (parent)
|
||||
domain = of_get_pci_domain_nr(parent->of_node);
|
||||
|
||||
/*
|
||||
* Check DT domain and use_dt_domains values.
|
||||
*
|
||||
|
||||
@ -49,17 +49,15 @@ static void free_list(struct list_head *head)
|
||||
}
|
||||
|
||||
/**
|
||||
* add_to_list() - add a new resource tracker to the list
|
||||
* add_to_list() - Add a new resource tracker to the list
|
||||
* @head: Head of the list
|
||||
* @dev: device corresponding to which the resource
|
||||
* belongs
|
||||
* @res: The resource to be tracked
|
||||
* @add_size: additional size to be optionally added
|
||||
* to the resource
|
||||
* @dev: Device to which the resource belongs
|
||||
* @res: Resource to be tracked
|
||||
* @add_size: Additional size to be optionally added to the resource
|
||||
*/
|
||||
static int add_to_list(struct list_head *head,
|
||||
struct pci_dev *dev, struct resource *res,
|
||||
resource_size_t add_size, resource_size_t min_align)
|
||||
static int add_to_list(struct list_head *head, struct pci_dev *dev,
|
||||
struct resource *res, resource_size_t add_size,
|
||||
resource_size_t min_align)
|
||||
{
|
||||
struct pci_dev_resource *tmp;
|
||||
|
||||
@ -80,8 +78,7 @@ static int add_to_list(struct list_head *head,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void remove_from_list(struct list_head *head,
|
||||
struct resource *res)
|
||||
static void remove_from_list(struct list_head *head, struct resource *res)
|
||||
{
|
||||
struct pci_dev_resource *dev_res, *tmp;
|
||||
|
||||
@ -158,7 +155,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
|
||||
tmp->res = r;
|
||||
tmp->dev = dev;
|
||||
|
||||
/* fallback is smallest one or list is empty*/
|
||||
/* Fallback is smallest one or list is empty */
|
||||
n = head;
|
||||
list_for_each_entry(dev_res, head, list) {
|
||||
resource_size_t align;
|
||||
@ -171,21 +168,20 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Insert it just before n*/
|
||||
/* Insert it just before n */
|
||||
list_add_tail(&tmp->list, n);
|
||||
}
|
||||
}
|
||||
|
||||
static void __dev_sort_resources(struct pci_dev *dev,
|
||||
struct list_head *head)
|
||||
static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
|
||||
{
|
||||
u16 class = dev->class >> 8;
|
||||
|
||||
/* Don't touch classless devices or host bridges or ioapics. */
|
||||
/* Don't touch classless devices or host bridges or IOAPICs */
|
||||
if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
|
||||
return;
|
||||
|
||||
/* Don't touch ioapic devices already enabled by firmware */
|
||||
/* Don't touch IOAPIC devices already enabled by firmware */
|
||||
if (class == PCI_CLASS_SYSTEM_PIC) {
|
||||
u16 command;
|
||||
pci_read_config_word(dev, PCI_COMMAND, &command);
|
||||
@ -204,16 +200,15 @@ static inline void reset_resource(struct resource *res)
|
||||
}
|
||||
|
||||
/**
|
||||
* reassign_resources_sorted() - satisfy any additional resource requests
|
||||
* reassign_resources_sorted() - Satisfy any additional resource requests
|
||||
*
|
||||
* @realloc_head : head of the list tracking requests requiring additional
|
||||
* resources
|
||||
* @head : head of the list tracking requests with allocated
|
||||
* @realloc_head: Head of the list tracking requests requiring
|
||||
* additional resources
|
||||
* @head: Head of the list tracking requests with allocated
|
||||
* resources
|
||||
*
|
||||
* Walk through each element of the realloc_head and try to procure
|
||||
* additional resources for the element, provided the element
|
||||
* is in the head list.
|
||||
* Walk through each element of the realloc_head and try to procure additional
|
||||
* resources for the element, provided the element is in the head list.
|
||||
*/
|
||||
static void reassign_resources_sorted(struct list_head *realloc_head,
|
||||
struct list_head *head)
|
||||
@ -228,18 +223,18 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
|
||||
bool found_match = false;
|
||||
|
||||
res = add_res->res;
|
||||
/* skip resource that has been reset */
|
||||
/* Skip resource that has been reset */
|
||||
if (!res->flags)
|
||||
goto out;
|
||||
|
||||
/* skip this resource if not found in head list */
|
||||
/* Skip this resource if not found in head list */
|
||||
list_for_each_entry(dev_res, head, list) {
|
||||
if (dev_res->res == res) {
|
||||
found_match = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found_match)/* just skip */
|
||||
if (!found_match) /* Just skip */
|
||||
continue;
|
||||
|
||||
idx = res - &add_res->dev->resource[0];
|
||||
@ -266,14 +261,14 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
|
||||
}
|
||||
|
||||
/**
|
||||
* assign_requested_resources_sorted() - satisfy resource requests
|
||||
* assign_requested_resources_sorted() - Satisfy resource requests
|
||||
*
|
||||
* @head : head of the list tracking requests for resources
|
||||
* @fail_head : head of the list tracking requests that could
|
||||
* not be allocated
|
||||
* @head: Head of the list tracking requests for resources
|
||||
* @fail_head: Head of the list tracking requests that could not be
|
||||
* allocated
|
||||
*
|
||||
* Satisfy resource requests of each element in the list. Add
|
||||
* requests that could not satisfied to the failed_list.
|
||||
* Satisfy resource requests of each element in the list. Add requests that
|
||||
* could not be satisfied to the failed_list.
|
||||
*/
|
||||
static void assign_requested_resources_sorted(struct list_head *head,
|
||||
struct list_head *fail_head)
|
||||
@ -289,8 +284,9 @@ static void assign_requested_resources_sorted(struct list_head *head,
|
||||
pci_assign_resource(dev_res->dev, idx)) {
|
||||
if (fail_head) {
|
||||
/*
|
||||
* if the failed res is for ROM BAR, and it will
|
||||
* be enabled later, don't add it to the list
|
||||
* If the failed resource is a ROM BAR and
|
||||
* it will be enabled later, don't add it
|
||||
* to the list.
|
||||
*/
|
||||
if (!((idx == PCI_ROM_RESOURCE) &&
|
||||
(!(res->flags & IORESOURCE_ROM_ENABLE))))
|
||||
@ -309,15 +305,14 @@ static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
|
||||
struct pci_dev_resource *fail_res;
|
||||
unsigned long mask = 0;
|
||||
|
||||
/* check failed type */
|
||||
/* Check failed type */
|
||||
list_for_each_entry(fail_res, fail_head, list)
|
||||
mask |= fail_res->flags;
|
||||
|
||||
/*
|
||||
* one pref failed resource will set IORESOURCE_MEM,
|
||||
* as we can allocate pref in non-pref range.
|
||||
* Will release all assigned non-pref sibling resources
|
||||
* according to that bit.
|
||||
* One pref failed resource will set IORESOURCE_MEM, as we can
|
||||
* allocate pref in non-pref range. Will release all assigned
|
||||
* non-pref sibling resources according to that bit.
|
||||
*/
|
||||
return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
|
||||
}
|
||||
@ -327,11 +322,11 @@ static bool pci_need_to_release(unsigned long mask, struct resource *res)
|
||||
if (res->flags & IORESOURCE_IO)
|
||||
return !!(mask & IORESOURCE_IO);
|
||||
|
||||
/* check pref at first */
|
||||
/* Check pref at first */
|
||||
if (res->flags & IORESOURCE_PREFETCH) {
|
||||
if (mask & IORESOURCE_PREFETCH)
|
||||
return true;
|
||||
/* count pref if its parent is non-pref */
|
||||
/* Count pref if its parent is non-pref */
|
||||
else if ((mask & IORESOURCE_MEM) &&
|
||||
!(res->parent->flags & IORESOURCE_PREFETCH))
|
||||
return true;
|
||||
@ -342,7 +337,7 @@ static bool pci_need_to_release(unsigned long mask, struct resource *res)
|
||||
if (res->flags & IORESOURCE_MEM)
|
||||
return !!(mask & IORESOURCE_MEM);
|
||||
|
||||
return false; /* should not get here */
|
||||
return false; /* Should not get here */
|
||||
}
|
||||
|
||||
static void __assign_resources_sorted(struct list_head *head,
|
||||
@ -350,25 +345,25 @@ static void __assign_resources_sorted(struct list_head *head,
|
||||
struct list_head *fail_head)
|
||||
{
|
||||
/*
|
||||
* Should not assign requested resources at first.
|
||||
* they could be adjacent, so later reassign can not reallocate
|
||||
* them one by one in parent resource window.
|
||||
* Try to assign requested + add_size at beginning
|
||||
* if could do that, could get out early.
|
||||
* if could not do that, we still try to assign requested at first,
|
||||
* then try to reassign add_size for some resources.
|
||||
* Should not assign requested resources at first. They could be
|
||||
* adjacent, so later reassign can not reallocate them one by one in
|
||||
* parent resource window.
|
||||
*
|
||||
* Try to assign requested + add_size at beginning. If could do that,
|
||||
* could get out early. If could not do that, we still try to assign
|
||||
* requested at first, then try to reassign add_size for some resources.
|
||||
*
|
||||
* Separate three resource type checking if we need to release
|
||||
* assigned resource after requested + add_size try.
|
||||
* 1. if there is io port assign fail, will release assigned
|
||||
* io port.
|
||||
* 2. if there is pref mmio assign fail, release assigned
|
||||
* pref mmio.
|
||||
* if assigned pref mmio's parent is non-pref mmio and there
|
||||
* is non-pref mmio assign fail, will release that assigned
|
||||
* pref mmio.
|
||||
* 3. if there is non-pref mmio assign fail or pref mmio
|
||||
* assigned fail, will release assigned non-pref mmio.
|
||||
*
|
||||
* 1. If IO port assignment fails, will release assigned IO
|
||||
* port.
|
||||
* 2. If pref MMIO assignment fails, release assigned pref
|
||||
* MMIO. If assigned pref MMIO's parent is non-pref MMIO
|
||||
* and non-pref MMIO assignment fails, will release that
|
||||
* assigned pref MMIO.
|
||||
* 3. If non-pref MMIO assignment fails or pref MMIO
|
||||
* assignment fails, will release assigned non-pref MMIO.
|
||||
*/
|
||||
LIST_HEAD(save_head);
|
||||
LIST_HEAD(local_fail_head);
|
||||
@ -406,10 +401,10 @@ static void __assign_resources_sorted(struct list_head *head,
|
||||
add_align = get_res_add_align(realloc_head, dev_res->res);
|
||||
|
||||
/*
|
||||
* The "head" list is sorted by the alignment to make sure
|
||||
* resources with bigger alignment will be assigned first.
|
||||
* After we change the alignment of a dev_res in "head" list,
|
||||
* we need to reorder the list by alignment to make it
|
||||
* The "head" list is sorted by alignment so resources with
|
||||
* bigger alignment will be assigned first. After we
|
||||
* change the alignment of a dev_res in "head" list, we
|
||||
* need to reorder the list by alignment to make it
|
||||
* consistent.
|
||||
*/
|
||||
if (add_align > dev_res->res->start) {
|
||||
@ -434,7 +429,7 @@ static void __assign_resources_sorted(struct list_head *head,
|
||||
/* Try updated head list with add_size added */
|
||||
assign_requested_resources_sorted(head, &local_fail_head);
|
||||
|
||||
/* all assigned with add_size ? */
|
||||
/* All assigned with add_size? */
|
||||
if (list_empty(&local_fail_head)) {
|
||||
/* Remove head list from realloc_head list */
|
||||
list_for_each_entry(dev_res, head, list)
|
||||
@ -444,13 +439,13 @@ static void __assign_resources_sorted(struct list_head *head,
|
||||
return;
|
||||
}
|
||||
|
||||
/* check failed type */
|
||||
/* Check failed type */
|
||||
fail_type = pci_fail_res_type_mask(&local_fail_head);
|
||||
/* remove not need to be released assigned res from head list etc */
|
||||
/* Remove not need to be released assigned res from head list etc */
|
||||
list_for_each_entry_safe(dev_res, tmp_res, head, list)
|
||||
if (dev_res->res->parent &&
|
||||
!pci_need_to_release(fail_type, dev_res->res)) {
|
||||
/* remove it from realloc_head list */
|
||||
/* Remove it from realloc_head list */
|
||||
remove_from_list(realloc_head, dev_res->res);
|
||||
remove_from_list(&save_head, dev_res->res);
|
||||
list_del(&dev_res->list);
|
||||
@ -476,8 +471,7 @@ static void __assign_resources_sorted(struct list_head *head,
|
||||
/* Satisfy the must-have resource requests */
|
||||
assign_requested_resources_sorted(head, fail_head);
|
||||
|
||||
/* Try to satisfy any additional optional resource
|
||||
requests */
|
||||
/* Try to satisfy any additional optional resource requests */
|
||||
if (realloc_head)
|
||||
reassign_resources_sorted(realloc_head, head);
|
||||
free_list(head);
|
||||
@ -562,17 +556,19 @@ void pci_setup_cardbus(struct pci_bus *bus)
|
||||
}
|
||||
EXPORT_SYMBOL(pci_setup_cardbus);
|
||||
|
||||
/* Initialize bridges with base/limit values we have collected.
|
||||
PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
|
||||
requires that if there is no I/O ports or memory behind the
|
||||
bridge, corresponding range must be turned off by writing base
|
||||
value greater than limit to the bridge's base/limit registers.
|
||||
|
||||
Note: care must be taken when updating I/O base/limit registers
|
||||
of bridges which support 32-bit I/O. This update requires two
|
||||
config space writes, so it's quite possible that an I/O window of
|
||||
the bridge will have some undesirable address (e.g. 0) after the
|
||||
first write. Ditto 64-bit prefetchable MMIO. */
|
||||
/*
|
||||
* Initialize bridges with base/limit values we have collected. PCI-to-PCI
|
||||
* Bridge Architecture Specification rev. 1.1 (1998) requires that if there
|
||||
* are no I/O ports or memory behind the bridge, the corresponding range
|
||||
* must be turned off by writing base value greater than limit to the
|
||||
* bridge's base/limit registers.
|
||||
*
|
||||
* Note: care must be taken when updating I/O base/limit registers of
|
||||
* bridges which support 32-bit I/O. This update requires two config space
|
||||
* writes, so it's quite possible that an I/O window of the bridge will
|
||||
* have some undesirable address (e.g. 0) after the first write. Ditto
|
||||
* 64-bit prefetchable MMIO.
|
||||
*/
|
||||
static void pci_setup_bridge_io(struct pci_dev *bridge)
|
||||
{
|
||||
struct resource *res;
|
||||
@ -586,7 +582,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
|
||||
if (bridge->io_window_1k)
|
||||
io_mask = PCI_IO_1K_RANGE_MASK;
|
||||
|
||||
/* Set up the top and bottom of the PCI I/O segment for this bus. */
|
||||
/* Set up the top and bottom of the PCI I/O segment for this bus */
|
||||
res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
|
||||
pcibios_resource_to_bus(bridge->bus, ®ion, res);
|
||||
if (res->flags & IORESOURCE_IO) {
|
||||
@ -594,19 +590,19 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
|
||||
io_base_lo = (region.start >> 8) & io_mask;
|
||||
io_limit_lo = (region.end >> 8) & io_mask;
|
||||
l = ((u16) io_limit_lo << 8) | io_base_lo;
|
||||
/* Set up upper 16 bits of I/O base/limit. */
|
||||
/* Set up upper 16 bits of I/O base/limit */
|
||||
io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
|
||||
pci_info(bridge, " bridge window %pR\n", res);
|
||||
} else {
|
||||
/* Clear upper 16 bits of I/O base/limit. */
|
||||
/* Clear upper 16 bits of I/O base/limit */
|
||||
io_upper16 = 0;
|
||||
l = 0x00f0;
|
||||
}
|
||||
/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
|
||||
/* Temporarily disable the I/O range before updating PCI_IO_BASE */
|
||||
pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
|
||||
/* Update lower 16 bits of I/O base/limit. */
|
||||
/* Update lower 16 bits of I/O base/limit */
|
||||
pci_write_config_word(bridge, PCI_IO_BASE, l);
|
||||
/* Update upper 16 bits of I/O base/limit. */
|
||||
/* Update upper 16 bits of I/O base/limit */
|
||||
pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
|
||||
}
|
||||
|
||||
@ -616,7 +612,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge)
|
||||
struct pci_bus_region region;
|
||||
u32 l;
|
||||
|
||||
/* Set up the top and bottom of the PCI Memory segment for this bus. */
|
||||
/* Set up the top and bottom of the PCI Memory segment for this bus */
|
||||
res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
|
||||
pcibios_resource_to_bus(bridge->bus, ®ion, res);
|
||||
if (res->flags & IORESOURCE_MEM) {
|
||||
@ -635,12 +631,14 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
|
||||
struct pci_bus_region region;
|
||||
u32 l, bu, lu;
|
||||
|
||||
/* Clear out the upper 32 bits of PREF limit.
|
||||
If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
|
||||
disables PREF range, which is ok. */
|
||||
/*
|
||||
* Clear out the upper 32 bits of PREF limit. If
|
||||
* PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
|
||||
* PREF range, which is ok.
|
||||
*/
|
||||
pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
|
||||
|
||||
/* Set up PREF base/limit. */
|
||||
/* Set up PREF base/limit */
|
||||
bu = lu = 0;
|
||||
res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
|
||||
pcibios_resource_to_bus(bridge->bus, ®ion, res);
|
||||
@ -657,7 +655,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
|
||||
}
|
||||
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
|
||||
|
||||
/* Set the upper 32 bits of PREF base & limit. */
|
||||
/* Set the upper 32 bits of PREF base & limit */
|
||||
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
|
||||
pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
|
||||
}
|
||||
@ -701,13 +699,13 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
|
||||
return 0;
|
||||
|
||||
if (pci_claim_resource(bridge, i) == 0)
|
||||
return 0; /* claimed the window */
|
||||
return 0; /* Claimed the window */
|
||||
|
||||
if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
|
||||
return 0;
|
||||
|
||||
if (!pci_bus_clip_resource(bridge, i))
|
||||
return -EINVAL; /* clipping didn't change anything */
|
||||
return -EINVAL; /* Clipping didn't change anything */
|
||||
|
||||
switch (i - PCI_BRIDGE_RESOURCES) {
|
||||
case 0:
|
||||
@ -724,14 +722,16 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
|
||||
}
|
||||
|
||||
if (pci_claim_resource(bridge, i) == 0)
|
||||
return 0; /* claimed a smaller window */
|
||||
return 0; /* Claimed a smaller window */
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Check whether the bridge supports optional I/O and
|
||||
prefetchable memory ranges. If not, the respective
|
||||
base/limit registers must be read-only and read as 0. */
|
||||
/*
|
||||
* Check whether the bridge supports optional I/O and prefetchable memory
|
||||
* ranges. If not, the respective base/limit registers must be read-only
|
||||
* and read as 0.
|
||||
*/
|
||||
static void pci_bridge_check_ranges(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *bridge = bus->self;
|
||||
@ -751,12 +751,14 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
|
||||
}
|
||||
}
|
||||
|
||||
/* Helper function for sizing routines: find first available
|
||||
bus resource of a given type. Note: we intentionally skip
|
||||
the bus resources which have already been assigned (that is,
|
||||
have non-NULL parent resource). */
|
||||
/*
|
||||
* Helper function for sizing routines: find first available bus resource
|
||||
* of a given type. Note: we intentionally skip the bus resources which
|
||||
* have already been assigned (that is, have non-NULL parent resource).
|
||||
*/
|
||||
static struct resource *find_free_bus_resource(struct pci_bus *bus,
|
||||
unsigned long type_mask, unsigned long type)
|
||||
unsigned long type_mask,
|
||||
unsigned long type)
|
||||
{
|
||||
int i;
|
||||
struct resource *r;
|
||||
@ -782,8 +784,10 @@ static resource_size_t calculate_iosize(resource_size_t size,
|
||||
size = min_size;
|
||||
if (old_size == 1)
|
||||
old_size = 0;
|
||||
/* To be fixed in 2.5: we should have sort of HAVE_ISA
|
||||
flag in the struct pci_bus. */
|
||||
/*
|
||||
* To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
|
||||
* struct pci_bus.
|
||||
*/
|
||||
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
|
||||
size = (size & 0xff) + ((size & ~0xffUL) << 2);
|
||||
#endif
|
||||
@ -823,8 +827,7 @@ resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
|
||||
#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
|
||||
#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
|
||||
|
||||
static resource_size_t window_alignment(struct pci_bus *bus,
|
||||
unsigned long type)
|
||||
static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
|
||||
{
|
||||
resource_size_t align = 1, arch_align;
|
||||
|
||||
@ -832,8 +835,8 @@ static resource_size_t window_alignment(struct pci_bus *bus,
|
||||
align = PCI_P2P_DEFAULT_MEM_ALIGN;
|
||||
else if (type & IORESOURCE_IO) {
|
||||
/*
|
||||
* Per spec, I/O windows are 4K-aligned, but some
|
||||
* bridges have an extension to support 1K alignment.
|
||||
* Per spec, I/O windows are 4K-aligned, but some bridges have
|
||||
* an extension to support 1K alignment.
|
||||
*/
|
||||
if (bus->self->io_window_1k)
|
||||
align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
|
||||
@ -846,20 +849,21 @@ static resource_size_t window_alignment(struct pci_bus *bus,
|
||||
}
|
||||
|
||||
/**
|
||||
* pbus_size_io() - size the io window of a given bus
|
||||
* pbus_size_io() - Size the I/O window of a given bus
|
||||
*
|
||||
* @bus : the bus
|
||||
* @min_size : the minimum io window that must to be allocated
|
||||
* @add_size : additional optional io window
|
||||
* @realloc_head : track the additional io window on this list
|
||||
* @bus: The bus
|
||||
* @min_size: The minimum I/O window that must be allocated
|
||||
* @add_size: Additional optional I/O window
|
||||
* @realloc_head: Track the additional I/O window on this list
|
||||
*
|
||||
* Sizing the IO windows of the PCI-PCI bridge is trivial,
|
||||
* since these windows have 1K or 4K granularity and the IO ranges
|
||||
* of non-bridge PCI devices are limited to 256 bytes.
|
||||
* We must be careful with the ISA aliasing though.
|
||||
* Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
|
||||
* windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
|
||||
* devices are limited to 256 bytes. We must be careful with the ISA
|
||||
* aliasing though.
|
||||
*/
|
||||
static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
|
||||
resource_size_t add_size, struct list_head *realloc_head)
|
||||
resource_size_t add_size,
|
||||
struct list_head *realloc_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
|
||||
@ -946,33 +950,33 @@ static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
|
||||
}
|
||||
|
||||
/**
|
||||
* pbus_size_mem() - size the memory window of a given bus
|
||||
* pbus_size_mem() - Size the memory window of a given bus
|
||||
*
|
||||
* @bus : the bus
|
||||
* @mask: mask the resource flag, then compare it with type
|
||||
* @type: the type of free resource from bridge
|
||||
* @type2: second match type
|
||||
* @type3: third match type
|
||||
* @min_size : the minimum memory window that must to be allocated
|
||||
* @add_size : additional optional memory window
|
||||
* @realloc_head : track the additional memory window on this list
|
||||
* @bus: The bus
|
||||
* @mask: Mask the resource flag, then compare it with type
|
||||
* @type: The type of free resource from bridge
|
||||
* @type2: Second match type
|
||||
* @type3: Third match type
|
||||
* @min_size: The minimum memory window that must be allocated
|
||||
* @add_size: Additional optional memory window
|
||||
* @realloc_head: Track the additional memory window on this list
|
||||
*
|
||||
* Calculate the size of the bus and minimal alignment which
|
||||
* guarantees that all child resources fit in this size.
|
||||
* Calculate the size of the bus and minimal alignment which guarantees
|
||||
* that all child resources fit in this size.
|
||||
*
|
||||
* Returns -ENOSPC if there's no available bus resource of the desired type.
|
||||
* Otherwise, sets the bus resource start/end to indicate the required
|
||||
* size, adds things to realloc_head (if supplied), and returns 0.
|
||||
* Return -ENOSPC if there's no available bus resource of the desired
|
||||
* type. Otherwise, set the bus resource start/end to indicate the
|
||||
* required size, add things to realloc_head (if supplied), and return 0.
|
||||
*/
|
||||
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
unsigned long type, unsigned long type2,
|
||||
unsigned long type3,
|
||||
resource_size_t min_size, resource_size_t add_size,
|
||||
unsigned long type3, resource_size_t min_size,
|
||||
resource_size_t add_size,
|
||||
struct list_head *realloc_head)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
resource_size_t min_align, align, size, size0, size1;
|
||||
resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
|
||||
resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
|
||||
int order, max_order;
|
||||
struct resource *b_res = find_free_bus_resource(bus,
|
||||
mask | IORESOURCE_PREFETCH, type);
|
||||
@ -1001,12 +1005,12 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
continue;
|
||||
r_size = resource_size(r);
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
/* put SRIOV requested res to the optional list */
|
||||
/* Put SRIOV requested res to the optional list */
|
||||
if (realloc_head && i >= PCI_IOV_RESOURCES &&
|
||||
i <= PCI_IOV_RESOURCE_END) {
|
||||
add_align = max(pci_resource_alignment(dev, r), add_align);
|
||||
r->end = r->start - 1;
|
||||
add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
|
||||
add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
|
||||
children_add_size += r_size;
|
||||
continue;
|
||||
}
|
||||
@ -1028,8 +1032,10 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
|
||||
continue;
|
||||
}
|
||||
size += max(r_size, align);
|
||||
/* Exclude ranges with size > align from
|
||||
calculation of the alignment. */
|
||||
/*
|
||||
* Exclude ranges with size > align from calculation of
|
||||
* the alignment.
|
||||
*/
|
||||
if (r_size <= align)
|
||||
aligns[order] += align;
|
||||
if (order > max_order)
|
||||
@ -1090,8 +1096,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
if (b_res[0].parent)
|
||||
goto handle_b_res_1;
|
||||
/*
|
||||
* Reserve some resources for CardBus. We reserve
|
||||
* a fixed amount of bus space for CardBus bridges.
|
||||
* Reserve some resources for CardBus. We reserve a fixed amount
|
||||
* of bus space for CardBus bridges.
|
||||
*/
|
||||
b_res[0].start = pci_cardbus_io_size;
|
||||
b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
|
||||
@ -1115,7 +1121,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
}
|
||||
|
||||
handle_b_res_2:
|
||||
/* MEM1 must not be pref mmio */
|
||||
/* MEM1 must not be pref MMIO */
|
||||
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
|
||||
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
|
||||
ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
|
||||
@ -1123,10 +1129,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check whether prefetchable memory is supported
|
||||
* by this bridge.
|
||||
*/
|
||||
/* Check whether prefetchable memory is supported by this bridge. */
|
||||
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
|
||||
if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
|
||||
ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
|
||||
@ -1137,9 +1140,8 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
if (b_res[2].parent)
|
||||
goto handle_b_res_3;
|
||||
/*
|
||||
* If we have prefetchable memory support, allocate
|
||||
* two regions. Otherwise, allocate one region of
|
||||
* twice the size.
|
||||
* If we have prefetchable memory support, allocate two regions.
|
||||
* Otherwise, allocate one region of twice the size.
|
||||
*/
|
||||
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
|
||||
b_res[2].start = pci_cardbus_mem_size;
|
||||
@ -1152,7 +1154,7 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
||||
pci_cardbus_mem_size, pci_cardbus_mem_size);
|
||||
}
|
||||
|
||||
/* reduce that to half */
|
||||
/* Reduce that to half */
|
||||
b_res_3_size = pci_cardbus_mem_size;
|
||||
}
|
||||
|
||||
@ -1203,7 +1205,7 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
|
||||
|
||||
switch (bus->self->hdr_type) {
|
||||
case PCI_HEADER_TYPE_CARDBUS:
|
||||
/* don't size cardbuses yet. */
|
||||
/* Don't size CardBuses yet */
|
||||
break;
|
||||
|
||||
case PCI_HEADER_TYPE_BRIDGE:
|
||||
@ -1275,13 +1277,12 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
|
||||
* - all non-prefetchable resources
|
||||
* - 32-bit prefetchable resources if there's a 64-bit
|
||||
* prefetchable window or no prefetchable window at all
|
||||
* - 64-bit prefetchable resources if there's no
|
||||
* prefetchable window at all
|
||||
* - 64-bit prefetchable resources if there's no prefetchable
|
||||
* window at all
|
||||
*
|
||||
* Note that the strategy in __pci_assign_resource() must
|
||||
* match that used here. Specifically, we cannot put a
|
||||
* 32-bit prefetchable resource in a 64-bit prefetchable
|
||||
* window.
|
||||
* Note that the strategy in __pci_assign_resource() must match
|
||||
* that used here. Specifically, we cannot put a 32-bit
|
||||
* prefetchable resource in a 64-bit prefetchable window.
|
||||
*/
|
||||
pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
|
||||
realloc_head ? 0 : additional_mem_size,
|
||||
@ -1314,8 +1315,8 @@ static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
|
||||
}
|
||||
|
||||
/*
|
||||
* Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
|
||||
* are skipped by pbus_assign_resources_sorted().
|
||||
* Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
|
||||
* skipped by pbus_assign_resources_sorted().
|
||||
*/
|
||||
static void pdev_assign_fixed_resources(struct pci_dev *dev)
|
||||
{
|
||||
@ -1426,10 +1427,9 @@ static void pci_bus_allocate_resources(struct pci_bus *b)
|
||||
struct pci_bus *child;
|
||||
|
||||
/*
|
||||
* Carry out a depth-first search on the PCI bus
|
||||
* tree to allocate bridge apertures. Read the
|
||||
* programmed bridge bases and recursively claim
|
||||
* the respective bridge resources.
|
||||
* Carry out a depth-first search on the PCI bus tree to allocate
|
||||
* bridge apertures. Read the programmed bridge bases and
|
||||
* recursively claim the respective bridge resources.
|
||||
*/
|
||||
if (b->self) {
|
||||
pci_read_bridge_bases(b);
|
||||
@ -1494,16 +1494,14 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
|
||||
b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
|
||||
|
||||
/*
|
||||
* 1. if there is io port assign fail, will release bridge
|
||||
* io port.
|
||||
* 2. if there is non pref mmio assign fail, release bridge
|
||||
* nonpref mmio.
|
||||
* 3. if there is 64bit pref mmio assign fail, and bridge pref
|
||||
* is 64bit, release bridge pref mmio.
|
||||
* 4. if there is pref mmio assign fail, and bridge pref is
|
||||
* 32bit mmio, release bridge pref mmio
|
||||
* 5. if there is pref mmio assign fail, and bridge pref is not
|
||||
* assigned, release bridge nonpref mmio.
|
||||
* 1. If IO port assignment fails, release bridge IO port.
|
||||
* 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
|
||||
* 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
|
||||
* release bridge pref MMIO.
|
||||
* 4. If pref MMIO assignment fails, and bridge pref is 32bit,
|
||||
* release bridge pref MMIO.
|
||||
* 5. If pref MMIO assignment fails, and bridge pref is not
|
||||
* assigned, release bridge nonpref MMIO.
|
||||
*/
|
||||
if (type & IORESOURCE_IO)
|
||||
idx = 0;
|
||||
@ -1523,25 +1521,22 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
|
||||
if (!r->parent)
|
||||
return;
|
||||
|
||||
/*
|
||||
* if there are children under that, we should release them
|
||||
* all
|
||||
*/
|
||||
/* If there are children, release them all */
|
||||
release_child_resources(r);
|
||||
if (!release_resource(r)) {
|
||||
type = old_flags = r->flags & PCI_RES_TYPE_MASK;
|
||||
pci_info(dev, "resource %d %pR released\n",
|
||||
PCI_BRIDGE_RESOURCES + idx, r);
|
||||
/* keep the old size */
|
||||
/* Keep the old size */
|
||||
r->end = resource_size(r) - 1;
|
||||
r->start = 0;
|
||||
r->flags = 0;
|
||||
|
||||
/* avoiding touch the one without PREF */
|
||||
/* Avoiding touch the one without PREF */
|
||||
if (type & IORESOURCE_PREFETCH)
|
||||
type = IORESOURCE_PREFETCH;
|
||||
__pci_setup_bridge(bus, type);
|
||||
/* for next child res under same bridge */
|
||||
/* For next child res under same bridge */
|
||||
r->flags = old_flags;
|
||||
}
|
||||
}
|
||||
@ -1550,9 +1545,10 @@ enum release_type {
|
||||
leaf_only,
|
||||
whole_subtree,
|
||||
};
|
||||
|
||||
/*
|
||||
* try to release pci bridge resources that is from leaf bridge,
|
||||
* so we can allocate big new one later
|
||||
* Try to release PCI bridge resources from leaf bridge, so we can allocate
|
||||
* a larger window later.
|
||||
*/
|
||||
static void pci_bus_release_bridge_resources(struct pci_bus *bus,
|
||||
unsigned long type,
|
||||
@ -1677,7 +1673,7 @@ static int iov_resources_unassigned(struct pci_dev *dev, void *data)
|
||||
pcibios_resource_to_bus(dev->bus, ®ion, r);
|
||||
if (!region.start) {
|
||||
*unassigned = true;
|
||||
return 1; /* return early from pci_walk_bus() */
|
||||
return 1; /* Return early from pci_walk_bus() */
|
||||
}
|
||||
}
|
||||
|
||||
@ -1707,14 +1703,14 @@ static enum enable_type pci_realloc_detect(struct pci_bus *bus,
|
||||
#endif
|
||||
|
||||
/*
|
||||
* first try will not touch pci bridge res
|
||||
* second and later try will clear small leaf bridge res
|
||||
* will stop till to the max depth if can not find good one
|
||||
* First try will not touch PCI bridge res.
|
||||
* Second and later try will clear small leaf bridge res.
|
||||
* Will stop till to the max depth if can not find good one.
|
||||
*/
|
||||
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
{
|
||||
LIST_HEAD(realloc_head); /* list of resources that
|
||||
want additional resources */
|
||||
LIST_HEAD(realloc_head);
|
||||
/* List of resources that want additional resources */
|
||||
struct list_head *add_list = NULL;
|
||||
int tried_times = 0;
|
||||
enum release_type rel_type = leaf_only;
|
||||
@ -1723,7 +1719,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
int pci_try_num = 1;
|
||||
enum enable_type enable_local;
|
||||
|
||||
/* don't realloc if asked to do so */
|
||||
/* Don't realloc if asked to do so */
|
||||
enable_local = pci_realloc_detect(bus, pci_realloc_enable);
|
||||
if (pci_realloc_enabled(enable_local)) {
|
||||
int max_depth = pci_bus_get_depth(bus);
|
||||
@ -1735,13 +1731,14 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
|
||||
again:
|
||||
/*
|
||||
* last try will use add_list, otherwise will try good to have as
|
||||
* must have, so can realloc parent bridge resource
|
||||
* Last try will use add_list, otherwise will try good to have as must
|
||||
* have, so can realloc parent bridge resource
|
||||
*/
|
||||
if (tried_times + 1 == pci_try_num)
|
||||
add_list = &realloc_head;
|
||||
/* Depth first, calculate sizes and alignments of all
|
||||
subordinate buses. */
|
||||
/*
|
||||
* Depth first, calculate sizes and alignments of all subordinate buses.
|
||||
*/
|
||||
__pci_bus_size_bridges(bus, add_list);
|
||||
|
||||
/* Depth last, allocate resources and update the hardware. */
|
||||
@ -1750,7 +1747,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
BUG_ON(!list_empty(add_list));
|
||||
tried_times++;
|
||||
|
||||
/* any device complain? */
|
||||
/* Any device complain? */
|
||||
if (list_empty(&fail_head))
|
||||
goto dump;
|
||||
|
||||
@ -1767,20 +1764,20 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
|
||||
tried_times + 1);
|
||||
|
||||
/* third times and later will not check if it is leaf */
|
||||
/* Third times and later will not check if it is leaf */
|
||||
if ((tried_times + 1) > 2)
|
||||
rel_type = whole_subtree;
|
||||
|
||||
/*
|
||||
* Try to release leaf bridge's resources that doesn't fit resource of
|
||||
* child device under that bridge
|
||||
* child device under that bridge.
|
||||
*/
|
||||
list_for_each_entry(fail_res, &fail_head, list)
|
||||
pci_bus_release_bridge_resources(fail_res->dev->bus,
|
||||
fail_res->flags & PCI_RES_TYPE_MASK,
|
||||
rel_type);
|
||||
|
||||
/* restore size and flags */
|
||||
/* Restore size and flags */
|
||||
list_for_each_entry(fail_res, &fail_head, list) {
|
||||
struct resource *res = fail_res->res;
|
||||
|
||||
@ -1795,7 +1792,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
|
||||
goto again;
|
||||
|
||||
dump:
|
||||
/* dump the resource on buses */
|
||||
/* Dump the resource on buses */
|
||||
pci_bus_dump_resources(bus);
|
||||
}
|
||||
|
||||
@ -1806,14 +1803,15 @@ void __init pci_assign_unassigned_resources(void)
|
||||
list_for_each_entry(root_bus, &pci_root_buses, node) {
|
||||
pci_assign_unassigned_root_bus_resources(root_bus);
|
||||
|
||||
/* Make sure the root bridge has a companion ACPI device: */
|
||||
/* Make sure the root bridge has a companion ACPI device */
|
||||
if (ACPI_HANDLE(root_bus->bridge))
|
||||
acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
|
||||
}
|
||||
}
|
||||
|
||||
static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
|
||||
struct list_head *add_list, resource_size_t available)
|
||||
struct list_head *add_list,
|
||||
resource_size_t available)
|
||||
{
|
||||
struct pci_dev_resource *dev_res;
|
||||
|
||||
@ -1837,8 +1835,10 @@ static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
|
||||
}
|
||||
|
||||
static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
||||
struct list_head *add_list, resource_size_t available_io,
|
||||
resource_size_t available_mmio, resource_size_t available_mmio_pref)
|
||||
struct list_head *add_list,
|
||||
resource_size_t available_io,
|
||||
resource_size_t available_mmio,
|
||||
resource_size_t available_mmio_pref)
|
||||
{
|
||||
resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
|
||||
unsigned int normal_bridges = 0, hotplug_bridges = 0;
|
||||
@ -1907,8 +1907,8 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
||||
|
||||
/*
|
||||
* There is only one bridge on the bus so it gets all available
|
||||
* resources which it can then distribute to the possible
|
||||
* hotplug bridges below.
|
||||
* resources which it can then distribute to the possible hotplug
|
||||
* bridges below.
|
||||
*/
|
||||
if (hotplug_bridges + normal_bridges == 1) {
|
||||
dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
|
||||
@ -1959,8 +1959,7 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
pci_bridge_distribute_available_resources(struct pci_dev *bridge,
|
||||
static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
|
||||
struct list_head *add_list)
|
||||
{
|
||||
resource_size_t available_io, available_mmio, available_mmio_pref;
|
||||
@ -1978,14 +1977,17 @@ pci_bridge_distribute_available_resources(struct pci_dev *bridge,
|
||||
available_mmio_pref = resource_size(res);
|
||||
|
||||
pci_bus_distribute_available_resources(bridge->subordinate,
|
||||
add_list, available_io, available_mmio, available_mmio_pref);
|
||||
add_list, available_io,
|
||||
available_mmio,
|
||||
available_mmio_pref);
|
||||
}
|
||||
|
||||
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
|
||||
{
|
||||
struct pci_bus *parent = bridge->subordinate;
|
||||
LIST_HEAD(add_list); /* list of resources that
|
||||
want additional resources */
|
||||
/* List of resources that want additional resources */
|
||||
LIST_HEAD(add_list);
|
||||
|
||||
int tried_times = 0;
|
||||
LIST_HEAD(fail_head);
|
||||
struct pci_dev_resource *fail_res;
|
||||
@ -1995,9 +1997,9 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
|
||||
__pci_bus_size_bridges(parent, &add_list);
|
||||
|
||||
/*
|
||||
* Distribute remaining resources (if any) equally between
|
||||
* hotplug bridges below. This makes it possible to extend the
|
||||
* hierarchy later without running out of resources.
|
||||
* Distribute remaining resources (if any) equally between hotplug
|
||||
* bridges below. This makes it possible to extend the hierarchy
|
||||
* later without running out of resources.
|
||||
*/
|
||||
pci_bridge_distribute_available_resources(bridge, &add_list);
|
||||
|
||||
@ -2009,7 +2011,7 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
|
||||
goto enable_all;
|
||||
|
||||
if (tried_times >= 2) {
|
||||
/* still fail, don't need to try more */
|
||||
/* Still fail, don't need to try more */
|
||||
free_list(&fail_head);
|
||||
goto enable_all;
|
||||
}
|
||||
@ -2018,15 +2020,15 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
|
||||
tried_times + 1);
|
||||
|
||||
/*
|
||||
* Try to release leaf bridge's resources that doesn't fit resource of
|
||||
* child device under that bridge
|
||||
* Try to release leaf bridge's resources that aren't big enough
|
||||
* to contain child device resources.
|
||||
*/
|
||||
list_for_each_entry(fail_res, &fail_head, list)
|
||||
pci_bus_release_bridge_resources(fail_res->dev->bus,
|
||||
fail_res->flags & PCI_RES_TYPE_MASK,
|
||||
whole_subtree);
|
||||
|
||||
/* restore size and flags */
|
||||
/* Restore size and flags */
|
||||
list_for_each_entry(fail_res, &fail_head, list) {
|
||||
struct resource *res = fail_res->res;
|
||||
|
||||
@ -2105,7 +2107,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
|
||||
}
|
||||
|
||||
list_for_each_entry(dev_res, &saved, list) {
|
||||
/* Skip the bridge we just assigned resources for. */
|
||||
/* Skip the bridge we just assigned resources for */
|
||||
if (bridge == dev_res->dev)
|
||||
continue;
|
||||
|
||||
@ -2117,7 +2119,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
/* restore size and flags */
|
||||
/* Restore size and flags */
|
||||
list_for_each_entry(dev_res, &failed, list) {
|
||||
struct resource *res = dev_res->res;
|
||||
|
||||
@ -2149,8 +2151,8 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
|
||||
void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
LIST_HEAD(add_list); /* list of resources that
|
||||
want additional resources */
|
||||
/* List of resources that want additional resources */
|
||||
LIST_HEAD(add_list);
|
||||
|
||||
down_read(&pci_bus_sem);
|
||||
for_each_pci_bridge(dev, bus)
|
||||
|
||||
@ -44,7 +44,7 @@
|
||||
*/
|
||||
#define CPER_REC_LEN 256
|
||||
/*
|
||||
* Severity difinition for error_severity in struct cper_record_header
|
||||
* Severity definition for error_severity in struct cper_record_header
|
||||
* and section_severity in struct cper_section_descriptor
|
||||
*/
|
||||
enum {
|
||||
@ -55,24 +55,21 @@ enum {
|
||||
};
|
||||
|
||||
/*
|
||||
* Validation bits difinition for validation_bits in struct
|
||||
* Validation bits definition for validation_bits in struct
|
||||
* cper_record_header. If set, corresponding fields in struct
|
||||
* cper_record_header contain valid information.
|
||||
*
|
||||
* corresponds platform_id
|
||||
*/
|
||||
#define CPER_VALID_PLATFORM_ID 0x0001
|
||||
/* corresponds timestamp */
|
||||
#define CPER_VALID_TIMESTAMP 0x0002
|
||||
/* corresponds partition_id */
|
||||
#define CPER_VALID_PARTITION_ID 0x0004
|
||||
|
||||
/*
|
||||
* Notification type used to generate error record, used in
|
||||
* notification_type in struct cper_record_header
|
||||
*
|
||||
* Corrected Machine Check
|
||||
* notification_type in struct cper_record_header. These UUIDs are defined
|
||||
* in the UEFI spec v2.7, sec N.2.1.
|
||||
*/
|
||||
|
||||
/* Corrected Machine Check */
|
||||
#define CPER_NOTIFY_CMC \
|
||||
GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \
|
||||
0xEB, 0xD4, 0xF8, 0x90)
|
||||
@ -122,14 +119,11 @@ enum {
|
||||
#define CPER_SEC_REV 0x0100
|
||||
|
||||
/*
|
||||
* Validation bits difinition for validation_bits in struct
|
||||
* Validation bits definition for validation_bits in struct
|
||||
* cper_section_descriptor. If set, corresponding fields in struct
|
||||
* cper_section_descriptor contain valid information.
|
||||
*
|
||||
* corresponds fru_id
|
||||
*/
|
||||
#define CPER_SEC_VALID_FRU_ID 0x1
|
||||
/* corresponds fru_text */
|
||||
#define CPER_SEC_VALID_FRU_TEXT 0x2
|
||||
|
||||
/*
|
||||
@ -165,10 +159,11 @@ enum {
|
||||
|
||||
/*
|
||||
* Section type definitions, used in section_type field in struct
|
||||
* cper_section_descriptor
|
||||
*
|
||||
* Processor Generic
|
||||
* cper_section_descriptor. These UUIDs are defined in the UEFI spec
|
||||
* v2.7, sec N.2.2.
|
||||
*/
|
||||
|
||||
/* Processor Generic */
|
||||
#define CPER_SEC_PROC_GENERIC \
|
||||
GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1, \
|
||||
0x93, 0xC4, 0xF3, 0xDB)
|
||||
@ -325,220 +320,223 @@ enum {
|
||||
*/
|
||||
#pragma pack(1)
|
||||
|
||||
/* Record Header, UEFI v2.7 sec N.2.1 */
|
||||
struct cper_record_header {
|
||||
char signature[CPER_SIG_SIZE]; /* must be CPER_SIG_RECORD */
|
||||
__u16 revision; /* must be CPER_RECORD_REV */
|
||||
__u32 signature_end; /* must be CPER_SIG_END */
|
||||
__u16 section_count;
|
||||
__u32 error_severity;
|
||||
__u32 validation_bits;
|
||||
__u32 record_length;
|
||||
__u64 timestamp;
|
||||
u16 revision; /* must be CPER_RECORD_REV */
|
||||
u32 signature_end; /* must be CPER_SIG_END */
|
||||
u16 section_count;
|
||||
u32 error_severity;
|
||||
u32 validation_bits;
|
||||
u32 record_length;
|
||||
u64 timestamp;
|
||||
guid_t platform_id;
|
||||
guid_t partition_id;
|
||||
guid_t creator_id;
|
||||
guid_t notification_type;
|
||||
__u64 record_id;
|
||||
__u32 flags;
|
||||
__u64 persistence_information;
|
||||
__u8 reserved[12]; /* must be zero */
|
||||
u64 record_id;
|
||||
u32 flags;
|
||||
u64 persistence_information;
|
||||
u8 reserved[12]; /* must be zero */
|
||||
};
|
||||
|
||||
/* Section Descriptor, UEFI v2.7 sec N.2.2 */
|
||||
struct cper_section_descriptor {
|
||||
__u32 section_offset; /* Offset in bytes of the
|
||||
u32 section_offset; /* Offset in bytes of the
|
||||
* section body from the base
|
||||
* of the record header */
|
||||
__u32 section_length;
|
||||
__u16 revision; /* must be CPER_RECORD_REV */
|
||||
__u8 validation_bits;
|
||||
__u8 reserved; /* must be zero */
|
||||
__u32 flags;
|
||||
u32 section_length;
|
||||
u16 revision; /* must be CPER_RECORD_REV */
|
||||
u8 validation_bits;
|
||||
u8 reserved; /* must be zero */
|
||||
u32 flags;
|
||||
guid_t section_type;
|
||||
guid_t fru_id;
|
||||
__u32 section_severity;
|
||||
__u8 fru_text[20];
|
||||
u32 section_severity;
|
||||
u8 fru_text[20];
|
||||
};
|
||||
|
||||
/* Generic Processor Error Section */
|
||||
/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */
|
||||
struct cper_sec_proc_generic {
|
||||
__u64 validation_bits;
|
||||
__u8 proc_type;
|
||||
__u8 proc_isa;
|
||||
__u8 proc_error_type;
|
||||
__u8 operation;
|
||||
__u8 flags;
|
||||
__u8 level;
|
||||
__u16 reserved;
|
||||
__u64 cpu_version;
|
||||
u64 validation_bits;
|
||||
u8 proc_type;
|
||||
u8 proc_isa;
|
||||
u8 proc_error_type;
|
||||
u8 operation;
|
||||
u8 flags;
|
||||
u8 level;
|
||||
u16 reserved;
|
||||
u64 cpu_version;
|
||||
char cpu_brand[128];
|
||||
__u64 proc_id;
|
||||
__u64 target_addr;
|
||||
__u64 requestor_id;
|
||||
__u64 responder_id;
|
||||
__u64 ip;
|
||||
u64 proc_id;
|
||||
u64 target_addr;
|
||||
u64 requestor_id;
|
||||
u64 responder_id;
|
||||
u64 ip;
|
||||
};
|
||||
|
||||
/* IA32/X64 Processor Error Section */
|
||||
/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */
|
||||
struct cper_sec_proc_ia {
|
||||
__u64 validation_bits;
|
||||
__u64 lapic_id;
|
||||
__u8 cpuid[48];
|
||||
u64 validation_bits;
|
||||
u64 lapic_id;
|
||||
u8 cpuid[48];
|
||||
};
|
||||
|
||||
/* IA32/X64 Processor Error Information Structure */
|
||||
/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */
|
||||
struct cper_ia_err_info {
|
||||
guid_t err_type;
|
||||
__u64 validation_bits;
|
||||
__u64 check_info;
|
||||
__u64 target_id;
|
||||
__u64 requestor_id;
|
||||
__u64 responder_id;
|
||||
__u64 ip;
|
||||
u64 validation_bits;
|
||||
u64 check_info;
|
||||
u64 target_id;
|
||||
u64 requestor_id;
|
||||
u64 responder_id;
|
||||
u64 ip;
|
||||
};
|
||||
|
||||
/* IA32/X64 Processor Context Information Structure */
|
||||
/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */
|
||||
struct cper_ia_proc_ctx {
|
||||
__u16 reg_ctx_type;
|
||||
__u16 reg_arr_size;
|
||||
__u32 msr_addr;
|
||||
__u64 mm_reg_addr;
|
||||
u16 reg_ctx_type;
|
||||
u16 reg_arr_size;
|
||||
u32 msr_addr;
|
||||
u64 mm_reg_addr;
|
||||
};
|
||||
|
||||
/* ARM Processor Error Section */
|
||||
/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */
|
||||
struct cper_sec_proc_arm {
|
||||
__u32 validation_bits;
|
||||
__u16 err_info_num; /* Number of Processor Error Info */
|
||||
__u16 context_info_num; /* Number of Processor Context Info Records*/
|
||||
__u32 section_length;
|
||||
__u8 affinity_level;
|
||||
__u8 reserved[3]; /* must be zero */
|
||||
__u64 mpidr;
|
||||
__u64 midr;
|
||||
__u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
|
||||
__u32 psci_state;
|
||||
u32 validation_bits;
|
||||
u16 err_info_num; /* Number of Processor Error Info */
|
||||
u16 context_info_num; /* Number of Processor Context Info Records*/
|
||||
u32 section_length;
|
||||
u8 affinity_level;
|
||||
u8 reserved[3]; /* must be zero */
|
||||
u64 mpidr;
|
||||
u64 midr;
|
||||
u32 running_state; /* Bit 0 set - Processor running. PSCI = 0 */
|
||||
u32 psci_state;
|
||||
};
|
||||
|
||||
/* ARM Processor Error Information Structure */
|
||||
/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */
|
||||
struct cper_arm_err_info {
|
||||
__u8 version;
|
||||
__u8 length;
|
||||
__u16 validation_bits;
|
||||
__u8 type;
|
||||
__u16 multiple_error;
|
||||
__u8 flags;
|
||||
__u64 error_info;
|
||||
__u64 virt_fault_addr;
|
||||
__u64 physical_fault_addr;
|
||||
u8 version;
|
||||
u8 length;
|
||||
u16 validation_bits;
|
||||
u8 type;
|
||||
u16 multiple_error;
|
||||
u8 flags;
|
||||
u64 error_info;
|
||||
u64 virt_fault_addr;
|
||||
u64 physical_fault_addr;
|
||||
};
|
||||
|
||||
/* ARM Processor Context Information Structure */
|
||||
/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */
|
||||
struct cper_arm_ctx_info {
|
||||
__u16 version;
|
||||
__u16 type;
|
||||
__u32 size;
|
||||
u16 version;
|
||||
u16 type;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
/* Old Memory Error Section UEFI 2.1, 2.2 */
|
||||
/* Old Memory Error Section, UEFI v2.1, v2.2 */
|
||||
struct cper_sec_mem_err_old {
|
||||
__u64 validation_bits;
|
||||
__u64 error_status;
|
||||
__u64 physical_addr;
|
||||
__u64 physical_addr_mask;
|
||||
__u16 node;
|
||||
__u16 card;
|
||||
__u16 module;
|
||||
__u16 bank;
|
||||
__u16 device;
|
||||
__u16 row;
|
||||
__u16 column;
|
||||
__u16 bit_pos;
|
||||
__u64 requestor_id;
|
||||
__u64 responder_id;
|
||||
__u64 target_id;
|
||||
__u8 error_type;
|
||||
u64 validation_bits;
|
||||
u64 error_status;
|
||||
u64 physical_addr;
|
||||
u64 physical_addr_mask;
|
||||
u16 node;
|
||||
u16 card;
|
||||
u16 module;
|
||||
u16 bank;
|
||||
u16 device;
|
||||
u16 row;
|
||||
u16 column;
|
||||
u16 bit_pos;
|
||||
u64 requestor_id;
|
||||
u64 responder_id;
|
||||
u64 target_id;
|
||||
u8 error_type;
|
||||
};
|
||||
|
||||
/* Memory Error Section UEFI >= 2.3 */
|
||||
/* Memory Error Section (UEFI >= v2.3), UEFI v2.7 sec N.2.5 */
|
||||
struct cper_sec_mem_err {
|
||||
__u64 validation_bits;
|
||||
__u64 error_status;
|
||||
__u64 physical_addr;
|
||||
__u64 physical_addr_mask;
|
||||
__u16 node;
|
||||
__u16 card;
|
||||
__u16 module;
|
||||
__u16 bank;
|
||||
__u16 device;
|
||||
__u16 row;
|
||||
__u16 column;
|
||||
__u16 bit_pos;
|
||||
__u64 requestor_id;
|
||||
__u64 responder_id;
|
||||
__u64 target_id;
|
||||
__u8 error_type;
|
||||
__u8 reserved;
|
||||
__u16 rank;
|
||||
__u16 mem_array_handle; /* card handle in UEFI 2.4 */
|
||||
__u16 mem_dev_handle; /* module handle in UEFI 2.4 */
|
||||
u64 validation_bits;
|
||||
u64 error_status;
|
||||
u64 physical_addr;
|
||||
u64 physical_addr_mask;
|
||||
u16 node;
|
||||
u16 card;
|
||||
u16 module;
|
||||
u16 bank;
|
||||
u16 device;
|
||||
u16 row;
|
||||
u16 column;
|
||||
u16 bit_pos;
|
||||
u64 requestor_id;
|
||||
u64 responder_id;
|
||||
u64 target_id;
|
||||
u8 error_type;
|
||||
u8 reserved;
|
||||
u16 rank;
|
||||
u16 mem_array_handle; /* "card handle" in UEFI 2.4 */
|
||||
u16 mem_dev_handle; /* "module handle" in UEFI 2.4 */
|
||||
};
|
||||
|
||||
struct cper_mem_err_compact {
|
||||
__u64 validation_bits;
|
||||
__u16 node;
|
||||
__u16 card;
|
||||
__u16 module;
|
||||
__u16 bank;
|
||||
__u16 device;
|
||||
__u16 row;
|
||||
__u16 column;
|
||||
__u16 bit_pos;
|
||||
__u64 requestor_id;
|
||||
__u64 responder_id;
|
||||
__u64 target_id;
|
||||
__u16 rank;
|
||||
__u16 mem_array_handle;
|
||||
__u16 mem_dev_handle;
|
||||
u64 validation_bits;
|
||||
u16 node;
|
||||
u16 card;
|
||||
u16 module;
|
||||
u16 bank;
|
||||
u16 device;
|
||||
u16 row;
|
||||
u16 column;
|
||||
u16 bit_pos;
|
||||
u64 requestor_id;
|
||||
u64 responder_id;
|
||||
u64 target_id;
|
||||
u16 rank;
|
||||
u16 mem_array_handle;
|
||||
u16 mem_dev_handle;
|
||||
};
|
||||
|
||||
/* PCI Express Error Section, UEFI v2.7 sec N.2.7 */
|
||||
struct cper_sec_pcie {
|
||||
__u64 validation_bits;
|
||||
__u32 port_type;
|
||||
u64 validation_bits;
|
||||
u32 port_type;
|
||||
struct {
|
||||
__u8 minor;
|
||||
__u8 major;
|
||||
__u8 reserved[2];
|
||||
u8 minor;
|
||||
u8 major;
|
||||
u8 reserved[2];
|
||||
} version;
|
||||
__u16 command;
|
||||
__u16 status;
|
||||
__u32 reserved;
|
||||
u16 command;
|
||||
u16 status;
|
||||
u32 reserved;
|
||||
struct {
|
||||
__u16 vendor_id;
|
||||
__u16 device_id;
|
||||
__u8 class_code[3];
|
||||
__u8 function;
|
||||
__u8 device;
|
||||
__u16 segment;
|
||||
__u8 bus;
|
||||
__u8 secondary_bus;
|
||||
__u16 slot;
|
||||
__u8 reserved;
|
||||
u16 vendor_id;
|
||||
u16 device_id;
|
||||
u8 class_code[3];
|
||||
u8 function;
|
||||
u8 device;
|
||||
u16 segment;
|
||||
u8 bus;
|
||||
u8 secondary_bus;
|
||||
u16 slot;
|
||||
u8 reserved;
|
||||
} device_id;
|
||||
struct {
|
||||
__u32 lower;
|
||||
__u32 upper;
|
||||
u32 lower;
|
||||
u32 upper;
|
||||
} serial_number;
|
||||
struct {
|
||||
__u16 secondary_status;
|
||||
__u16 control;
|
||||
u16 secondary_status;
|
||||
u16 control;
|
||||
} bridge;
|
||||
__u8 capability[60];
|
||||
__u8 aer_info[96];
|
||||
u8 capability[60];
|
||||
u8 aer_info[96];
|
||||
};
|
||||
|
||||
/* Reset to default packing */
|
||||
#pragma pack()
|
||||
|
||||
extern const char * const cper_proc_error_type_strs[4];
|
||||
extern const char *const cper_proc_error_type_strs[4];
|
||||
|
||||
u64 cper_next_record_id(void);
|
||||
const char *cper_severity_str(unsigned int);
|
||||
|
||||
@ -1,7 +1,5 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
/*
|
||||
* pci_regs.h
|
||||
*
|
||||
* PCI standard defines
|
||||
* Copyright 1994, Drew Eckhardt
|
||||
* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
|
||||
@ -15,7 +13,7 @@
|
||||
* PCI System Design Guide
|
||||
*
|
||||
* For HyperTransport information, please consult the following manuals
|
||||
* from http://www.hypertransport.org
|
||||
* from http://www.hypertransport.org :
|
||||
*
|
||||
* The HyperTransport I/O Link Specification
|
||||
*/
|
||||
@ -301,7 +299,7 @@
|
||||
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
|
||||
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
|
||||
|
||||
/* Message Signalled Interrupts registers */
|
||||
/* Message Signalled Interrupt registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Message Control */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
|
||||
@ -319,7 +317,7 @@
|
||||
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
|
||||
#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
|
||||
|
||||
/* MSI-X registers */
|
||||
/* MSI-X registers (in MSI-X capability) */
|
||||
#define PCI_MSIX_FLAGS 2 /* Message Control */
|
||||
#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
|
||||
#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
|
||||
@ -333,13 +331,13 @@
|
||||
#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
|
||||
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
|
||||
|
||||
/* MSI-X Table entry format */
|
||||
/* MSI-X Table entry format (in memory mapped by a BAR) */
|
||||
#define PCI_MSIX_ENTRY_SIZE 16
|
||||
#define PCI_MSIX_ENTRY_LOWER_ADDR 0
|
||||
#define PCI_MSIX_ENTRY_UPPER_ADDR 4
|
||||
#define PCI_MSIX_ENTRY_DATA 8
|
||||
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
|
||||
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
|
||||
#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
|
||||
#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
|
||||
#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
|
||||
#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
|
||||
#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
|
||||
|
||||
/* CompactPCI Hotswap Register */
|
||||
|
||||
@ -881,12 +879,12 @@
|
||||
|
||||
/* Page Request Interface */
|
||||
#define PCI_PRI_CTRL 0x04 /* PRI control register */
|
||||
#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
|
||||
#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
|
||||
#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
|
||||
#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
|
||||
#define PCI_PRI_STATUS 0x06 /* PRI status register */
|
||||
#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
|
||||
#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
|
||||
#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
|
||||
#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
|
||||
#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
|
||||
#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
|
||||
#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
|
||||
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
|
||||
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
|
||||
@ -904,16 +902,16 @@
|
||||
|
||||
/* Single Root I/O Virtualization */
|
||||
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
|
||||
#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
|
||||
#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
|
||||
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
|
||||
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
|
||||
#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
|
||||
#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
|
||||
#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
|
||||
#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
|
||||
#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
|
||||
#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
|
||||
#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
|
||||
#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
|
||||
#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
|
||||
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
|
||||
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
|
||||
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
|
||||
@ -943,13 +941,13 @@
|
||||
|
||||
/* Access Control Service */
|
||||
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
|
||||
#define PCI_ACS_SV 0x01 /* Source Validation */
|
||||
#define PCI_ACS_TB 0x02 /* Translation Blocking */
|
||||
#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
|
||||
#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
|
||||
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
|
||||
#define PCI_ACS_EC 0x20 /* P2P Egress Control */
|
||||
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
|
||||
#define PCI_ACS_SV 0x0001 /* Source Validation */
|
||||
#define PCI_ACS_TB 0x0002 /* Translation Blocking */
|
||||
#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
|
||||
#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
|
||||
#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
|
||||
#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
|
||||
#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
|
||||
#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
|
||||
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
|
||||
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user