mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 04:06:53 +07:00
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net
This commit is contained in:
commit
c70a3a9203
@ -838,6 +838,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
ew32(IMC, 0xFFFFFFFF);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(10);
|
||||
|
||||
/* Test each interrupt */
|
||||
@ -856,6 +857,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMC, mask);
|
||||
ew32(ICS, mask);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(10);
|
||||
|
||||
if (adapter->test_icr & mask) {
|
||||
@ -873,6 +875,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMS, mask);
|
||||
ew32(ICS, mask);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(10);
|
||||
|
||||
if (!(adapter->test_icr & mask)) {
|
||||
@ -890,6 +893,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMC, ~mask & 0x00007FFF);
|
||||
ew32(ICS, ~mask & 0x00007FFF);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(10);
|
||||
|
||||
if (adapter->test_icr) {
|
||||
@ -901,6 +905,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
ew32(IMC, 0xFFFFFFFF);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(10);
|
||||
|
||||
/* Unhook test interrupt handler */
|
||||
@ -1394,6 +1399,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
|
||||
if (unlikely(++k == txdr->count)) k = 0;
|
||||
}
|
||||
ew32(TDT, k);
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(200);
|
||||
time = jiffies; /* set the start time for the receive */
|
||||
good_cnt = 0;
|
||||
|
@ -446,6 +446,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
|
||||
/* Must reset the PHY before resetting the MAC */
|
||||
if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
|
||||
ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
|
||||
E1000_WRITE_FLUSH();
|
||||
msleep(5);
|
||||
}
|
||||
|
||||
@ -3752,6 +3753,7 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
|
||||
/* Clear SK and CS */
|
||||
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
|
||||
ew32(EECD, eecd);
|
||||
E1000_WRITE_FLUSH();
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
@ -3824,6 +3826,7 @@ static void e1000_release_eeprom(struct e1000_hw *hw)
|
||||
eecd &= ~E1000_EECD_SK; /* Lower SCK */
|
||||
|
||||
ew32(EECD, eecd);
|
||||
E1000_WRITE_FLUSH();
|
||||
|
||||
udelay(hw->eeprom.delay_usec);
|
||||
} else if (hw->eeprom.type == e1000_eeprom_microwire) {
|
||||
|
@ -1313,6 +1313,7 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
|
||||
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
|
||||
E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
|
||||
ew32(KMRNCTRLSTA, kmrnctrlsta);
|
||||
e1e_flush();
|
||||
|
||||
udelay(2);
|
||||
|
||||
@ -1347,6 +1348,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
|
||||
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
|
||||
E1000_KMRNCTRLSTA_OFFSET) | data;
|
||||
ew32(KMRNCTRLSTA, kmrnctrlsta);
|
||||
e1e_flush();
|
||||
|
||||
udelay(2);
|
||||
|
||||
|
@ -28,8 +28,8 @@
|
||||
|
||||
/* ethtool support for e1000 */
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
@ -964,6 +964,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
ew32(IMC, 0xFFFFFFFF);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
/* Test each interrupt */
|
||||
@ -996,6 +997,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMC, mask);
|
||||
ew32(ICS, mask);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (adapter->test_icr & mask) {
|
||||
@ -1014,6 +1016,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMS, mask);
|
||||
ew32(ICS, mask);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (!(adapter->test_icr & mask)) {
|
||||
@ -1032,6 +1035,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
ew32(IMC, ~mask & 0x00007FFF);
|
||||
ew32(ICS, ~mask & 0x00007FFF);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (adapter->test_icr) {
|
||||
@ -1043,6 +1047,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
ew32(IMC, 0xFFFFFFFF);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
/* Unhook test interrupt handler */
|
||||
@ -1276,6 +1281,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
|
||||
E1000_CTRL_FD); /* Force Duplex to FULL */
|
||||
|
||||
ew32(CTRL, ctrl_reg);
|
||||
e1e_flush();
|
||||
udelay(500);
|
||||
|
||||
return 0;
|
||||
@ -1418,6 +1424,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
|
||||
*/
|
||||
#define E1000_SERDES_LB_ON 0x410
|
||||
ew32(SCTL, E1000_SERDES_LB_ON);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
return 0;
|
||||
@ -1513,6 +1520,7 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter)
|
||||
hw->phy.media_type == e1000_media_type_internal_serdes) {
|
||||
#define E1000_SERDES_LB_OFF 0x400
|
||||
ew32(SCTL, E1000_SERDES_LB_OFF);
|
||||
e1e_flush();
|
||||
usleep_range(10000, 20000);
|
||||
break;
|
||||
}
|
||||
@ -1592,6 +1600,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
|
||||
k = 0;
|
||||
}
|
||||
ew32(TDT, k);
|
||||
e1e_flush();
|
||||
msleep(200);
|
||||
time = jiffies; /* set the start time for the receive */
|
||||
good_cnt = 0;
|
||||
|
@ -283,6 +283,7 @@ static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
|
||||
ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
|
||||
ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
|
||||
ew32(CTRL, ctrl);
|
||||
e1e_flush();
|
||||
udelay(10);
|
||||
ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
|
||||
ew32(CTRL, ctrl);
|
||||
@ -1230,9 +1231,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
|
||||
ew32(CTRL, reg);
|
||||
|
||||
ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
|
||||
e1e_flush();
|
||||
udelay(20);
|
||||
ew32(CTRL, ctrl_reg);
|
||||
ew32(CTRL_EXT, ctrl_ext);
|
||||
e1e_flush();
|
||||
udelay(20);
|
||||
|
||||
out:
|
||||
@ -2134,8 +2137,7 @@ static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
|
||||
|
||||
ret_val = 0;
|
||||
for (i = 0; i < words; i++) {
|
||||
if ((dev_spec->shadow_ram) &&
|
||||
(dev_spec->shadow_ram[offset+i].modified)) {
|
||||
if (dev_spec->shadow_ram[offset+i].modified) {
|
||||
data[i] = dev_spec->shadow_ram[offset+i].value;
|
||||
} else {
|
||||
ret_val = e1000_read_flash_word_ich8lan(hw,
|
||||
@ -3090,6 +3092,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
|
||||
ret_val = e1000_acquire_swflag_ich8lan(hw);
|
||||
e_dbg("Issuing a global reset to ich8lan\n");
|
||||
ew32(CTRL, (ctrl | E1000_CTRL_RST));
|
||||
/* cannot issue a flush here because it hangs the hardware */
|
||||
msleep(20);
|
||||
|
||||
if (!ret_val)
|
||||
|
@ -1986,6 +1986,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
|
||||
/* Clear SK and CS */
|
||||
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
|
||||
ew32(EECD, eecd);
|
||||
e1e_flush();
|
||||
udelay(1);
|
||||
|
||||
/*
|
||||
|
@ -31,12 +31,12 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/ipv6.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -537,6 +537,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
|
||||
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
|
||||
E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
|
||||
ew32(KMRNCTRLSTA, kmrnctrlsta);
|
||||
e1e_flush();
|
||||
|
||||
udelay(2);
|
||||
|
||||
@ -609,6 +610,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
|
||||
kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
|
||||
E1000_KMRNCTRLSTA_OFFSET) | data;
|
||||
ew32(KMRNCTRLSTA, kmrnctrlsta);
|
||||
e1e_flush();
|
||||
|
||||
udelay(2);
|
||||
|
||||
|
@ -285,6 +285,7 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
|
||||
/* Clear SK and CS */
|
||||
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
|
||||
wr32(E1000_EECD, eecd);
|
||||
wrfl();
|
||||
udelay(1);
|
||||
timeout = NVM_MAX_RETRY_SPI;
|
||||
|
||||
|
@ -1225,6 +1225,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
wr32(E1000_IMC, ~0);
|
||||
wrfl();
|
||||
msleep(10);
|
||||
|
||||
/* Define all writable bits for ICS */
|
||||
@ -1268,6 +1269,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
|
||||
|
||||
wr32(E1000_IMC, mask);
|
||||
wr32(E1000_ICS, mask);
|
||||
wrfl();
|
||||
msleep(10);
|
||||
|
||||
if (adapter->test_icr & mask) {
|
||||
@ -1289,6 +1291,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
|
||||
|
||||
wr32(E1000_IMS, mask);
|
||||
wr32(E1000_ICS, mask);
|
||||
wrfl();
|
||||
msleep(10);
|
||||
|
||||
if (!(adapter->test_icr & mask)) {
|
||||
@ -1310,6 +1313,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
|
||||
|
||||
wr32(E1000_IMC, ~mask);
|
||||
wr32(E1000_ICS, ~mask);
|
||||
wrfl();
|
||||
msleep(10);
|
||||
|
||||
if (adapter->test_icr & mask) {
|
||||
@ -1321,6 +1325,7 @@ static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
wr32(E1000_IMC, ~0);
|
||||
wrfl();
|
||||
msleep(10);
|
||||
|
||||
/* Unhook test interrupt handler */
|
||||
|
@ -1052,6 +1052,7 @@ static int igb_set_interrupt_capability(struct igb_adapter *adapter)
|
||||
kfree(adapter->vf_data);
|
||||
adapter->vf_data = NULL;
|
||||
wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
|
||||
wrfl();
|
||||
msleep(100);
|
||||
dev_info(&adapter->pdev->dev, "IOV Disabled\n");
|
||||
}
|
||||
@ -2022,7 +2023,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
|
||||
|
||||
if (hw->bus.func == 0)
|
||||
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
|
||||
else if (hw->mac.type == e1000_82580)
|
||||
else if (hw->mac.type >= e1000_82580)
|
||||
hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
|
||||
NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
|
||||
&eeprom_data);
|
||||
@ -2198,6 +2199,7 @@ static void __devexit igb_remove(struct pci_dev *pdev)
|
||||
kfree(adapter->vf_data);
|
||||
adapter->vf_data = NULL;
|
||||
wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
|
||||
wrfl();
|
||||
msleep(100);
|
||||
dev_info(&pdev->dev, "IOV Disabled\n");
|
||||
}
|
||||
|
@ -1226,6 +1226,7 @@ static void igbvf_configure_tx(struct igbvf_adapter *adapter)
|
||||
/* disable transmits */
|
||||
txdctl = er32(TXDCTL(0));
|
||||
ew32(TXDCTL(0), txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
|
||||
e1e_flush();
|
||||
msleep(10);
|
||||
|
||||
/* Setup the HW Tx Head and Tail descriptor pointers */
|
||||
@ -1306,6 +1307,7 @@ static void igbvf_configure_rx(struct igbvf_adapter *adapter)
|
||||
/* disable receives */
|
||||
rxdctl = er32(RXDCTL(0));
|
||||
ew32(RXDCTL(0), rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
|
||||
e1e_flush();
|
||||
msleep(10);
|
||||
|
||||
rdlen = rx_ring->count * sizeof(union e1000_adv_rx_desc);
|
||||
|
@ -57,6 +57,7 @@ ixgb_raise_clock(struct ixgb_hw *hw,
|
||||
*/
|
||||
*eecd_reg = *eecd_reg | IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
@ -75,6 +76,7 @@ ixgb_lower_clock(struct ixgb_hw *hw,
|
||||
*/
|
||||
*eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, *eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
@ -112,6 +114,7 @@ ixgb_shift_out_bits(struct ixgb_hw *hw,
|
||||
eecd_reg |= IXGB_EECD_DI;
|
||||
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
|
||||
udelay(50);
|
||||
|
||||
@ -206,21 +209,25 @@ ixgb_standby_eeprom(struct ixgb_hw *hw)
|
||||
/* Deselect EEPROM */
|
||||
eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
|
||||
/* Clock high */
|
||||
eecd_reg |= IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
|
||||
/* Select EEPROM */
|
||||
eecd_reg |= IXGB_EECD_CS;
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
|
||||
/* Clock low */
|
||||
eecd_reg &= ~IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
@ -239,11 +246,13 @@ ixgb_clock_eeprom(struct ixgb_hw *hw)
|
||||
/* Rising edge of clock */
|
||||
eecd_reg |= IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
|
||||
/* Falling edge of clock */
|
||||
eecd_reg &= ~IXGB_EECD_SK;
|
||||
IXGB_WRITE_REG(hw, EECD, eecd_reg);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
|
@ -149,6 +149,7 @@ ixgb_adapter_stop(struct ixgb_hw *hw)
|
||||
*/
|
||||
IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
|
||||
IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
msleep(IXGB_DELAY_BEFORE_RESET);
|
||||
|
||||
/* Issue a global reset to the MAC. This will reset the chip's
|
||||
@ -1220,6 +1221,7 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw)
|
||||
ctrl &= ~IXGB_CTRL0_SDP2;
|
||||
ctrl |= IXGB_CTRL0_SDP3;
|
||||
IXGB_WRITE_REG(hw, CTRL0, ctrl);
|
||||
IXGB_WRITE_FLUSH(hw);
|
||||
|
||||
/* SerDes needs extra delay */
|
||||
msleep(IXGB_SUN_PHY_RESET_DELAY);
|
||||
|
@ -213,6 +213,7 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
|
||||
switch (hw->phy.type) {
|
||||
case ixgbe_phy_tn:
|
||||
phy->ops.check_link = &ixgbe_check_phy_link_tnx;
|
||||
phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
|
||||
phy->ops.get_firmware_version =
|
||||
&ixgbe_get_phy_firmware_version_tnx;
|
||||
break;
|
||||
|
@ -2632,6 +2632,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
|
||||
autoc_reg |= IXGBE_AUTOC_AN_RESTART;
|
||||
autoc_reg |= IXGBE_AUTOC_FLU;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
usleep_range(10000, 20000);
|
||||
}
|
||||
|
||||
|
@ -1378,6 +1378,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
|
||||
IXGBE_WRITE_FLUSH(&adapter->hw);
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
/* Test each interrupt */
|
||||
@ -1398,6 +1399,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
|
||||
~mask & 0x00007FFF);
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
|
||||
~mask & 0x00007FFF);
|
||||
IXGBE_WRITE_FLUSH(&adapter->hw);
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (adapter->test_icr & mask) {
|
||||
@ -1415,6 +1417,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
|
||||
adapter->test_icr = 0;
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
|
||||
IXGBE_WRITE_FLUSH(&adapter->hw);
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (!(adapter->test_icr &mask)) {
|
||||
@ -1435,6 +1438,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
|
||||
~mask & 0x00007FFF);
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
|
||||
~mask & 0x00007FFF);
|
||||
IXGBE_WRITE_FLUSH(&adapter->hw);
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
if (adapter->test_icr) {
|
||||
@ -1446,6 +1450,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
|
||||
|
||||
/* Disable all the interrupts */
|
||||
IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
|
||||
IXGBE_WRITE_FLUSH(&adapter->hw);
|
||||
usleep_range(10000, 20000);
|
||||
|
||||
/* Unhook test interrupt handler */
|
||||
|
@ -184,6 +184,7 @@ static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
|
||||
vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
|
||||
vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* take a breather then clean up driver data */
|
||||
msleep(100);
|
||||
@ -1005,7 +1006,7 @@ static int __ixgbe_notify_dca(struct device *dev, void *data)
|
||||
struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
|
||||
unsigned long event = *(unsigned long *)data;
|
||||
|
||||
if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
|
||||
if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
|
||||
return 0;
|
||||
|
||||
switch (event) {
|
||||
|
@ -1585,6 +1585,7 @@ static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* SCL rise time (1000ns) */
|
||||
udelay(IXGBE_I2C_T_RISE);
|
||||
@ -1605,6 +1606,7 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* SCL fall time (300ns) */
|
||||
udelay(IXGBE_I2C_T_FALL);
|
||||
@ -1628,6 +1630,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
|
||||
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
|
||||
udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
|
||||
|
@ -162,6 +162,7 @@ static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
|
||||
ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
|
||||
ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
|
||||
msleep(50);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user