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bpf, arm: Optimize ALU ARSH K using asr immediate instruction
This patch adds an optimization that uses the asr immediate instruction for BPF_ALU BPF_ARSH BPF_K, rather than loading the immediate to a temporary register. This is similar to existing code for handling BPF_ALU BPF_{LSH,RSH} BPF_K. This optimization saves two instructions and is more consistent with LSH and RSH. Example of the code generated for BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5) before the optimization: 2c: mov r8, #5 30: mov r9, #0 34: asr r0, r0, r8 and after optimization: 2c: asr r0, r0, #5 Tested on QEMU using lib/test_bpf and test_verifier. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/20200501020210.32294-3-luke.r.nels@gmail.com
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@ -795,6 +795,9 @@ static inline void emit_a32_alu_i(const s8 dst, const u32 val,
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case BPF_RSH:
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emit(ARM_LSR_I(rd, rd, val), ctx);
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break;
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case BPF_ARSH:
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emit(ARM_ASR_I(rd, rd, val), ctx);
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break;
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case BPF_NEG:
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emit(ARM_RSB_I(rd, rd, val), ctx);
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break;
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@ -1408,7 +1411,6 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
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case BPF_ALU | BPF_MUL | BPF_X:
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case BPF_ALU | BPF_LSH | BPF_X:
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case BPF_ALU | BPF_RSH | BPF_X:
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case BPF_ALU | BPF_ARSH | BPF_K:
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case BPF_ALU | BPF_ARSH | BPF_X:
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case BPF_ALU64 | BPF_ADD | BPF_K:
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case BPF_ALU64 | BPF_ADD | BPF_X:
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@ -1465,10 +1467,12 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
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case BPF_ALU64 | BPF_MOD | BPF_K:
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case BPF_ALU64 | BPF_MOD | BPF_X:
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goto notyet;
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/* dst = dst >> imm */
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/* dst = dst << imm */
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case BPF_ALU | BPF_RSH | BPF_K:
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/* dst = dst >> imm */
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/* dst = dst >> imm (signed) */
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case BPF_ALU | BPF_LSH | BPF_K:
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case BPF_ALU | BPF_RSH | BPF_K:
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case BPF_ALU | BPF_ARSH | BPF_K:
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if (unlikely(imm > 31))
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return -EINVAL;
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if (imm)
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@ -94,6 +94,9 @@
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#define ARM_INST_LSR_I 0x01a00020
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#define ARM_INST_LSR_R 0x01a00030
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#define ARM_INST_ASR_I 0x01a00040
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#define ARM_INST_ASR_R 0x01a00050
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#define ARM_INST_MOV_R 0x01a00000
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#define ARM_INST_MOVS_R 0x01b00000
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#define ARM_INST_MOV_I 0x03a00000
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