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drm/i915/skl: Retrieve the Rpe value from Pcode
Read the efficient frequency (aka RPe) value through the the mailbox command (0x1A) from the pcode, as done on Haswell and Broadwell. The turbo minimum frequency softlimit is not revised as per the efficient frequency value. v2: Replaced the conditional expression operator with 'if' statement (Tom) v3: Corrected the derivation of efficient frequency & shifted the GEN9_FREQ_SCALER multiplications downwards (Ville) Issue: VIZ-5143 Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -4703,18 +4703,11 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
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dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
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}
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if (IS_SKYLAKE(dev)) {
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/* Store the frequency values in 16.66 MHZ units, which is
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the natural hardware unit for SKL */
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dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
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}
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/* hw_max = RP0 until we check for overclocking */
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dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
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dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
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if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
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ret = sandybridge_pcode_read(dev_priv,
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HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
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&ddcc_status);
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@ -4726,6 +4719,16 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
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dev_priv->rps.max_freq);
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}
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if (IS_SKYLAKE(dev)) {
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/* Store the frequency values in 16.66 MHZ units, which is
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the natural hardware unit for SKL */
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dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
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dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
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}
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dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
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/* Preserve min/max settings in case of re-init */
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