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drm/i915/chv: Update csc coefficient matrix during modeset

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During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.

Changes since V1:
- Removed platform check

Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1536589634-29680-1-git-send-email-raviraj.p.sitaram@intel.com
This commit is contained in:
P Raviraj Sitaram 2018-09-10 19:57:14 +05:30 committed by Ville Syrjälä
parent b84d9ab0b7
commit c59d2da8ec
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/drm/i915/intel_display.c
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@ -6013,6 +6013,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(intel_crtc);
intel_color_set_csc(&pipe_config->base);
intel_crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);