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s390/kernel: use expoline for indirect branches
The assember code in arch/s390/kernel uses a few more indirect branches
which need to be done with execute trampolines for CONFIG_EXPOLINE=y.
Cc: stable@vger.kernel.org # 4.16
Fixes: f19fbd5ed6
("s390: introduce execute-trampolines for branches")
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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@ -9,18 +9,22 @@
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/nospec-insn.h>
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#include <asm/ptrace.h>
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#include <asm/sigp.h>
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GEN_BR_THUNK %r9
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GEN_BR_THUNK %r14
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ENTRY(s390_base_mcck_handler)
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basr %r13,0
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0: lg %r15,__LC_PANIC_STACK # load panic stack
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aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_mcck_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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basr %r14,%r1
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BASR_EX %r14,%r9
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1: la %r1,4095
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lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)
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lpswe __LC_MCK_OLD_PSW
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@ -37,10 +41,10 @@ ENTRY(s390_base_ext_handler)
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_ext_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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basr %r14,%r1
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BASR_EX %r14,%r9
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1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC
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ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit
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lpswe __LC_EXT_OLD_PSW
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@ -57,10 +61,10 @@ ENTRY(s390_base_pgm_handler)
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basr %r13,0
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0: aghi %r15,-STACK_FRAME_OVERHEAD
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larl %r1,s390_base_pgm_handler_fn
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lg %r1,0(%r1)
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ltgr %r1,%r1
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lg %r9,0(%r1)
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ltgr %r9,%r9
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jz 1f
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basr %r14,%r1
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BASR_EX %r14,%r9
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lmg %r0,%r15,__LC_SAVE_AREA_SYNC
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lpswe __LC_PGM_OLD_PSW
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1: lpswe disabled_wait_psw-0b(%r13)
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@ -117,7 +121,7 @@ ENTRY(diag308_reset)
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larl %r4,.Lcontinue_psw # Restore PSW flags
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lpswe 0(%r4)
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.Lcontinue:
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br %r14
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BR_EX %r14
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.align 16
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.Lrestart_psw:
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.long 0x00080000,0x80000000 + .Lrestart_part2
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@ -7,8 +7,11 @@
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/nospec-insn.h>
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#include <asm/sigp.h>
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GEN_BR_THUNK %r9
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#
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# Issue "store status" for the current CPU to its prefix page
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# and call passed function afterwards
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@ -67,9 +70,9 @@ ENTRY(store_status)
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st %r4,0(%r1)
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st %r5,4(%r1)
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stg %r2,8(%r1)
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lgr %r1,%r2
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lgr %r9,%r2
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lgr %r2,%r3
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br %r1
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BR_EX %r9
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.section .bss
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.align 8
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@ -13,6 +13,7 @@
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/nospec-insn.h>
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#include <asm/sigp.h>
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/*
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@ -24,6 +25,8 @@
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* (see below) in the resume process.
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* This function runs with disabled interrupts.
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*/
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GEN_BR_THUNK %r14
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.section .text
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ENTRY(swsusp_arch_suspend)
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stmg %r6,%r15,__SF_GPRS(%r15)
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@ -103,7 +106,7 @@ ENTRY(swsusp_arch_suspend)
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spx 0x318(%r1)
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lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
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lghi %r2,0
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br %r14
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BR_EX %r14
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/*
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* Restore saved memory image to correct place and restore register context.
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@ -197,11 +200,10 @@ pgm_check_entry:
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larl %r15,init_thread_union
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ahi %r15,1<<(PAGE_SHIFT+THREAD_SIZE_ORDER)
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larl %r2,.Lpanic_string
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larl %r3,sclp_early_printk
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lghi %r1,0
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sam31
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE
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basr %r14,%r3
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brasl %r14,sclp_early_printk
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larl %r3,.Ldisabled_wait_31
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lpsw 0(%r3)
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4:
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@ -267,7 +269,7 @@ restore_registers:
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/* Return 0 */
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lmg %r6,%r15,STACK_FRAME_OVERHEAD + __SF_GPRS(%r15)
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lghi %r2,0
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br %r14
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BR_EX %r14
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.section .data..nosave,"aw",@progbits
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.align 8
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