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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: qcom/emac: add ethtool support for reading hardware registers
Implement the get_regs_len and get_regs ethtool methods. The driver returns the values of selected hardware registers. The make the register offsets known to emac_ethtool, the the register offset macros are all combined into one header file. They were inexplicably and arbitrarily split between two files. Signed-off-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Timur Tabi
David S. Miller
parent
15c2e10241
commit
c4e7beea21
@ -170,6 +170,43 @@ static int emac_set_pauseparam(struct net_device *netdev,
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return 0;
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}
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/* Selected registers that might want to track during runtime. */
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static const u16 emac_regs[] = {
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EMAC_DMA_MAS_CTRL,
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EMAC_MAC_CTRL,
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EMAC_TXQ_CTRL_0,
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EMAC_RXQ_CTRL_0,
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EMAC_DMA_CTRL,
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EMAC_INT_MASK,
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EMAC_AXI_MAST_CTRL,
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EMAC_CORE_HW_VERSION,
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EMAC_MISC_CTRL,
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};
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/* Every time emac_regs[] above is changed, increase this version number. */
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#define EMAC_REGS_VERSION 0
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#define EMAC_MAX_REG_SIZE ARRAY_SIZE(emac_regs)
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static void emac_get_regs(struct net_device *netdev,
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struct ethtool_regs *regs, void *buff)
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{
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struct emac_adapter *adpt = netdev_priv(netdev);
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u32 *val = buff;
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unsigned int i;
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regs->version = EMAC_REGS_VERSION;
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regs->len = EMAC_MAX_REG_SIZE * sizeof(u32);
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for (i = 0; i < EMAC_MAX_REG_SIZE; i++)
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val[i] = readl(adpt->base + emac_regs[i]);
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}
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static int emac_get_regs_len(struct net_device *netdev)
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{
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return EMAC_MAX_REG_SIZE * sizeof(32);
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}
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static const struct ethtool_ops emac_ethtool_ops = {
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.get_link_ksettings = phy_ethtool_get_link_ksettings,
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.set_link_ksettings = phy_ethtool_set_link_ksettings,
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@ -189,6 +226,9 @@ static const struct ethtool_ops emac_ethtool_ops = {
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.nway_reset = emac_nway_reset,
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.get_link = ethtool_op_get_link,
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.get_regs_len = emac_get_regs_len,
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.get_regs = emac_get_regs,
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};
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void emac_set_ethtool_ops(struct net_device *netdev)
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@ -25,58 +25,6 @@
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#include "emac.h"
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#include "emac-sgmii.h"
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/* EMAC base register offsets */
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#define EMAC_MAC_CTRL 0x001480
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#define EMAC_WOL_CTRL0 0x0014a0
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#define EMAC_RSS_KEY0 0x0014b0
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#define EMAC_H1TPD_BASE_ADDR_LO 0x0014e0
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#define EMAC_H2TPD_BASE_ADDR_LO 0x0014e4
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#define EMAC_H3TPD_BASE_ADDR_LO 0x0014e8
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#define EMAC_INTER_SRAM_PART9 0x001534
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#define EMAC_DESC_CTRL_0 0x001540
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#define EMAC_DESC_CTRL_1 0x001544
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#define EMAC_DESC_CTRL_2 0x001550
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#define EMAC_DESC_CTRL_10 0x001554
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#define EMAC_DESC_CTRL_12 0x001558
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#define EMAC_DESC_CTRL_13 0x00155c
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#define EMAC_DESC_CTRL_3 0x001560
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#define EMAC_DESC_CTRL_4 0x001564
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#define EMAC_DESC_CTRL_5 0x001568
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#define EMAC_DESC_CTRL_14 0x00156c
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#define EMAC_DESC_CTRL_15 0x001570
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#define EMAC_DESC_CTRL_16 0x001574
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#define EMAC_DESC_CTRL_6 0x001578
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#define EMAC_DESC_CTRL_8 0x001580
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#define EMAC_DESC_CTRL_9 0x001584
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#define EMAC_DESC_CTRL_11 0x001588
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#define EMAC_TXQ_CTRL_0 0x001590
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#define EMAC_TXQ_CTRL_1 0x001594
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#define EMAC_TXQ_CTRL_2 0x001598
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#define EMAC_RXQ_CTRL_0 0x0015a0
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#define EMAC_RXQ_CTRL_1 0x0015a4
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#define EMAC_RXQ_CTRL_2 0x0015a8
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#define EMAC_RXQ_CTRL_3 0x0015ac
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#define EMAC_BASE_CPU_NUMBER 0x0015b8
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#define EMAC_DMA_CTRL 0x0015c0
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#define EMAC_MAILBOX_0 0x0015e0
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#define EMAC_MAILBOX_5 0x0015e4
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#define EMAC_MAILBOX_6 0x0015e8
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#define EMAC_MAILBOX_13 0x0015ec
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#define EMAC_MAILBOX_2 0x0015f4
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#define EMAC_MAILBOX_3 0x0015f8
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#define EMAC_MAILBOX_11 0x00160c
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#define EMAC_AXI_MAST_CTRL 0x001610
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#define EMAC_MAILBOX_12 0x001614
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#define EMAC_MAILBOX_9 0x001618
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#define EMAC_MAILBOX_10 0x00161c
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#define EMAC_ATHR_HEADER_CTRL 0x001620
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#define EMAC_CLK_GATE_CTRL 0x001814
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#define EMAC_MISC_CTRL 0x001990
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#define EMAC_MAILBOX_7 0x0019e0
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#define EMAC_MAILBOX_8 0x0019e4
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#define EMAC_MAILBOX_15 0x001bd4
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#define EMAC_MAILBOX_16 0x001bd8
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/* EMAC_MAC_CTRL */
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#define SINGLE_PAUSE_MODE 0x10000000
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#define DEBUG_MODE 0x08000000
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@ -22,35 +22,85 @@
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#include "emac-sgmii.h"
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/* EMAC base register offsets */
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#define EMAC_DMA_MAS_CTRL 0x001400
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#define EMAC_IRQ_MOD_TIM_INIT 0x001408
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#define EMAC_BLK_IDLE_STS 0x00140c
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#define EMAC_PHY_LINK_DELAY 0x00141c
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#define EMAC_SYS_ALIV_CTRL 0x001434
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#define EMAC_MAC_IPGIFG_CTRL 0x001484
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#define EMAC_MAC_STA_ADDR0 0x001488
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#define EMAC_MAC_STA_ADDR1 0x00148c
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#define EMAC_HASH_TAB_REG0 0x001490
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#define EMAC_HASH_TAB_REG1 0x001494
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#define EMAC_MAC_HALF_DPLX_CTRL 0x001498
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#define EMAC_MAX_FRAM_LEN_CTRL 0x00149c
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#define EMAC_INT_STATUS 0x001600
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#define EMAC_INT_MASK 0x001604
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#define EMAC_RXMAC_STATC_REG0 0x001700
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#define EMAC_RXMAC_STATC_REG22 0x001758
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#define EMAC_TXMAC_STATC_REG0 0x001760
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#define EMAC_TXMAC_STATC_REG24 0x0017c0
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#define EMAC_CORE_HW_VERSION 0x001974
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#define EMAC_IDT_TABLE0 0x001b00
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#define EMAC_RXMAC_STATC_REG23 0x001bc8
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#define EMAC_RXMAC_STATC_REG24 0x001bcc
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#define EMAC_TXMAC_STATC_REG25 0x001bd0
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#define EMAC_INT1_MASK 0x001bf0
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#define EMAC_INT1_STATUS 0x001bf4
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#define EMAC_INT2_MASK 0x001bf8
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#define EMAC_INT2_STATUS 0x001bfc
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#define EMAC_INT3_MASK 0x001c00
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#define EMAC_INT3_STATUS 0x001c04
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#define EMAC_DMA_MAS_CTRL 0x1400
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#define EMAC_IRQ_MOD_TIM_INIT 0x1408
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#define EMAC_BLK_IDLE_STS 0x140c
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#define EMAC_PHY_LINK_DELAY 0x141c
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#define EMAC_SYS_ALIV_CTRL 0x1434
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#define EMAC_MAC_CTRL 0x1480
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#define EMAC_MAC_IPGIFG_CTRL 0x1484
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#define EMAC_MAC_STA_ADDR0 0x1488
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#define EMAC_MAC_STA_ADDR1 0x148c
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#define EMAC_HASH_TAB_REG0 0x1490
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#define EMAC_HASH_TAB_REG1 0x1494
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#define EMAC_MAC_HALF_DPLX_CTRL 0x1498
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#define EMAC_MAX_FRAM_LEN_CTRL 0x149c
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#define EMAC_WOL_CTRL0 0x14a0
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#define EMAC_RSS_KEY0 0x14b0
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#define EMAC_H1TPD_BASE_ADDR_LO 0x14e0
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#define EMAC_H2TPD_BASE_ADDR_LO 0x14e4
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#define EMAC_H3TPD_BASE_ADDR_LO 0x14e8
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#define EMAC_INTER_SRAM_PART9 0x1534
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#define EMAC_DESC_CTRL_0 0x1540
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#define EMAC_DESC_CTRL_1 0x1544
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#define EMAC_DESC_CTRL_2 0x1550
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#define EMAC_DESC_CTRL_10 0x1554
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#define EMAC_DESC_CTRL_12 0x1558
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#define EMAC_DESC_CTRL_13 0x155c
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#define EMAC_DESC_CTRL_3 0x1560
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#define EMAC_DESC_CTRL_4 0x1564
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#define EMAC_DESC_CTRL_5 0x1568
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#define EMAC_DESC_CTRL_14 0x156c
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#define EMAC_DESC_CTRL_15 0x1570
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#define EMAC_DESC_CTRL_16 0x1574
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#define EMAC_DESC_CTRL_6 0x1578
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#define EMAC_DESC_CTRL_8 0x1580
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#define EMAC_DESC_CTRL_9 0x1584
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#define EMAC_DESC_CTRL_11 0x1588
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#define EMAC_TXQ_CTRL_0 0x1590
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#define EMAC_TXQ_CTRL_1 0x1594
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#define EMAC_TXQ_CTRL_2 0x1598
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#define EMAC_RXQ_CTRL_0 0x15a0
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#define EMAC_RXQ_CTRL_1 0x15a4
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#define EMAC_RXQ_CTRL_2 0x15a8
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#define EMAC_RXQ_CTRL_3 0x15ac
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#define EMAC_BASE_CPU_NUMBER 0x15b8
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#define EMAC_DMA_CTRL 0x15c0
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#define EMAC_MAILBOX_0 0x15e0
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#define EMAC_MAILBOX_5 0x15e4
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#define EMAC_MAILBOX_6 0x15e8
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#define EMAC_MAILBOX_13 0x15ec
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#define EMAC_MAILBOX_2 0x15f4
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#define EMAC_MAILBOX_3 0x15f8
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#define EMAC_INT_STATUS 0x1600
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#define EMAC_INT_MASK 0x1604
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#define EMAC_MAILBOX_11 0x160c
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#define EMAC_AXI_MAST_CTRL 0x1610
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#define EMAC_MAILBOX_12 0x1614
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#define EMAC_MAILBOX_9 0x1618
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#define EMAC_MAILBOX_10 0x161c
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#define EMAC_ATHR_HEADER_CTRL 0x1620
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#define EMAC_RXMAC_STATC_REG0 0x1700
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#define EMAC_RXMAC_STATC_REG22 0x1758
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#define EMAC_TXMAC_STATC_REG0 0x1760
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#define EMAC_TXMAC_STATC_REG24 0x17c0
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#define EMAC_CLK_GATE_CTRL 0x1814
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#define EMAC_CORE_HW_VERSION 0x1974
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#define EMAC_MISC_CTRL 0x1990
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#define EMAC_MAILBOX_7 0x19e0
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#define EMAC_MAILBOX_8 0x19e4
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#define EMAC_IDT_TABLE0 0x1b00
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#define EMAC_RXMAC_STATC_REG23 0x1bc8
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#define EMAC_RXMAC_STATC_REG24 0x1bcc
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#define EMAC_TXMAC_STATC_REG25 0x1bd0
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#define EMAC_MAILBOX_15 0x1bd4
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#define EMAC_MAILBOX_16 0x1bd8
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#define EMAC_INT1_MASK 0x1bf0
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#define EMAC_INT1_STATUS 0x1bf4
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#define EMAC_INT2_MASK 0x1bf8
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#define EMAC_INT2_STATUS 0x1bfc
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#define EMAC_INT3_MASK 0x1c00
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#define EMAC_INT3_STATUS 0x1c04
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/* EMAC_DMA_MAS_CTRL */
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#define DEV_ID_NUM_BMSK 0x7f000000
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