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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 18:47:56 +07:00
drm/msm/dsi: add implementation for helper functions
Add dsi host helper function implementation for DSI v2 DSI 6G 1.x and DSI 6G v2.0+ controllers Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Sibi Sankar
Rob Clark
parent
e18177cc57
commit
c4d8cfe516
@ -183,6 +183,21 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
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int msm_dsi_host_init(struct msm_dsi *msm_dsi);
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int msm_dsi_runtime_suspend(struct device *dev);
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int msm_dsi_runtime_resume(struct device *dev);
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int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
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int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
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void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);
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void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host);
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int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size);
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int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size);
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void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host);
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void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host);
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void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host);
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int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *iova);
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int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova);
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int dsi_clk_init_v2(struct msm_dsi_host *msm_host);
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int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host);
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int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host);
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int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host);
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/* dsi phy */
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struct msm_dsi_phy;
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@ -136,20 +136,58 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
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.num_dsi = 2,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_v2,
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.link_clk_disable = dsi_link_clk_disable_v2,
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.clk_init_ver = dsi_clk_init_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_v2,
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.tx_buf_get = dsi_tx_buf_get_v2,
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.tx_buf_put = NULL,
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.dma_base_get = dsi_dma_base_get_v2,
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.calc_clk_rate = dsi_calc_clk_rate_v2,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = NULL,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
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.link_clk_enable = dsi_link_clk_enable_6g,
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.link_clk_disable = dsi_link_clk_disable_6g,
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.clk_init_ver = dsi_clk_init_6g_v2,
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.tx_buf_alloc = dsi_tx_buf_alloc_6g,
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.tx_buf_get = dsi_tx_buf_get_6g,
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.tx_buf_put = dsi_tx_buf_put_6g,
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.dma_base_get = dsi_dma_base_get_6g,
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.calc_clk_rate = dsi_calc_clk_rate_6g,
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};
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static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
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{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg},
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{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
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&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
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&msm8974_apq8084_dsi_cfg},
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
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&msm8974_apq8084_dsi_cfg},
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
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&msm8974_apq8084_dsi_cfg},
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
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&msm8974_apq8084_dsi_cfg},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, &msm8994_dsi_cfg},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, &msm8916_dsi_cfg},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, &msm8996_dsi_cfg},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, &sdm845_dsi_cfg},
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&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
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&msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
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&msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
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&msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
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{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
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&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
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};
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const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
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@ -332,6 +332,54 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host)
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return 0;
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}
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int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
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{
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struct platform_device *pdev = msm_host->pdev;
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int ret = 0;
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msm_host->src_clk = msm_clk_get(pdev, "src");
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if (IS_ERR(msm_host->src_clk)) {
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ret = PTR_ERR(msm_host->src_clk);
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pr_err("%s: can't find src clock. ret=%d\n",
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__func__, ret);
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msm_host->src_clk = NULL;
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return ret;
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}
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msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
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if (!msm_host->esc_clk_src) {
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ret = -ENODEV;
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pr_err("%s: can't get esc clock parent. ret=%d\n",
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__func__, ret);
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return ret;
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}
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msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
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if (!msm_host->dsi_clk_src) {
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ret = -ENODEV;
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pr_err("%s: can't get src clock parent. ret=%d\n",
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__func__, ret);
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}
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return ret;
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}
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int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
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{
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struct platform_device *pdev = msm_host->pdev;
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int ret = 0;
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msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
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if (IS_ERR(msm_host->byte_intf_clk)) {
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ret = PTR_ERR(msm_host->byte_intf_clk);
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pr_err("%s: can't find byte_intf clock. ret=%d\n",
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__func__, ret);
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}
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return ret;
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}
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static int dsi_clk_init(struct msm_dsi_host *msm_host)
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{
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struct platform_device *pdev = msm_host->pdev;
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@ -498,7 +546,7 @@ int msm_dsi_runtime_resume(struct device *dev)
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return dsi_bus_clk_enable(msm_host);
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}
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static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
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int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
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{
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int ret;
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@ -566,7 +614,7 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
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return ret;
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}
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static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
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int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
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{
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int ret;
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@ -644,6 +692,23 @@ static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
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return dsi_link_clk_enable_v2(msm_host);
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}
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void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
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{
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clk_disable_unprepare(msm_host->esc_clk);
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clk_disable_unprepare(msm_host->pixel_clk);
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if (msm_host->byte_intf_clk)
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clk_disable_unprepare(msm_host->byte_intf_clk);
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clk_disable_unprepare(msm_host->byte_clk);
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}
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void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
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{
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clk_disable_unprepare(msm_host->pixel_clk);
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clk_disable_unprepare(msm_host->src_clk);
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clk_disable_unprepare(msm_host->esc_clk);
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clk_disable_unprepare(msm_host->byte_clk);
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}
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static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
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{
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const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
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@ -662,6 +727,84 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
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}
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}
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int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host)
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{
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struct drm_display_mode *mode = msm_host->mode;
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u8 lanes = msm_host->lanes;
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u32 bpp = dsi_get_bpp(msm_host->format);
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u32 pclk_rate;
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pclk_rate = mode->clock * 1000;
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if (lanes > 0) {
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msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
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} else {
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pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
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msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
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}
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DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
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msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
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return 0;
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}
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int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host)
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{
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struct drm_display_mode *mode = msm_host->mode;
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u8 lanes = msm_host->lanes;
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u32 bpp = dsi_get_bpp(msm_host->format);
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u32 pclk_rate;
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unsigned int esc_mhz, esc_div;
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unsigned long byte_mhz;
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pclk_rate = mode->clock * 1000;
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if (lanes > 0) {
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msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
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} else {
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pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
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msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
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}
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DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
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msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
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/*
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* esc clock is byte clock followed by a 4 bit divider,
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* we need to find an escape clock frequency within the
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* mipi DSI spec range within the maximum divider limit
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* We iterate here between an escape clock frequencey
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* between 20 Mhz to 5 Mhz and pick up the first one
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* that can be supported by our divider
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*/
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byte_mhz = msm_host->byte_clk_rate / 1000000;
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for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
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esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
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/*
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* TODO: Ideally, we shouldn't know what sort of divider
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* is available in mmss_cc, we're just assuming that
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* it'll always be a 4 bit divider. Need to come up with
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* a better way here.
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*/
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if (esc_div >= 1 && esc_div <= 16)
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break;
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}
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if (esc_mhz < 5)
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return -EINVAL;
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msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
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DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
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msm_host->src_clk_rate);
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return 0;
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}
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static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
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{
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struct drm_display_mode *mode = msm_host->mode;
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@ -1015,6 +1158,41 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
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}
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}
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int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
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{
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struct drm_device *dev = msm_host->dev;
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struct msm_drm_private *priv = dev->dev_private;
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uint64_t iova;
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u8 *data;
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data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED,
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priv->kms->aspace,
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&msm_host->tx_gem_obj, &iova);
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if (IS_ERR(data)) {
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msm_host->tx_gem_obj = NULL;
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return PTR_ERR(data);
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}
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msm_host->tx_size = msm_host->tx_gem_obj->size;
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return 0;
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}
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int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
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{
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struct drm_device *dev = msm_host->dev;
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msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
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&msm_host->tx_buf_paddr, GFP_KERNEL);
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if (!msm_host->tx_buf)
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return -ENOMEM;
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msm_host->tx_size = size;
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return 0;
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}
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/* dsi_cmd */
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static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
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{
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@ -1089,6 +1267,21 @@ static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
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msm_host->tx_buf_paddr);
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}
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void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
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{
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return msm_gem_get_vaddr(msm_host->tx_gem_obj);
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}
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void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
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{
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return msm_host->tx_buf;
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}
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void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
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{
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msm_gem_put_vaddr(msm_host->tx_gem_obj);
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}
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/*
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* prepare cmd buffer to be txed
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*/
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@ -1190,6 +1383,27 @@ static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
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return msg->rx_len;
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}
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int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
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{
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struct drm_device *dev = msm_host->dev;
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struct msm_drm_private *priv = dev->dev_private;
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if (!dma_base)
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return -EINVAL;
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return msm_gem_get_iova(msm_host->tx_gem_obj,
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priv->kms->aspace, dma_base);
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}
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int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
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{
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if (!dma_base)
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return -EINVAL;
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*dma_base = msm_host->tx_buf_paddr;
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return 0;
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}
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static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
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{
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const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
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