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ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unset
TE/RE bit of T/RCSR will remain set untill the current frame is physically finished. The FIFO reset operation should wait this bit's totally cleared rather than ignoring its status which might cause TE/RE disabling failed. This patch adds delay and timeout to wait for its completion before FIFO reset. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -327,7 +327,7 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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u32 xcsr;
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u32 xcsr, count = 100;
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/*
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* The transmitter bit clock and frame sync are to be
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@ -369,11 +369,20 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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if (!(xcsr & FSL_SAI_CSR_FRDE)) {
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/* Disable both directions and reset their FIFOs */
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_TERE | FSL_SAI_CSR_FR,
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FSL_SAI_CSR_FR);
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FSL_SAI_CSR_TERE, 0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_TERE | FSL_SAI_CSR_FR,
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FSL_SAI_CSR_FR);
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FSL_SAI_CSR_TERE, 0);
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/* TERE will remain set till the end of current frame */
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do {
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udelay(10);
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regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
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} while (--count && xcsr & FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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}
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break;
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default:
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