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[MIPS] Fix timer/performance interrupt detection

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Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chris Dearman 2007-06-21 12:59:57 +01:00 committed by Ralf Baechle
parent 6fb88ce04f
commit c3e838a2cb
1 changed files with 4 additions and 4 deletions
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8
arch/mips/kernel/traps.c
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@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void)
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
cp0_perfcount_irq = -1;
cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
if (cp0_perfcount_irq != cp0_compare_irq)
cp0_perfcount_irq = -1;
cp0_perfcount_irq = -1;
}
#ifdef CONFIG_MIPS_MT_SMTC