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arm/arm64: KVM: vgic: handle out-of-range MMIO accesses
Now that we can (almost) dynamically size the number of interrupts, we're facing an interesting issue: We have to evaluate at runtime whether or not an access hits a valid register, based on the sizing of this particular instance of the distributor. Furthermore, the GIC spec says that accessing a reserved register is RAZ/WI. For this, add a new field to our range structure, indicating the number of bits a single interrupts uses. That allows us to find out whether or not the access is in range. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -32,6 +32,7 @@
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#define VGIC_V2_MAX_LRS (1 << 6)
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#define VGIC_V3_MAX_LRS 16
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#define VGIC_MAX_IRQS 1024
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/* Sanity checks... */
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#if (KVM_MAX_VCPUS > 8)
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@ -42,7 +43,7 @@
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#error "VGIC_NR_IRQS must be a multiple of 32"
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#endif
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#if (VGIC_NR_IRQS > 1024)
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#if (VGIC_NR_IRQS > VGIC_MAX_IRQS)
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#error "VGIC_NR_IRQS must be <= 1024"
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#endif
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@ -895,6 +895,7 @@ static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
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struct mmio_range {
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phys_addr_t base;
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unsigned long len;
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int bits_per_irq;
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bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
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phys_addr_t offset);
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};
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@ -903,56 +904,67 @@ static const struct mmio_range vgic_dist_ranges[] = {
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{
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.base = GIC_DIST_CTRL,
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.len = 12,
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.bits_per_irq = 0,
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.handle_mmio = handle_mmio_misc,
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},
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{
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.base = GIC_DIST_IGROUP,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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},
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{
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.base = GIC_DIST_ENABLE_SET,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_set_enable_reg,
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},
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{
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.base = GIC_DIST_ENABLE_CLEAR,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_clear_enable_reg,
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},
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{
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.base = GIC_DIST_PENDING_SET,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_set_pending_reg,
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},
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{
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.base = GIC_DIST_PENDING_CLEAR,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_clear_pending_reg,
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},
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{
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.base = GIC_DIST_ACTIVE_SET,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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},
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{
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.base = GIC_DIST_ACTIVE_CLEAR,
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.len = VGIC_NR_IRQS / 8,
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.len = VGIC_MAX_IRQS / 8,
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.bits_per_irq = 1,
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.handle_mmio = handle_mmio_raz_wi,
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},
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{
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.base = GIC_DIST_PRI,
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.len = VGIC_NR_IRQS,
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.len = VGIC_MAX_IRQS,
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.bits_per_irq = 8,
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.handle_mmio = handle_mmio_priority_reg,
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},
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{
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.base = GIC_DIST_TARGET,
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.len = VGIC_NR_IRQS,
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.len = VGIC_MAX_IRQS,
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.bits_per_irq = 8,
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.handle_mmio = handle_mmio_target_reg,
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},
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{
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.base = GIC_DIST_CONFIG,
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.len = VGIC_NR_IRQS / 4,
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.len = VGIC_MAX_IRQS / 4,
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.bits_per_irq = 2,
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.handle_mmio = handle_mmio_cfg_reg,
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},
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{
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@ -990,6 +1002,22 @@ struct mmio_range *find_matching_range(const struct mmio_range *ranges,
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return NULL;
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}
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static bool vgic_validate_access(const struct vgic_dist *dist,
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const struct mmio_range *range,
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unsigned long offset)
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{
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int irq;
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if (!range->bits_per_irq)
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return true; /* Not an irq-based access */
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irq = offset * 8 / range->bits_per_irq;
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if (irq >= dist->nr_irqs)
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return false;
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return true;
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}
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/**
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* vgic_handle_mmio - handle an in-kernel MMIO access
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* @vcpu: pointer to the vcpu performing the access
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@ -1029,7 +1057,13 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
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spin_lock(&vcpu->kvm->arch.vgic.lock);
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offset = mmio->phys_addr - range->base - base;
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updated_state = range->handle_mmio(vcpu, mmio, offset);
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if (vgic_validate_access(dist, range, offset)) {
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updated_state = range->handle_mmio(vcpu, mmio, offset);
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} else {
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vgic_reg_access(mmio, NULL, offset,
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ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
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updated_state = false;
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}
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spin_unlock(&vcpu->kvm->arch.vgic.lock);
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kvm_prepare_mmio(run, mmio);
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kvm_handle_mmio_return(vcpu, run);
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