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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 00:40:55 +07:00
drm/tegra: sor: Do not support deep color modes
Current generations of Tegra do not support deep color modes, so force 8 bits per color even if the connected monitor or panel supports more. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
2bd1dd399f
commit
c31efa7a30
@ -190,6 +190,18 @@ struct tegra_sor {
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struct regulator *hdmi_supply;
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};
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struct tegra_sor_state {
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struct drm_connector_state base;
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unsigned int bpc;
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};
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static inline struct tegra_sor_state *
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to_sor_state(struct drm_connector_state *state)
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{
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return container_of(state, struct tegra_sor_state, base);
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}
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struct tegra_sor_config {
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u32 bits_per_pixel;
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@ -720,7 +732,7 @@ static void tegra_sor_apply_config(struct tegra_sor *sor,
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static void tegra_sor_mode_set(struct tegra_sor *sor,
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const struct drm_display_mode *mode,
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const struct drm_display_info *info)
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struct tegra_sor_state *state)
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{
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struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
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unsigned int vbe, vse, hbe, hse, vbs, hbs;
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@ -746,7 +758,19 @@ static void tegra_sor_mode_set(struct tegra_sor *sor,
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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value |= SOR_STATE_ASY_VSYNCPOL;
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switch (info->bpc) {
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switch (state->bpc) {
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case 16:
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value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
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break;
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case 12:
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value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
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break;
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case 10:
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value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
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break;
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case 8:
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value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
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break;
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@ -756,7 +780,7 @@ static void tegra_sor_mode_set(struct tegra_sor *sor,
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break;
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default:
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BUG();
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value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
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break;
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}
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@ -1173,6 +1197,22 @@ static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
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sor->debugfs = NULL;
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}
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static void tegra_sor_connector_reset(struct drm_connector *connector)
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{
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struct tegra_sor_state *state;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return;
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if (connector->state) {
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__drm_atomic_helper_connector_destroy_state(connector->state);
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kfree(connector->state);
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}
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__drm_atomic_helper_connector_reset(connector, &state->base);
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}
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static enum drm_connector_status
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tegra_sor_connector_detect(struct drm_connector *connector, bool force)
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{
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@ -1185,13 +1225,28 @@ tegra_sor_connector_detect(struct drm_connector *connector, bool force)
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return tegra_output_connector_detect(connector, force);
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}
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static struct drm_connector_state *
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tegra_sor_connector_duplicate_state(struct drm_connector *connector)
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{
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struct tegra_sor_state *state = to_sor_state(connector->state);
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struct tegra_sor_state *copy;
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copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
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if (!copy)
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return NULL;
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__drm_atomic_helper_connector_duplicate_state(connector, ©->base);
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return ©->base;
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}
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static const struct drm_connector_funcs tegra_sor_connector_funcs = {
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.dpms = drm_atomic_helper_connector_dpms,
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.reset = drm_atomic_helper_connector_reset,
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.reset = tegra_sor_connector_reset,
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.detect = tegra_sor_connector_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = tegra_output_connector_destroy,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_duplicate_state = tegra_sor_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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@ -1329,14 +1384,14 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
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struct tegra_sor *sor = to_sor(output);
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struct tegra_sor_config config;
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struct drm_display_info *info;
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struct tegra_sor_state *state;
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struct drm_dp_link link;
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u8 rate, lanes;
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unsigned int i;
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int err = 0;
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u32 value;
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info = &output->connector.display_info;
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state = to_sor_state(output->connector.state);
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err = clk_prepare_enable(sor->clk);
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if (err < 0)
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@ -1363,7 +1418,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
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memset(&config, 0, sizeof(config));
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config.bits_per_pixel = output->connector.display_info.bpc * 3;
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config.bits_per_pixel = state->bpc * 3;
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err = tegra_sor_compute_config(sor, mode, &config, &link);
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if (err < 0)
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@ -1596,7 +1651,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder)
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value |= SOR_STATE_ASY_PROTOCOL_DP_A;
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tegra_sor_writel(sor, value, SOR_STATE1);
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tegra_sor_mode_set(sor, mode, info);
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tegra_sor_mode_set(sor, mode, state);
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/* PWM setup */
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err = tegra_sor_setup_pwm(sor, 250);
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@ -1629,11 +1684,15 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_connector_state *conn_state)
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{
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struct tegra_output *output = encoder_to_output(encoder);
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struct tegra_sor_state *state = to_sor_state(conn_state);
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struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
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unsigned long pclk = crtc_state->mode.clock * 1000;
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struct tegra_sor *sor = to_sor(output);
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struct drm_display_info *info;
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int err;
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info = &output->connector.display_info;
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err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
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pclk, 0);
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if (err < 0) {
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@ -1641,6 +1700,18 @@ tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
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return err;
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}
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switch (info->bpc) {
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case 8:
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case 6:
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state->bpc = info->bpc;
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break;
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default:
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DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
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state->bpc = 8;
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break;
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}
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return 0;
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}
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@ -1815,14 +1886,14 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
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struct tegra_sor_hdmi_settings *settings;
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struct tegra_sor *sor = to_sor(output);
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struct tegra_sor_state *state;
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struct drm_display_mode *mode;
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struct drm_display_info *info;
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unsigned int div;
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u32 value;
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int err;
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state = to_sor_state(output->connector.state);
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mode = &encoder->crtc->state->adjusted_mode;
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info = &output->connector.display_info;
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err = clk_prepare_enable(sor->clk);
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if (err < 0)
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@ -2055,7 +2126,7 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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value &= ~DITHER_CONTROL_MASK;
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value &= ~BASE_COLOR_SIZE_MASK;
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switch (info->bpc) {
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switch (state->bpc) {
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case 6:
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value |= BASE_COLOR_SIZE_666;
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break;
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@ -2065,7 +2136,8 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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break;
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default:
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WARN(1, "%u bits-per-color not supported\n", info->bpc);
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WARN(1, "%u bits-per-color not supported\n", state->bpc);
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value |= BASE_COLOR_SIZE_888;
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break;
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}
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@ -2087,7 +2159,7 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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value |= SOR_HEAD_STATE_COLORSPACE_RGB;
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tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
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tegra_sor_mode_set(sor, mode, info);
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tegra_sor_mode_set(sor, mode, state);
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tegra_sor_update(sor);
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@ -27,6 +27,9 @@
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#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
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#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17)
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#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17)
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#define SOR_STATE_ASY_PIXELDEPTH_BPP_30_444 (0x6 << 17)
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#define SOR_STATE_ASY_PIXELDEPTH_BPP_36_444 (0x8 << 17)
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#define SOR_STATE_ASY_PIXELDEPTH_BPP_48_444 (0x9 << 17)
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#define SOR_STATE_ASY_VSYNCPOL (1 << 13)
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#define SOR_STATE_ASY_HSYNCPOL (1 << 12)
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#define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8)
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