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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-09 00:56:39 +07:00
OMAPDSS: HDMI: split PLL enable & config
At the moment we have one function, hdmi_pll_enable, which enables the PLL and writes the PLL configuration to registers. To make the HDMI PLL ahere to the DSS PLL API, split the hdmi_pll_enable into two parts: hdmi_pll_enable which enables the PLL HW, and hdmi_pll_set_config which writes the config. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -316,6 +316,7 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
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/* HDMI PLL funcs */
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int hdmi_pll_enable(struct hdmi_pll_data *pll);
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void hdmi_pll_disable(struct hdmi_pll_data *pll);
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int hdmi_pll_set_config(struct hdmi_pll_data *pll);
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
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unsigned long target_tmds);
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@ -196,13 +196,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi_pll_enable(&hdmi.pll);
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if (r) {
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DSSDBG("Failed to lock PLL\n");
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DSSERR("Failed to enable PLL\n");
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goto err_pll_enable;
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}
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r = hdmi_pll_set_config(&hdmi.pll);
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if (r) {
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DSSERR("Failed to configure PLL\n");
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goto err_pll_cfg;
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}
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r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
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hdmi.pll.info.clkout);
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if (r) {
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@ -241,6 +246,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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err_phy_cfg:
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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err_phy_pwr:
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err_pll_cfg:
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hdmi_pll_disable(&hdmi.pll);
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err_pll_enable:
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hdmi_power_off_core(dssdev);
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@ -214,13 +214,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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hdmi_wp_set_irqstatus(&hdmi.wp,
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hdmi_wp_get_irqstatus(&hdmi.wp));
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi_pll_enable(&hdmi.pll);
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if (r) {
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DSSDBG("Failed to lock PLL\n");
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DSSERR("Failed to enable PLL\n");
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goto err_pll_enable;
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}
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r = hdmi_pll_set_config(&hdmi.pll);
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if (r) {
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DSSERR("Failed to configure PLL\n");
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goto err_pll_cfg;
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}
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r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
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hdmi.pll.info.clkout);
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if (r) {
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@ -259,6 +264,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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err_phy_pwr:
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err_phy_cfg:
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err_pll_cfg:
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hdmi_pll_disable(&hdmi.pll);
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err_pll_enable:
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hdmi_power_off_core(dssdev);
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@ -103,7 +103,7 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
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pi->clkout = clkout;
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}
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static int hdmi_pll_config(struct hdmi_pll_data *pll)
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int hdmi_pll_set_config(struct hdmi_pll_data *pll)
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{
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u32 r;
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struct hdmi_pll_info *fmt = &pll->info;
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@ -179,10 +179,6 @@ int hdmi_pll_enable(struct hdmi_pll_data *pll)
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if (r)
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return r;
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r = hdmi_pll_config(pll);
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if (r)
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return r;
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return 0;
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}
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