mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 19:10:51 +07:00
[ALSA] oxygen: add register definitions
Add more symbols for registers and register fields. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Clemens Ladisch
Jaroslav Kysela
parent
4052ce4cbf
commit
c2353a0826
@ -102,18 +102,21 @@ static void ak4396_write(struct oxygen *chip, unsigned int codec,
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static const u8 codec_spi_map[4] = {
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0, 1, 2, 4
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};
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oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE |
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oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_2 |
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OXYGEN_SPI_CLOCK_160 |
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(codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
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OXYGEN_SPI_MAGIC,
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OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
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AK4396_WRITE | (reg << 8) | value);
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}
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static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
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{
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oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE |
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oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
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OXYGEN_SPI_DATA_LENGTH_2 |
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(3 << OXYGEN_SPI_CODEC_SHIFT),
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OXYGEN_SPI_CLOCK_160 |
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(3 << OXYGEN_SPI_CODEC_SHIFT) |
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OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
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(reg << 9) | value);
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}
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@ -119,7 +119,7 @@ void oxygen_write_ac97(struct oxygen *chip, unsigned int codec,
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udelay(5);
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oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
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/* require two "completed" writes, just to be sure */
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if (oxygen_ac97_wait(chip, OXYGEN_AC97_WRITE_COMPLETE) >= 0 &&
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if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_WRITE_DONE) >= 0 &&
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++succeeded >= 2)
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return;
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}
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@ -141,7 +141,7 @@ u16 oxygen_read_ac97(struct oxygen *chip, unsigned int codec,
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udelay(5);
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oxygen_write32(chip, OXYGEN_AC97_REGS, reg);
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udelay(10);
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if (oxygen_ac97_wait(chip, OXYGEN_AC97_READ_COMPLETE) >= 0) {
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if (oxygen_ac97_wait(chip, OXYGEN_AC97_INT_READ_DONE) >= 0) {
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u16 value = oxygen_read16(chip, OXYGEN_AC97_REGS);
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/* we require two consecutive reads of the same value */
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if (value == last_read)
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@ -51,11 +51,11 @@ static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
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OXYGEN_CHANNEL_SPDIF |
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OXYGEN_CHANNEL_MULTICH |
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OXYGEN_CHANNEL_AC97 |
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OXYGEN_INT_SPDIF_IN_CHANGE |
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OXYGEN_INT_SPDIF_IN_DETECT |
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OXYGEN_INT_GPIO);
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if (clear) {
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if (clear & OXYGEN_INT_SPDIF_IN_CHANGE)
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chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_CHANGE;
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if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
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chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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chip->interrupt_mask & ~clear);
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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@ -70,10 +70,10 @@ static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
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if ((elapsed_streams & (1 << i)) && chip->streams[i])
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snd_pcm_period_elapsed(chip->streams[i]);
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if (status & OXYGEN_INT_SPDIF_IN_CHANGE) {
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if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
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spin_lock(&chip->reg_lock);
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i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if (i & OXYGEN_SPDIF_IN_CHANGE) {
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if (i & OXYGEN_SPDIF_RATE_INT) {
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
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schedule_work(&chip->spdif_input_bits_work);
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}
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@ -95,28 +95,32 @@ static void oxygen_spdif_input_bits_changed(struct work_struct *work)
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spdif_input_bits_work);
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spin_lock_irq(&chip->reg_lock);
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oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_IN_INVERT);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_unlock_irq(&chip->reg_lock);
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msleep(1);
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if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
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& OXYGEN_SPDIF_IN_VALID)) {
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& OXYGEN_SPDIF_LOCK_STATUS)) {
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spin_lock_irq(&chip->reg_lock);
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oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_INVERT);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_192,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_unlock_irq(&chip->reg_lock);
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msleep(1);
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if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
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& OXYGEN_SPDIF_IN_VALID)) {
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& OXYGEN_SPDIF_LOCK_STATUS)) {
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spin_lock_irq(&chip->reg_lock);
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oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_INVERT);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_unlock_irq(&chip->reg_lock);
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}
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}
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if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
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spin_lock_irq(&chip->reg_lock);
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chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE;
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chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
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chip->interrupt_mask);
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spin_unlock_irq(&chip->reg_lock);
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@ -194,7 +198,8 @@ static void __devinit oxygen_init(struct oxygen *chip)
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chip->revision = 1;
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if (chip->revision == 1)
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oxygen_set_bits8(chip, OXYGEN_MISC, OXYGEN_MISC_MAGIC);
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oxygen_set_bits8(chip, OXYGEN_MISC,
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OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
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i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
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chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
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@ -207,7 +212,7 @@ static void __devinit oxygen_init(struct oxygen *chip)
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oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 0x010a);
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oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 0x010a);
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oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 0x010a);
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oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_MAGIC2);
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oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_RATE_MASK);
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oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
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oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 0xe100);
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oxygen_write8(chip, OXYGEN_REC_ROUTING, 0x10);
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@ -220,9 +225,17 @@ static void __devinit oxygen_init(struct oxygen *chip)
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oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0x00);
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if (chip->has_ac97_0) {
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oxygen_clear_bits16(chip, OXYGEN_AC97_OUT_CONFIG,
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OXYGEN_AC97_OUT_MAGIC3);
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OXYGEN_AC97_CODEC0_FRONTL |
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OXYGEN_AC97_CODEC0_FRONTR |
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OXYGEN_AC97_CODEC0_SIDEL |
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OXYGEN_AC97_CODEC0_SIDER |
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OXYGEN_AC97_CODEC0_CENTER |
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OXYGEN_AC97_CODEC0_BASE |
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OXYGEN_AC97_CODEC0_REARL |
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OXYGEN_AC97_CODEC0_REARR);
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oxygen_set_bits16(chip, OXYGEN_AC97_IN_CONFIG,
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OXYGEN_AC97_IN_MAGIC3);
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OXYGEN_AC97_CODEC0_LINEL |
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OXYGEN_AC97_CODEC0_LINER);
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oxygen_write_ac97(chip, 0, AC97_RESET, 0);
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msleep(1);
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oxygen_ac97_set_bits(chip, 0, 0x70, 0x0300);
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@ -349,7 +362,7 @@ int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
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oxygen_proc_init(chip);
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spin_lock_irq(&chip->reg_lock);
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chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_CHANGE;
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chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
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oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
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spin_unlock_irq(&chip->reg_lock);
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@ -308,9 +308,10 @@ static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
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}
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}
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static unsigned int oxygen_i2s_magic2(struct snd_pcm_hw_params *hw_params)
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static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
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{
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return params_rate(hw_params) <= 96000 ? 0x10 : 0x00;
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return params_rate(hw_params) <= 96000
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? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
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}
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static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
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@ -388,12 +389,12 @@ static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
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OXYGEN_REC_FORMAT_A_MASK);
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oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
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oxygen_rate(hw_params) |
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oxygen_i2s_magic2(hw_params) |
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oxygen_i2s_mclk(hw_params) |
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chip->model->adc_i2s_format |
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oxygen_i2s_bits(hw_params),
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OXYGEN_I2S_RATE_MASK |
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OXYGEN_I2S_FORMAT_MASK |
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OXYGEN_I2S_MAGIC2_MASK |
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OXYGEN_I2S_MCLK_MASK |
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OXYGEN_I2S_BITS_MASK);
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oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
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spin_unlock_irq(&chip->reg_lock);
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@ -420,12 +421,12 @@ static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
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OXYGEN_REC_FORMAT_B_MASK);
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oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
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oxygen_rate(hw_params) |
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oxygen_i2s_magic2(hw_params) |
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oxygen_i2s_mclk(hw_params) |
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chip->model->adc_i2s_format |
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oxygen_i2s_bits(hw_params),
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OXYGEN_I2S_RATE_MASK |
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OXYGEN_I2S_FORMAT_MASK |
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OXYGEN_I2S_MAGIC2_MASK |
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OXYGEN_I2S_MCLK_MASK |
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OXYGEN_I2S_BITS_MASK);
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oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
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spin_unlock_irq(&chip->reg_lock);
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@ -514,24 +515,6 @@ static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
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return 0;
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}
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static int oxygen_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct oxygen *chip = snd_pcm_substream_chip(substream);
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int err;
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err = oxygen_hw_params(substream, hw_params);
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if (err < 0)
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return err;
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spin_lock_irq(&chip->reg_lock);
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oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
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oxygen_format(hw_params) << OXYGEN_AC97_FORMAT_SHIFT,
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OXYGEN_AC97_FORMAT_MASK);
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spin_unlock_irq(&chip->reg_lock);
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return 0;
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}
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static int oxygen_hw_free(struct snd_pcm_substream *substream)
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{
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struct oxygen *chip = snd_pcm_substream_chip(substream);
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@ -680,7 +663,7 @@ static struct snd_pcm_ops oxygen_ac97_ops = {
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.open = oxygen_ac97_open,
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.close = oxygen_close,
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.ioctl = snd_pcm_lib_ioctl,
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.hw_params = oxygen_ac97_hw_params,
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.hw_params = oxygen_hw_params,
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.hw_free = oxygen_hw_free,
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.prepare = oxygen_prepare,
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.trigger = oxygen_trigger,
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@ -23,8 +23,8 @@
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/* multichannel playback channel */
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#define OXYGEN_DMA_MULTICH_ADDRESS 0x20
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#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 32 bits */
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#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 32 bits */
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#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 24 bits */
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#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 24 bits */
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/* AC'97 (front panel) playback channel */
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#define OXYGEN_DMA_AC97_ADDRESS 0x30
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@ -41,6 +41,9 @@
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#define OXYGEN_CHANNEL_MULTICH 0x10
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#define OXYGEN_CHANNEL_AC97 0x20
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#define OXYGEN_DMA_PAUSE 0x41 /* 1 = pause */
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/* OXYGEN_CHANNEL_* */
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#define OXYGEN_DMA_RESET 0x42
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/* OXYGEN_CHANNEL_* */
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@ -50,19 +53,37 @@
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#define OXYGEN_PLAY_CHANNELS_4 0x01
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#define OXYGEN_PLAY_CHANNELS_6 0x02
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#define OXYGEN_PLAY_CHANNELS_8 0x03
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#define OXYGEN_DMA_A_BURST_MASK 0x04
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#define OXYGEN_DMA_A_BURST_8 0x00 /* dwords */
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#define OXYGEN_DMA_A_BURST_16 0x04
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#define OXYGEN_DMA_MULTICH_BURST_MASK 0x08
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#define OXYGEN_DMA_MULTICH_BURST_8 0x00
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#define OXYGEN_DMA_MULTICH_BURST_16 0x08
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#define OXYGEN_INTERRUPT_MASK 0x44
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/* OXYGEN_CHANNEL_* */
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#define OXYGEN_INT_SPDIF_IN_CHANGE 0x0100
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#define OXYGEN_INT_SPDIF_IN_DETECT 0x0100
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#define OXYGEN_INT_MCU 0x0200
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#define OXYGEN_INT_2WIRE 0x0400
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#define OXYGEN_INT_GPIO 0x0800
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#define OXYGEN_INT_MCB 0x2000
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#define OXYGEN_INT_AC97 0x4000
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#define OXYGEN_INTERRUPT_STATUS 0x46
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/* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */
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#define OXYGEN_INT_MIDI 0x1000
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#define OXYGEN_MISC 0x48
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#define OXYGEN_MISC_MAGIC 0x20
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#define OXYGEN_MISC_WRITE_PCI_SUBID 0x01
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#define OXYGEN_MISC_LATENCY_3F 0x02
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#define OXYGEN_MISC_REC_C_FROM_SPDIF 0x04
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#define OXYGEN_MISC_REC_B_FROM_AC97 0x08
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#define OXYGEN_MISC_REC_A_FROM_MULTICH 0x10
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#define OXYGEN_MISC_PCI_MEM_W_1_CLOCK 0x20
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#define OXYGEN_MISC_MIDI 0x40
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#define OXYGEN_MISC_CRYSTAL_MASK 0x80
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#define OXYGEN_MISC_CRYSTAL_24576 0x00
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#define OXYGEN_MISC_CRYSTAL_27 0x80 /* MHz */
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#define OXYGEN_REC_FORMAT 0x4a
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#define OXYGEN_REC_FORMAT_A_MASK 0x03
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@ -80,23 +101,32 @@
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#define OXYGEN_SPDIF_FORMAT_SHIFT 0
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#define OXYGEN_MULTICH_FORMAT_MASK 0x0c
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#define OXYGEN_MULTICH_FORMAT_SHIFT 2
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#define OXYGEN_AC97_FORMAT_MASK 0x30
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#define OXYGEN_AC97_FORMAT_SHIFT 4
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/* OXYGEN_FORMAT_* */
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#define OXYGEN_REC_CHANNELS 0x4c
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#define OXYGEN_REC_A_CHANNELS_MASK 0x07
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#define OXYGEN_REC_CHANNELS_2 0x00
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#define OXYGEN_REC_CHANNELS_4 0x01
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#define OXYGEN_REC_CHANNELS_6 0x03 /* or 0x02 */
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#define OXYGEN_REC_CHANNELS_8 0x04
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#define OXYGEN_REC_CHANNELS_MASK 0x07
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#define OXYGEN_REC_CHANNELS_2_2_2 0x00 /* DMA A, B, C */
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#define OXYGEN_REC_CHANNELS_4_2_2 0x01
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#define OXYGEN_REC_CHANNELS_6_0_2 0x02
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#define OXYGEN_REC_CHANNELS_6_2_0 0x03
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#define OXYGEN_REC_CHANNELS_8_0_0 0x04
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#define OXYGEN_FUNCTION 0x50
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#define OXYGEN_FUNCTION_CLOCK_MASK 0x01
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#define OXYGEN_FUNCTION_CLOCK_PLL 0x00
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#define OXYGEN_FUNCTION_CLOCK_CRYSTAL 0x01
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#define OXYGEN_FUNCTION_RESET_CODEC 0x02
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#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80
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#define OXYGEN_FUNCTION_RESET_POL 0x04
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#define OXYGEN_FUNCTION_PWDN 0x08
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#define OXYGEN_FUNCTION_PWDN_EN 0x10
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#define OXYGEN_FUNCTION_PWDN_POL 0x20
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#define OXYGEN_FUNCTION_2WIRE_SPI_MASK 0x40
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#define OXYGEN_FUNCTION_SPI 0x00
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#define OXYGEN_FUNCTION_2WIRE 0x40
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#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 /* 0 = EEPROM */
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#define OXYGEN_I2S_MULTICH_FORMAT 0x60
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#define OXYGEN_I2S_RATE_MASK 0x0007
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#define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */
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#define OXYGEN_RATE_32000 0x0000
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#define OXYGEN_RATE_44100 0x0001
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#define OXYGEN_RATE_48000 0x0002
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@ -108,12 +138,21 @@
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#define OXYGEN_I2S_FORMAT_MASK 0x0008
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#define OXYGEN_I2S_FORMAT_I2S 0x0000
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#define OXYGEN_I2S_FORMAT_LJUST 0x0008
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#define OXYGEN_I2S_MAGIC2_MASK 0x0030
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#define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */
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#define OXYGEN_I2S_MCLK_128 0x0000
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#define OXYGEN_I2S_MCLK_256 0x0010
|
||||
#define OXYGEN_I2S_MCLK_512 0x0020
|
||||
#define OXYGEN_I2S_BITS_MASK 0x00c0
|
||||
#define OXYGEN_I2S_BITS_16 0x0000
|
||||
#define OXYGEN_I2S_BITS_20 0x0040
|
||||
#define OXYGEN_I2S_BITS_24 0x0080
|
||||
#define OXYGEN_I2S_BITS_32 0x00c0
|
||||
#define OXYGEN_I2S_MASTER 0x0100
|
||||
#define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */
|
||||
#define OXYGEN_I2S_BCLK_64 0x0000
|
||||
#define OXYGEN_I2S_BCLK_128 0x0200
|
||||
#define OXYGEN_I2S_BCLK_256 0x0400
|
||||
#define OXYGEN_I2S_MUTE_MCLK 0x0800
|
||||
|
||||
#define OXYGEN_I2S_A_FORMAT 0x62
|
||||
#define OXYGEN_I2S_B_FORMAT 0x64
|
||||
@ -122,12 +161,21 @@
|
||||
|
||||
#define OXYGEN_SPDIF_CONTROL 0x70
|
||||
#define OXYGEN_SPDIF_OUT_ENABLE 0x00000002
|
||||
#define OXYGEN_SPDIF_LOOPBACK 0x00000004
|
||||
#define OXYGEN_SPDIF_MAGIC2 0x00000020
|
||||
#define OXYGEN_SPDIF_MAGIC3 0x00000040
|
||||
#define OXYGEN_SPDIF_IN_VALID 0x00001000
|
||||
#define OXYGEN_SPDIF_IN_CHANGE 0x00008000 /* r/wc */
|
||||
#define OXYGEN_SPDIF_IN_INVERT 0x00010000 /* ? */
|
||||
#define OXYGEN_SPDIF_LOOPBACK 0x00000004 /* in to out */
|
||||
#define OXYGEN_SPDIF_SENSE_MASK 0x00000008
|
||||
#define OXYGEN_SPDIF_LOCK_MASK 0x00000010
|
||||
#define OXYGEN_SPDIF_RATE_MASK 0x00000020
|
||||
#define OXYGEN_SPDIF_SPDVALID 0x00000040
|
||||
#define OXYGEN_SPDIF_SENSE_PAR 0x00000200
|
||||
#define OXYGEN_SPDIF_LOCK_PAR 0x00000400
|
||||
#define OXYGEN_SPDIF_SENSE_STATUS 0x00000800
|
||||
#define OXYGEN_SPDIF_LOCK_STATUS 0x00001000
|
||||
#define OXYGEN_SPDIF_SENSE_INT 0x00002000 /* r/wc */
|
||||
#define OXYGEN_SPDIF_LOCK_INT 0x00004000 /* r/wc */
|
||||
#define OXYGEN_SPDIF_RATE_INT 0x00008000 /* r/wc */
|
||||
#define OXYGEN_SPDIF_IN_CLOCK_MASK 0x00010000
|
||||
#define OXYGEN_SPDIF_IN_CLOCK_96 0x00000000 /* <= 96 kHz */
|
||||
#define OXYGEN_SPDIF_IN_CLOCK_192 0x00010000 /* > 96 kHz */
|
||||
#define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000
|
||||
#define OXYGEN_SPDIF_OUT_RATE_SHIFT 24
|
||||
/* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */
|
||||
@ -146,10 +194,22 @@
|
||||
#define OXYGEN_SPDIF_INPUT_BITS 0x78
|
||||
/* 32 bits, IEC958_AES_* */
|
||||
|
||||
#define OXYGEN_EEPROM_CONTROL 0x80
|
||||
#define OXYGEN_EEPROM_ADDRESS_MASK 0x7f
|
||||
#define OXYGEN_EEPROM_DIR_MASK 0x80
|
||||
#define OXYGEN_EEPROM_DIR_READ 0x00
|
||||
#define OXYGEN_EEPROM_DIR_WRITE 0x80
|
||||
|
||||
#define OXYGEN_EEPROM_STATUS 0x81
|
||||
#define OXYGEN_EEPROM_VALID 0x40
|
||||
#define OXYGEN_EEPROM_BUSY 0x80
|
||||
|
||||
#define OXYGEN_EEPROM_DATA 0x82 /* 16 bits */
|
||||
|
||||
#define OXYGEN_2WIRE_CONTROL 0x90
|
||||
#define OXYGEN_2WIRE_DIR_MASK 0x01
|
||||
#define OXYGEN_2WIRE_DIR_WRITE 0x00 /* ? */
|
||||
#define OXYGEN_2WIRE_DIR_READ 0x01 /* ? */
|
||||
#define OXYGEN_2WIRE_DIR_WRITE 0x00
|
||||
#define OXYGEN_2WIRE_DIR_READ 0x01
|
||||
#define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */
|
||||
#define OXYGEN_2WIRE_ADDRESS_SHIFT 1
|
||||
|
||||
@ -157,17 +217,37 @@
|
||||
#define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */
|
||||
|
||||
#define OXYGEN_2WIRE_BUS_STATUS 0x94
|
||||
#define OXYGEN_2WIRE_BUSY 0x01
|
||||
#define OXYGEN_2WIRE_BUSY 0x0001
|
||||
#define OXYGEN_2WIRE_LENGTH_MASK 0x0002
|
||||
#define OXYGEN_2WIRE_LENGTH_8 0x0000
|
||||
#define OXYGEN_2WIRE_LENGTH_16 0x0002
|
||||
#define OXYGEN_2WIRE_MANUAL_READ 0x0004 /* 0 = auto read */
|
||||
#define OXYGEN_2WIRE_WRITE_MAP_ONLY 0x0008
|
||||
#define OXYGEN_2WIRE_SLAVE_AD_MASK 0x0030 /* AD0, AD1 */
|
||||
#define OXYGEN_2WIRE_INTERRUPT_MASK 0x0040 /* 0 = int. if not responding */
|
||||
#define OXYGEN_2WIRE_SLAVE_NO_RESPONSE 0x0080
|
||||
#define OXYGEN_2WIRE_SPEED_MASK 0x0100
|
||||
#define OXYGEN_2WIRE_SPEED_STANDARD 0x0000
|
||||
#define OXYGEN_2WIRE_SPEED_FAST 0x0100
|
||||
#define OXYGEN_2WIRE_CLOCK_SYNC 0x0200
|
||||
#define OXYGEN_2WIRE_BUS_RESET 0x0400
|
||||
|
||||
#define OXYGEN_SPI_CONTROL 0x98
|
||||
#define OXYGEN_SPI_BUSY 0x01 /* read */
|
||||
#define OXYGEN_SPI_TRIGGER_WRITE 0x01 /* write */
|
||||
#define OXYGEN_SPI_TRIGGER 0x01 /* write */
|
||||
#define OXYGEN_SPI_DATA_LENGTH_MASK 0x02
|
||||
#define OXYGEN_SPI_DATA_LENGTH_2 0x00
|
||||
#define OXYGEN_SPI_DATA_LENGTH_3 0x02
|
||||
#define OXYGEN_SPI_CLOCK_MASK 0xc0
|
||||
#define OXYGEN_SPI_CLOCK_160 0x00 /* ns */
|
||||
#define OXYGEN_SPI_CLOCK_320 0x40
|
||||
#define OXYGEN_SPI_CLOCK_640 0x80
|
||||
#define OXYGEN_SPI_CLOCK_1280 0xc0
|
||||
#define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */
|
||||
#define OXYGEN_SPI_CODEC_SHIFT 4
|
||||
#define OXYGEN_SPI_MAGIC 0x80
|
||||
#define OXYGEN_SPI_CEN_MASK 0x80
|
||||
#define OXYGEN_SPI_CEN_LATCH_CLOCK_LO 0x00
|
||||
#define OXYGEN_SPI_CEN_LATCH_CLOCK_HI 0x80
|
||||
|
||||
#define OXYGEN_SPI_DATA1 0x99
|
||||
#define OXYGEN_SPI_DATA2 0x9a
|
||||
@ -175,56 +255,161 @@
|
||||
|
||||
#define OXYGEN_MPU401 0xa0
|
||||
|
||||
#define OXYGEN_MPU401_CONTROL 0xa2
|
||||
#define OXYGEN_MPU401_LOOPBACK 0x01 /* TXD to RXD */
|
||||
|
||||
#define OXYGEN_GPI_DATA 0xa4
|
||||
/* bits 0..5 = pin XGPI0..XGPI5 */
|
||||
|
||||
#define OXYGEN_GPI_INTERRUPT_MASK 0xa5
|
||||
/* bits 0..5, 1 = enable */
|
||||
|
||||
#define OXYGEN_GPIO_DATA 0xa6
|
||||
/* bits 0..9 */
|
||||
|
||||
#define OXYGEN_GPIO_CONTROL 0xa8
|
||||
/* 0: input, 1: output */
|
||||
/* bits 0..9, 0 = input, 1 = output */
|
||||
#define OXYGEN_GPIO1_XSLAVE_RDY 0x8000
|
||||
|
||||
#define OXYGEN_GPIO_INTERRUPT_MASK 0xaa
|
||||
/* bits 0..9, 1 = enable */
|
||||
|
||||
#define OXYGEN_DEVICE_SENSE 0xac /* ? */
|
||||
#define OXYGEN_DEVICE_SENSE 0xac
|
||||
#define OXYGEN_HEAD_PHONE_DETECT 0x01
|
||||
#define OXYGEN_HEAD_PHONE_MASK 0x06
|
||||
#define OXYGEN_HEAD_PHONE_PASSIVE_SPK 0x00
|
||||
#define OXYGEN_HEAD_PHONE_HP 0x02
|
||||
#define OXYGEN_HEAD_PHONE_ACTIVE_SPK 0x04
|
||||
|
||||
#define OXYGEN_MCU_2WIRE_DATA 0xb0
|
||||
|
||||
#define OXYGEN_MCU_2WIRE_MAP 0xb2
|
||||
|
||||
#define OXYGEN_MCU_2WIRE_STATUS 0xb3
|
||||
#define OXYGEN_MCU_2WIRE_BUSY 0x01
|
||||
#define OXYGEN_MCU_2WIRE_LENGTH_MASK 0x06
|
||||
#define OXYGEN_MCU_2WIRE_LENGTH_1 0x00
|
||||
#define OXYGEN_MCU_2WIRE_LENGTH_2 0x02
|
||||
#define OXYGEN_MCU_2WIRE_LENGTH_3 0x04
|
||||
#define OXYGEN_MCU_2WIRE_WRITE 0x08 /* r/wc */
|
||||
#define OXYGEN_MCU_2WIRE_READ 0x10 /* r/wc */
|
||||
#define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL 0x20 /* r/wc */
|
||||
#define OXYGEN_MCU_2WIRE_RESET 0x40
|
||||
|
||||
#define OXYGEN_MCU_2WIRE_CONTROL 0xb4
|
||||
#define OXYGEN_MCU_2WIRE_DRV_ACK 0x01
|
||||
#define OXYGEN_MCU_2WIRE_DRV_XACT 0x02
|
||||
#define OXYGEN_MCU_2WIRE_INT_MASK 0x04
|
||||
#define OXYGEN_MCU_2WIRE_SYNC_MASK 0x08
|
||||
#define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN 0x00
|
||||
#define OXYGEN_MCU_2WIRE_SYNC_DATA 0x08
|
||||
#define OXYGEN_MCU_2WIRE_ADDRESS_MASK 0x30
|
||||
#define OXYGEN_MCU_2WIRE_ADDRESS_10 0x00
|
||||
#define OXYGEN_MCU_2WIRE_ADDRESS_12 0x10
|
||||
#define OXYGEN_MCU_2WIRE_ADDRESS_14 0x20
|
||||
#define OXYGEN_MCU_2WIRE_ADDRESS_16 0x30
|
||||
#define OXYGEN_MCU_2WIRE_INT_POL 0x40
|
||||
#define OXYGEN_MCU_2WIRE_SYNC_ENABLE 0x80
|
||||
|
||||
#define OXYGEN_PLAY_ROUTING 0xc0
|
||||
#define OXYGEN_PLAY_MUTE01 0x0001
|
||||
#define OXYGEN_PLAY_MUTE23 0x0002
|
||||
#define OXYGEN_PLAY_MUTE45 0x0004
|
||||
#define OXYGEN_PLAY_MUTE67 0x0008
|
||||
#define OXYGEN_PLAY_MULTICH_MASK 0x0010
|
||||
#define OXYGEN_PLAY_MULTICH_I2S_DAC 0x0000
|
||||
#define OXYGEN_PLAY_MULTICH_AC97 0x0010
|
||||
#define OXYGEN_PLAY_SPDIF_MASK 0x00e0
|
||||
#define OXYGEN_PLAY_SPDIF_SPDIF 0x0000
|
||||
#define OXYGEN_PLAY_SPDIF_MULTICH_01 0x0020
|
||||
#define OXYGEN_PLAY_SPDIF_MULTICH_23 0x0040
|
||||
#define OXYGEN_PLAY_SPDIF_MULTICH_45 0x0060
|
||||
#define OXYGEN_PLAY_SPDIF_MULTICH_67 0x0080
|
||||
#define OXYGEN_PLAY_SPDIF_REC_A 0x00a0
|
||||
#define OXYGEN_PLAY_SPDIF_REC_B 0x00c0
|
||||
#define OXYGEN_PLAY_SPDIF_I2S_ADC_3 0x00e0
|
||||
#define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300
|
||||
#define OXYGEN_PLAY_DAC0_SOURCE_SHIFT 8
|
||||
#define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0700
|
||||
#define OXYGEN_PLAY_DAC1_SOURCE_SHIFT 10
|
||||
#define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000
|
||||
#define OXYGEN_PLAY_DAC2_SOURCE_SHIFT 12
|
||||
#define OXYGEN_PLAY_DAC3_SOURCE_MASK 0x7000
|
||||
#define OXYGEN_PLAY_DAC3_SOURCE_SHIFT 14
|
||||
|
||||
#define OXYGEN_REC_ROUTING 0xc2
|
||||
#define OXYGEN_MUTE_I2S_ADC_1 0x01
|
||||
#define OXYGEN_MUTE_I2S_ADC_2 0x02
|
||||
#define OXYGEN_MUTE_I2S_ADC_3 0x04
|
||||
#define OXYGEN_REC_A_ROUTE_MASK 0x08
|
||||
#define OXYGEN_REC_A_ROUTE_I2S_ADC_1 0x00
|
||||
#define OXYGEN_REC_A_ROUTE_AC97_0 0x08
|
||||
#define OXYGEN_REC_B_ROUTE_MASK 0x10
|
||||
#define OXYGEN_REC_B_ROUTE_I2S_ADC_2 0x00
|
||||
#define OXYGEN_REC_B_ROUTE_AC97_1 0x10
|
||||
#define OXYGEN_REC_C_ROUTE_MASK 0x20
|
||||
#define OXYGEN_REC_C_ROUTE_SPDIF 0x00
|
||||
#define OXYGEN_REC_C_ROUTE_I2S_ADC_3 0x20
|
||||
|
||||
#define OXYGEN_ADC_MONITOR 0xc3
|
||||
#define OXYGEN_ADC_MONITOR_MULTICH 0x01
|
||||
#define OXYGEN_ADC_MONITOR_AC97 0x04
|
||||
#define OXYGEN_ADC_MONITOR_SPDIF 0x10
|
||||
#define OXYGEN_ADC_MONITOR_A 0x01
|
||||
#define OXYGEN_ADC_MONITOR_A_HALF_VOL 0x02
|
||||
#define OXYGEN_ADC_MONITOR_B 0x04
|
||||
#define OXYGEN_ADC_MONITOR_B_HALF_VOL 0x08
|
||||
#define OXYGEN_ADC_MONITOR_C 0x10
|
||||
#define OXYGEN_ADC_MONITOR_C_HALF_VOL 0x20
|
||||
|
||||
#define OXYGEN_A_MONITOR_ROUTING 0xc4
|
||||
#define OXYGEN_A_MONITOR_ROUTE_01_MASK 0x03
|
||||
#define OXYGEN_A_MONITOR_ROUTE_23_MASK 0x0c
|
||||
#define OXYGEN_A_MONITOR_ROUTE_45_MASK 0x30
|
||||
#define OXYGEN_A_MONITOR_ROUTE_67_MASK 0xc0
|
||||
|
||||
#define OXYGEN_AC97_CONTROL 0xd0
|
||||
#define OXYGEN_AC97_RESET1 0x0001
|
||||
#define OXYGEN_AC97_RESET1_BUSY 0x0002
|
||||
#define OXYGEN_AC97_RESET2 0x0008
|
||||
#define OXYGEN_AC97_COLD_RESET 0x0001
|
||||
#define OXYGEN_AC97_SUSPENDED 0x0002 /* read */
|
||||
#define OXYGEN_AC97_RESUME 0x0002 /* write */
|
||||
#define OXYGEN_AC97_CLOCK_DISABLE 0x0004
|
||||
#define OXYGEN_AC97_NO_CODEC_0 0x0008
|
||||
#define OXYGEN_AC97_CODEC_0 0x0010
|
||||
#define OXYGEN_AC97_CODEC_1 0x0020
|
||||
|
||||
#define OXYGEN_AC97_INTERRUPT_MASK 0xd2
|
||||
#define OXYGEN_AC97_INT_READ_DONE 0x01
|
||||
#define OXYGEN_AC97_INT_WRITE_DONE 0x02
|
||||
#define OXYGEN_AC97_INT_CODEC_0 0x10
|
||||
#define OXYGEN_AC97_INT_CODEC_1 0x20
|
||||
|
||||
#define OXYGEN_AC97_INTERRUPT_STATUS 0xd3
|
||||
#define OXYGEN_AC97_READ_COMPLETE 0x01
|
||||
#define OXYGEN_AC97_WRITE_COMPLETE 0x02
|
||||
/* OXYGEN_AC97_INT_* */
|
||||
|
||||
#define OXYGEN_AC97_OUT_CONFIG 0xd4
|
||||
#define OXYGEN_AC97_OUT_MAGIC1 0x00000011
|
||||
#define OXYGEN_AC97_OUT_MAGIC2 0x00000033
|
||||
#define OXYGEN_AC97_OUT_MAGIC3 0x0000ff00
|
||||
#define OXYGEN_AC97_CODEC1_SLOT3 0x00000001
|
||||
#define OXYGEN_AC97_CODEC1_SLOT3_VSR 0x00000002
|
||||
#define OXYGEN_AC97_CODEC1_SLOT4 0x00000010
|
||||
#define OXYGEN_AC97_CODEC1_SLOT4_VSR 0x00000020
|
||||
#define OXYGEN_AC97_CODEC0_FRONTL 0x00000100
|
||||
#define OXYGEN_AC97_CODEC0_FRONTR 0x00000200
|
||||
#define OXYGEN_AC97_CODEC0_SIDEL 0x00000400
|
||||
#define OXYGEN_AC97_CODEC0_SIDER 0x00000800
|
||||
#define OXYGEN_AC97_CODEC0_CENTER 0x00001000
|
||||
#define OXYGEN_AC97_CODEC0_BASE 0x00002000
|
||||
#define OXYGEN_AC97_CODEC0_REARL 0x00004000
|
||||
#define OXYGEN_AC97_CODEC0_REARR 0x00008000
|
||||
|
||||
#define OXYGEN_AC97_IN_CONFIG 0xd8
|
||||
#define OXYGEN_AC97_IN_MAGIC1 0x00000011
|
||||
#define OXYGEN_AC97_IN_MAGIC2 0x00000033
|
||||
#define OXYGEN_AC97_IN_MAGIC3 0x00000300
|
||||
#define OXYGEN_AC97_CODEC1_LINEL 0x00000001
|
||||
#define OXYGEN_AC97_CODEC1_LINEL_VSR 0x00000002
|
||||
#define OXYGEN_AC97_CODEC1_LINEL_16 0x00000000
|
||||
#define OXYGEN_AC97_CODEC1_LINEL_18 0x00000004
|
||||
#define OXYGEN_AC97_CODEC1_LINEL_20 0x00000008
|
||||
#define OXYGEN_AC97_CODEC1_LINER 0x00000010
|
||||
#define OXYGEN_AC97_CODEC1_LINER_VSR 0x00000020
|
||||
#define OXYGEN_AC97_CODEC1_LINER_16 0x00000000
|
||||
#define OXYGEN_AC97_CODEC1_LINER_18 0x00000040
|
||||
#define OXYGEN_AC97_CODEC1_LINER_20 0x00000080
|
||||
#define OXYGEN_AC97_CODEC0_LINEL 0x00000100
|
||||
#define OXYGEN_AC97_CODEC0_LINER 0x00000200
|
||||
|
||||
#define OXYGEN_AC97_REGS 0xdc
|
||||
#define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff
|
||||
@ -236,13 +421,29 @@
|
||||
#define OXYGEN_AC97_REG_CODEC_MASK 0x01000000
|
||||
#define OXYGEN_AC97_REG_CODEC_SHIFT 24
|
||||
|
||||
#define OXYGEN_TEST 0xe0
|
||||
#define OXYGEN_TEST_RAM_SUCCEEDED 0x01
|
||||
#define OXYGEN_TEST_PLAYBACK_RAM 0x02
|
||||
#define OXYGEN_TEST_RECORD_RAM 0x04
|
||||
#define OXYGEN_TEST_PLL 0x08
|
||||
#define OXYGEN_TEST_2WIRE_LOOPBACK 0x10
|
||||
|
||||
#define OXYGEN_DMA_FLUSH 0xe1
|
||||
/* OXYGEN_CHANNEL_* */
|
||||
|
||||
#define OXYGEN_CODEC_VERSION 0xe4
|
||||
#define OXYGEN_XCID_MASK 0x07
|
||||
|
||||
#define OXYGEN_REVISION 0xe6
|
||||
#define OXYGEN_REVISION_2 0x08 /* bit flag */
|
||||
#define OXYGEN_REVISION_8787 0x14 /* all 8 bits */
|
||||
#define OXYGEN_REVISION_XPKGID_MASK 0x0007
|
||||
#define OXYGEN_REVISION_MASK 0xfff8
|
||||
#define OXYGEN_REVISION_2 0x0008 /* bit flag */
|
||||
#define OXYGEN_REVISION_8787 0x0014 /* 8 bits */
|
||||
|
||||
#define OXYGEN_OFFSIN_48K 0xe8
|
||||
#define OXYGEN_OFFSBASE_48K 0xe9
|
||||
#define OXYGEN_OFFSBASE_MASK 0x0fff
|
||||
#define OXYGEN_OFFSIN_44K 0xec
|
||||
#define OXYGEN_OFFSBASE_44K 0xed
|
||||
|
||||
#endif
|
||||
|
||||
@ -80,10 +80,11 @@ static void pcm1796_write(struct oxygen *chip, unsigned int codec,
|
||||
static const u8 codec_map[4] = {
|
||||
0, 1, 2, 4
|
||||
};
|
||||
oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER_WRITE |
|
||||
oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
|
||||
OXYGEN_SPI_DATA_LENGTH_2 |
|
||||
OXYGEN_SPI_CLOCK_160 |
|
||||
(codec_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
|
||||
OXYGEN_SPI_MAGIC,
|
||||
OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
|
||||
(reg << 8) | value);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user