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soundwire updates for v5.6-rc1
This round we have bunch of updates to interfaces for ASoC (audio) subsystem by Intel and a new Qualcomm controller driver Details - Updates for sdw_slave interfaces for ASoC - Updates to cadence library and intel driver - New Soundwire controller for Qualcomm masters - Rework of device number assignment -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+vs47OPLdNbVcHzyfBQHDyUjg0cFAl4iq9AACgkQfBQHDyUj g0e5Zg/8DS1KK/zzBPP5QTcNRzJvGngGBxsXkH6fEInfc9bD6XK+DgQ5c3N0NP4A njw4sBBKd6V1XSxaUKbOWXTLFGvxDl4tHghlwD1hUwMcb+jmAsaHhfpKCUGrzQD8 0rtGmSrwRyRj8QZeSU6s6bf8zynXpSEaJs5+yE/t8A8fzQobINVR5n2sfhLKRUYk +2n+3XRy1oipYWFaEWT/2JHui2iDv9QcH5Ssvlj01DImKXXGFD6Zb3JzJSfanv6t YKpEor8hTV5C2/Y8GYEMZWSJHwuvCTq4G3NJ4x3FxSj10D5gi8ZzHg2jnMTwvNjw teFsu9NP0Et1diDl1WGtAxx1HhMHY3Zoihu+fJ35c6kmYRWdm+ymTtSL2CQg2p6/ /IcWWHkeNC6ziOsABUn33HH4hPmjNmXeKqtRdJNCOaXtQgG2ncMQIx+xWClmSNP8 N4/tLcGjLLAIJFGT7aYsc2ysMVBH6bWgz4lmZLMUDxBEynSxairtExDx8oYowkBj 2nDhUe39ROdrgJtFU9IdDtqSSRliSQ9rLy5g6r4SwfFb+A3I4XJn4kDJ6YqHlw7H Mv5js0a+C7QfYIAWvmn3WHuzqUpHloN44/lRUmcr5gT2DyJX+sNPZK/DsCsspTkQ k16tMUZU29A27tYxl07M6OKxQaS/Q49zZJuS0BkcZOYt+A5NPZk= =PDic -----END PGP SIGNATURE----- Merge tag 'soundwire-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next Vinod writes: soundwire updates for v5.6-rc1 This round we have bunch of updates to interfaces for ASoC (audio) subsystem by Intel and a new Qualcomm controller driver Details - Updates for sdw_slave interfaces for ASoC - Updates to cadence library and intel driver - New Soundwire controller for Qualcomm masters - Rework of device number assignment * tag 'soundwire-5.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (27 commits) dt-bindings: soundwire: fix example soundwire: cadence: fix kernel-doc parameter descriptions soundwire: intel: report slave_ids for each link to SOF driver soundwire: intel: fix factor of two in MCLK handling soundwire: bus: fix device number leak on errors soundwire: cadence: remove useless variable incrementation soundwire: cadence: update kernel-doc parameter descriptions soundwire: qcom: add support for SoundWire controller dt-bindings: soundwire: add bindings for Qcom controller soundwire: bus: check first if Slaves become UNATTACHED soundwire: cadence_master: handle multiple status reports per Slave soundwire: cadence_master: remove config update for interrupt setting soundwire: cadence_master: log more useful information during timeouts soundwire: cadence_master: clear interrupt status before enabling interrupt soundwire: cadence_master: filter out bad interrupts soundwire: stream: remove redundant pr_err traces soundwire: intel: add clock stop quirks soundwire: intel: add mutex for shared SHIM register access soundwire: intel: add prototype for WAKEEN interrupt processing soundwire: intel: add link_list to handle interrupts with a single thread ...
This commit is contained in:
commit
c20c76acf6
167
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
Normal file
167
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
Normal file
@ -0,0 +1,167 @@
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Qualcomm SoundWire Controller Bindings
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This binding describes the Qualcomm SoundWire Controller along with its
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board specific bus parameters.
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- compatible:
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Usage: required
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Value type: <stringlist>
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Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
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Example:
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"qcom,soundwire-v1.3.0"
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"qcom,soundwire-v1.5.0"
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"qcom,soundwire-v1.6.0"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of SoundWire controller
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address space.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the SoundWire Controller IRQ
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: should be "iface" for SoundWire Controller interface clock
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the SoundWire Controller interface clock
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- #sound-dai-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 1 for digital audio interfaces on the controller.
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- qcom,dout-ports:
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Usage: required
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Value type: <u32>
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Definition: must be count of data out ports
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- qcom,din-ports:
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Usage: required
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Value type: <u32>
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Definition: must be count of data in ports
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- qcom,ports-offset1:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify payload transport window offset1 of each
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data port. Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-offset2:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify payload transport window offset2 of each
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data port. Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-sinterval-low:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should be sample interval low of each data port.
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Out ports followed by In ports. Used for Sample Interval
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calculation.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-word-length:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be size of payload channel sample.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-block-pack-mode:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be 0 or 1 to indicate the block packing mode.
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0 to indicate Blocks are per Channel
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1 to indicate Blocks are per Port.
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-block-group-count:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be in range 1 to 4 to indicate how many sample
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intervals are combined into a payload.
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-lane-control:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be in range 0 to 7 to identify which data lane
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the data port uses.
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-hstart:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be number identifying lowerst numbered coloum in
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SoundWire Frame, i.e. left edge of the Transport sub-frame
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for each port. Values between 0 and 15 are valid.
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,ports-hstop:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be number identifying highest numbered coloum in
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SoundWire Frame, i.e. the right edge of the Transport
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sub-frame for each port. Values between 0 and 15 are valid.
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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- qcom,dports-type:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: should be one of the following types
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0 for reduced port
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1 for simple ports
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2 for full port
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Out ports followed by In ports.
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More info in MIPI Alliance SoundWire 1.0 Specifications.
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Note:
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More Information on detail of encoding of these fields can be
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found in MIPI Alliance SoundWire 1.0 Specifications.
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= SoundWire devices
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Each subnode of the bus represents SoundWire device attached to it.
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The properties of these nodes are defined by the individual bindings.
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= EXAMPLE
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The following example represents a SoundWire controller on DB845c board
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which has controller integrated inside WCD934x codec on SDM845 SoC.
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soundwire: soundwire@c85 {
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compatible = "qcom,soundwire-v1.3.0";
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reg = <0xc85 0x20>;
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interrupts = <20 IRQ_TYPE_EDGE_RISING>;
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clocks = <&wcc>;
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clock-names = "iface";
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#sound-dai-cells = <1>;
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qcom,dports-type = <0>;
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qcom,dout-ports = <6>;
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qcom,din-ports = <2>;
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qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
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qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
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/* Left Speaker */
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left{
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....
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};
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/* Right Speaker */
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right{
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....
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};
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};
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@ -69,6 +69,7 @@ examples:
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reg = <0 1>;
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reg = <0 1>;
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powerdown-gpios = <&wcdpinctrl 2 0>;
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powerdown-gpios = <&wcdpinctrl 2 0>;
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#thermal-sensor-cells = <0>;
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#thermal-sensor-cells = <0>;
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#sound-dai-cells = <0>;
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};
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};
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speaker@0,2 {
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speaker@0,2 {
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@ -76,6 +77,7 @@ examples:
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reg = <0 2>;
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reg = <0 2>;
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powerdown-gpios = <&wcdpinctrl 2 0>;
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powerdown-gpios = <&wcdpinctrl 2 0>;
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#thermal-sensor-cells = <0>;
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#thermal-sensor-cells = <0>;
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#sound-dai-cells = <0>;
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};
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};
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};
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};
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@ -31,4 +31,13 @@ config SOUNDWIRE_INTEL
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enable this config option to get the SoundWire support for that
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enable this config option to get the SoundWire support for that
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device.
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device.
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config SOUNDWIRE_QCOM
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tristate "Qualcomm SoundWire Master driver"
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depends on SLIMBUS
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depends on SND_SOC
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help
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SoundWire Qualcomm Master driver.
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If you have an Qualcomm platform which has a SoundWire Master then
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enable this config option to get the SoundWire support for that
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device
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endif
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endif
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@ -21,3 +21,7 @@ obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel.o
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soundwire-intel-init-objs := intel_init.o
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soundwire-intel-init-objs := intel_init.o
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obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel-init.o
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obj-$(CONFIG_SOUNDWIRE_INTEL) += soundwire-intel-init.o
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#Qualcomm driver
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soundwire-qcom-objs := qcom.o
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obj-$(CONFIG_SOUNDWIRE_QCOM) += soundwire-qcom.o
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@ -456,26 +456,35 @@ static int sdw_get_device_num(struct sdw_slave *slave)
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static int sdw_assign_device_num(struct sdw_slave *slave)
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static int sdw_assign_device_num(struct sdw_slave *slave)
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{
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{
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int ret, dev_num;
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int ret, dev_num;
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bool new_device = false;
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/* check first if device number is assigned, if so reuse that */
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/* check first if device number is assigned, if so reuse that */
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if (!slave->dev_num) {
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if (!slave->dev_num) {
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mutex_lock(&slave->bus->bus_lock);
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if (!slave->dev_num_sticky) {
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dev_num = sdw_get_device_num(slave);
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mutex_lock(&slave->bus->bus_lock);
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mutex_unlock(&slave->bus->bus_lock);
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dev_num = sdw_get_device_num(slave);
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if (dev_num < 0) {
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mutex_unlock(&slave->bus->bus_lock);
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dev_err(slave->bus->dev, "Get dev_num failed: %d\n",
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if (dev_num < 0) {
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dev_num);
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dev_err(slave->bus->dev, "Get dev_num failed: %d\n",
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return dev_num;
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dev_num);
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return dev_num;
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}
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slave->dev_num = dev_num;
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slave->dev_num_sticky = dev_num;
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new_device = true;
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} else {
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slave->dev_num = slave->dev_num_sticky;
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}
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}
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} else {
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}
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if (!new_device)
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dev_info(slave->bus->dev,
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dev_info(slave->bus->dev,
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"Slave already registered dev_num:%d\n",
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"Slave already registered, reusing dev_num:%d\n",
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slave->dev_num);
|
slave->dev_num);
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/* Clear the slave->dev_num to transfer message on device 0 */
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/* Clear the slave->dev_num to transfer message on device 0 */
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dev_num = slave->dev_num;
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dev_num = slave->dev_num;
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slave->dev_num = 0;
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slave->dev_num = 0;
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}
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ret = sdw_write(slave, SDW_SCP_DEVNUMBER, dev_num);
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ret = sdw_write(slave, SDW_SCP_DEVNUMBER, dev_num);
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if (ret < 0) {
|
if (ret < 0) {
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@ -485,7 +494,7 @@ static int sdw_assign_device_num(struct sdw_slave *slave)
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}
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}
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/* After xfer of msg, restore dev_num */
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/* After xfer of msg, restore dev_num */
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slave->dev_num = dev_num;
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slave->dev_num = slave->dev_num_sticky;
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return 0;
|
return 0;
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}
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}
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@ -979,6 +988,24 @@ int sdw_handle_slave_status(struct sdw_bus *bus,
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struct sdw_slave *slave;
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struct sdw_slave *slave;
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int i, ret = 0;
|
int i, ret = 0;
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|
|
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/* first check if any Slaves fell off the bus */
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for (i = 1; i <= SDW_MAX_DEVICES; i++) {
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mutex_lock(&bus->bus_lock);
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|
if (test_bit(i, bus->assigned) == false) {
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|
mutex_unlock(&bus->bus_lock);
|
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|
continue;
|
||||||
|
}
|
||||||
|
mutex_unlock(&bus->bus_lock);
|
||||||
|
|
||||||
|
slave = sdw_get_slave(bus, i);
|
||||||
|
if (!slave)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
if (status[i] == SDW_SLAVE_UNATTACHED &&
|
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|
slave->status != SDW_SLAVE_UNATTACHED)
|
||||||
|
sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
|
||||||
|
}
|
||||||
|
|
||||||
if (status[0] == SDW_SLAVE_ATTACHED) {
|
if (status[0] == SDW_SLAVE_ATTACHED) {
|
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dev_dbg(bus->dev, "Slave attached, programming device number\n");
|
dev_dbg(bus->dev, "Slave attached, programming device number\n");
|
||||||
ret = sdw_program_device_num(bus);
|
ret = sdw_program_device_num(bus);
|
||||||
|
@ -74,6 +74,7 @@ MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
|
|||||||
#define CDNS_MCP_INTMASK 0x48
|
#define CDNS_MCP_INTMASK 0x48
|
||||||
|
|
||||||
#define CDNS_MCP_INT_IRQ BIT(31)
|
#define CDNS_MCP_INT_IRQ BIT(31)
|
||||||
|
#define CDNS_MCP_INT_RESERVED1 GENMASK(30, 17)
|
||||||
#define CDNS_MCP_INT_WAKEUP BIT(16)
|
#define CDNS_MCP_INT_WAKEUP BIT(16)
|
||||||
#define CDNS_MCP_INT_SLAVE_RSVD BIT(15)
|
#define CDNS_MCP_INT_SLAVE_RSVD BIT(15)
|
||||||
#define CDNS_MCP_INT_SLAVE_ALERT BIT(14)
|
#define CDNS_MCP_INT_SLAVE_ALERT BIT(14)
|
||||||
@ -85,10 +86,12 @@ MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
|
|||||||
#define CDNS_MCP_INT_DATA_CLASH BIT(9)
|
#define CDNS_MCP_INT_DATA_CLASH BIT(9)
|
||||||
#define CDNS_MCP_INT_PARITY BIT(8)
|
#define CDNS_MCP_INT_PARITY BIT(8)
|
||||||
#define CDNS_MCP_INT_CMD_ERR BIT(7)
|
#define CDNS_MCP_INT_CMD_ERR BIT(7)
|
||||||
|
#define CDNS_MCP_INT_RESERVED2 GENMASK(6, 4)
|
||||||
#define CDNS_MCP_INT_RX_NE BIT(3)
|
#define CDNS_MCP_INT_RX_NE BIT(3)
|
||||||
#define CDNS_MCP_INT_RX_WL BIT(2)
|
#define CDNS_MCP_INT_RX_WL BIT(2)
|
||||||
#define CDNS_MCP_INT_TXE BIT(1)
|
#define CDNS_MCP_INT_TXE BIT(1)
|
||||||
#define CDNS_MCP_INT_TXF BIT(0)
|
#define CDNS_MCP_INT_TXF BIT(0)
|
||||||
|
#define CDNS_MCP_INT_RESERVED (CDNS_MCP_INT_RESERVED1 | CDNS_MCP_INT_RESERVED2)
|
||||||
|
|
||||||
#define CDNS_MCP_INTSET 0x4C
|
#define CDNS_MCP_INTSET 0x4C
|
||||||
|
|
||||||
@ -444,7 +447,8 @@ _cdns_xfer_msg(struct sdw_cdns *cdns, struct sdw_msg *msg, int cmd,
|
|||||||
time = wait_for_completion_timeout(&cdns->tx_complete,
|
time = wait_for_completion_timeout(&cdns->tx_complete,
|
||||||
msecs_to_jiffies(CDNS_TX_TIMEOUT));
|
msecs_to_jiffies(CDNS_TX_TIMEOUT));
|
||||||
if (!time) {
|
if (!time) {
|
||||||
dev_err(cdns->dev, "IO transfer timed out\n");
|
dev_err(cdns->dev, "IO transfer timed out, cmd %d device %d addr %x len %d\n",
|
||||||
|
cmd, msg->dev_num, msg->addr, msg->len);
|
||||||
msg->len = 0;
|
msg->len = 0;
|
||||||
return SDW_CMD_TIMEOUT;
|
return SDW_CMD_TIMEOUT;
|
||||||
}
|
}
|
||||||
@ -672,13 +676,36 @@ static int cdns_update_slave_status(struct sdw_cdns *cdns,
|
|||||||
|
|
||||||
/* first check if Slave reported multiple status */
|
/* first check if Slave reported multiple status */
|
||||||
if (set_status > 1) {
|
if (set_status > 1) {
|
||||||
|
u32 val;
|
||||||
|
|
||||||
dev_warn_ratelimited(cdns->dev,
|
dev_warn_ratelimited(cdns->dev,
|
||||||
"Slave reported multiple Status: %d\n",
|
"Slave %d reported multiple Status: %d\n",
|
||||||
mask);
|
i, mask);
|
||||||
/*
|
|
||||||
* TODO: we need to reread the status here by
|
/* check latest status extracted from PING commands */
|
||||||
* issuing a PING cmd
|
val = cdns_readl(cdns, CDNS_MCP_SLAVE_STAT);
|
||||||
*/
|
val >>= (i * 2);
|
||||||
|
|
||||||
|
switch (val & 0x3) {
|
||||||
|
case 0:
|
||||||
|
status[i] = SDW_SLAVE_UNATTACHED;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
status[i] = SDW_SLAVE_ATTACHED;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
status[i] = SDW_SLAVE_ALERT;
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
default:
|
||||||
|
status[i] = SDW_SLAVE_RESERVED;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
dev_warn_ratelimited(cdns->dev,
|
||||||
|
"Slave %d status updated to %d\n",
|
||||||
|
i, status[i]);
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -705,6 +732,10 @@ irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
|
|||||||
|
|
||||||
int_status = cdns_readl(cdns, CDNS_MCP_INTSTAT);
|
int_status = cdns_readl(cdns, CDNS_MCP_INTSTAT);
|
||||||
|
|
||||||
|
/* check for reserved values read as zero */
|
||||||
|
if (int_status & CDNS_MCP_INT_RESERVED)
|
||||||
|
return IRQ_NONE;
|
||||||
|
|
||||||
if (!(int_status & CDNS_MCP_INT_IRQ))
|
if (!(int_status & CDNS_MCP_INT_IRQ))
|
||||||
return IRQ_NONE;
|
return IRQ_NONE;
|
||||||
|
|
||||||
@ -812,8 +843,9 @@ int sdw_cdns_exit_reset(struct sdw_cdns *cdns)
|
|||||||
EXPORT_SYMBOL(sdw_cdns_exit_reset);
|
EXPORT_SYMBOL(sdw_cdns_exit_reset);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* sdw_cdns_enable_interrupt() - Enable SDW interrupts and update config
|
* sdw_cdns_enable_interrupt() - Enable SDW interrupts
|
||||||
* @cdns: Cadence instance
|
* @cdns: Cadence instance
|
||||||
|
* @state: True if we are trying to enable interrupt.
|
||||||
*/
|
*/
|
||||||
int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state)
|
int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state)
|
||||||
{
|
{
|
||||||
@ -849,12 +881,21 @@ int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns, bool state)
|
|||||||
mask = interrupt_mask;
|
mask = interrupt_mask;
|
||||||
|
|
||||||
update_masks:
|
update_masks:
|
||||||
|
/* clear slave interrupt status before enabling interrupt */
|
||||||
|
if (state) {
|
||||||
|
u32 slave_state;
|
||||||
|
|
||||||
|
slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT0);
|
||||||
|
cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT0, slave_state);
|
||||||
|
slave_state = cdns_readl(cdns, CDNS_MCP_SLAVE_INTSTAT1);
|
||||||
|
cdns_writel(cdns, CDNS_MCP_SLAVE_INTSTAT1, slave_state);
|
||||||
|
}
|
||||||
|
|
||||||
cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK0, slave_intmask0);
|
cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK0, slave_intmask0);
|
||||||
cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK1, slave_intmask1);
|
cdns_writel(cdns, CDNS_MCP_SLAVE_INTMASK1, slave_intmask1);
|
||||||
cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
|
cdns_writel(cdns, CDNS_MCP_INTMASK, mask);
|
||||||
|
|
||||||
/* commit changes */
|
return 0;
|
||||||
return cdns_update_config(cdns);
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(sdw_cdns_enable_interrupt);
|
EXPORT_SYMBOL(sdw_cdns_enable_interrupt);
|
||||||
|
|
||||||
@ -948,8 +989,6 @@ int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
|
|||||||
ret = cdns_allocate_pdi(cdns, &stream->out,
|
ret = cdns_allocate_pdi(cdns, &stream->out,
|
||||||
stream->num_out, offset);
|
stream->num_out, offset);
|
||||||
|
|
||||||
offset += stream->num_out;
|
|
||||||
|
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
|
|
||||||
@ -1224,8 +1263,10 @@ EXPORT_SYMBOL(cdns_set_sdw_stream);
|
|||||||
* cdns_find_pdi() - Find a free PDI
|
* cdns_find_pdi() - Find a free PDI
|
||||||
*
|
*
|
||||||
* @cdns: Cadence instance
|
* @cdns: Cadence instance
|
||||||
|
* @offset: Starting offset
|
||||||
* @num: Number of PDIs
|
* @num: Number of PDIs
|
||||||
* @pdi: PDI instances
|
* @pdi: PDI instances
|
||||||
|
* @dai_id: DAI id
|
||||||
*
|
*
|
||||||
* Find a PDI for a given PDI array. The PDI num and dai_id are
|
* Find a PDI for a given PDI array. The PDI num and dai_id are
|
||||||
* expected to match, return NULL otherwise.
|
* expected to match, return NULL otherwise.
|
||||||
@ -1277,6 +1318,7 @@ EXPORT_SYMBOL(sdw_cdns_config_stream);
|
|||||||
* @stream: Stream to be allocated
|
* @stream: Stream to be allocated
|
||||||
* @ch: Channel count
|
* @ch: Channel count
|
||||||
* @dir: Data direction
|
* @dir: Data direction
|
||||||
|
* @dai_id: DAI id
|
||||||
*/
|
*/
|
||||||
struct sdw_cdns_pdi *sdw_cdns_alloc_pdi(struct sdw_cdns *cdns,
|
struct sdw_cdns_pdi *sdw_cdns_alloc_pdi(struct sdw_cdns *cdns,
|
||||||
struct sdw_cdns_streams *stream,
|
struct sdw_cdns_streams *stream,
|
||||||
|
@ -529,17 +529,24 @@ intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
|
|||||||
intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
|
intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int intel_config_stream(struct sdw_intel *sdw,
|
static int intel_params_stream(struct sdw_intel *sdw,
|
||||||
struct snd_pcm_substream *substream,
|
struct snd_pcm_substream *substream,
|
||||||
struct snd_soc_dai *dai,
|
struct snd_soc_dai *dai,
|
||||||
struct snd_pcm_hw_params *hw_params, int link_id)
|
struct snd_pcm_hw_params *hw_params,
|
||||||
|
int link_id, int alh_stream_id)
|
||||||
{
|
{
|
||||||
struct sdw_intel_link_res *res = sdw->res;
|
struct sdw_intel_link_res *res = sdw->res;
|
||||||
|
struct sdw_intel_stream_params_data params_data;
|
||||||
|
|
||||||
if (res->ops && res->ops->config_stream && res->arg)
|
params_data.substream = substream;
|
||||||
return res->ops->config_stream(res->arg,
|
params_data.dai = dai;
|
||||||
substream, dai, hw_params, link_id);
|
params_data.hw_params = hw_params;
|
||||||
|
params_data.link_id = link_id;
|
||||||
|
params_data.alh_stream_id = alh_stream_id;
|
||||||
|
|
||||||
|
if (res->ops && res->ops->params_stream && res->dev)
|
||||||
|
return res->ops->params_stream(res->dev,
|
||||||
|
¶ms_data);
|
||||||
return -EIO;
|
return -EIO;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -654,7 +661,8 @@ static int intel_hw_params(struct snd_pcm_substream *substream,
|
|||||||
|
|
||||||
|
|
||||||
/* Inform DSP about PDI stream number */
|
/* Inform DSP about PDI stream number */
|
||||||
ret = intel_config_stream(sdw, substream, dai, params,
|
ret = intel_params_stream(sdw, substream, dai, params,
|
||||||
|
sdw->instance,
|
||||||
pdi->intel_alh_id);
|
pdi->intel_alh_id);
|
||||||
if (ret)
|
if (ret)
|
||||||
goto error;
|
goto error;
|
||||||
@ -872,6 +880,9 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus)
|
|||||||
"intel-sdw-ip-clock",
|
"intel-sdw-ip-clock",
|
||||||
&prop->mclk_freq);
|
&prop->mclk_freq);
|
||||||
|
|
||||||
|
/* the values reported by BIOS are the 2x clock, not the bus clock */
|
||||||
|
prop->mclk_freq /= 2;
|
||||||
|
|
||||||
fwnode_property_read_u32(link,
|
fwnode_property_read_u32(link,
|
||||||
"intel-quirk-mask",
|
"intel-quirk-mask",
|
||||||
&quirk_mask);
|
&quirk_mask);
|
||||||
|
@ -5,23 +5,26 @@
|
|||||||
#define __SDW_INTEL_LOCAL_H
|
#define __SDW_INTEL_LOCAL_H
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct sdw_intel_link_res - Soundwire link resources
|
* struct sdw_intel_link_res - Soundwire Intel link resource structure,
|
||||||
|
* typically populated by the controller driver.
|
||||||
|
* @pdev: platform_device
|
||||||
|
* @mmio_base: mmio base of SoundWire registers
|
||||||
* @registers: Link IO registers base
|
* @registers: Link IO registers base
|
||||||
* @shim: Audio shim pointer
|
* @shim: Audio shim pointer
|
||||||
* @alh: ALH (Audio Link Hub) pointer
|
* @alh: ALH (Audio Link Hub) pointer
|
||||||
* @irq: Interrupt line
|
* @irq: Interrupt line
|
||||||
* @ops: Shim callback ops
|
* @ops: Shim callback ops
|
||||||
* @arg: Shim callback ops argument
|
* @dev: device implementing hw_params and free callbacks
|
||||||
*
|
|
||||||
* This is set as pdata for each link instance.
|
|
||||||
*/
|
*/
|
||||||
struct sdw_intel_link_res {
|
struct sdw_intel_link_res {
|
||||||
|
struct platform_device *pdev;
|
||||||
|
void __iomem *mmio_base; /* not strictly needed, useful for debug */
|
||||||
void __iomem *registers;
|
void __iomem *registers;
|
||||||
void __iomem *shim;
|
void __iomem *shim;
|
||||||
void __iomem *alh;
|
void __iomem *alh;
|
||||||
int irq;
|
int irq;
|
||||||
const struct sdw_intel_ops *ops;
|
const struct sdw_intel_ops *ops;
|
||||||
void *arg;
|
struct device *dev;
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif /* __SDW_INTEL_LOCAL_H */
|
#endif /* __SDW_INTEL_LOCAL_H */
|
||||||
|
@ -27,19 +27,9 @@ static int link_mask;
|
|||||||
module_param_named(sdw_link_mask, link_mask, int, 0444);
|
module_param_named(sdw_link_mask, link_mask, int, 0444);
|
||||||
MODULE_PARM_DESC(sdw_link_mask, "Intel link mask (one bit per link)");
|
MODULE_PARM_DESC(sdw_link_mask, "Intel link mask (one bit per link)");
|
||||||
|
|
||||||
struct sdw_link_data {
|
|
||||||
struct sdw_intel_link_res res;
|
|
||||||
struct platform_device *pdev;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct sdw_intel_ctx {
|
|
||||||
int count;
|
|
||||||
struct sdw_link_data *links;
|
|
||||||
};
|
|
||||||
|
|
||||||
static int sdw_intel_cleanup_pdev(struct sdw_intel_ctx *ctx)
|
static int sdw_intel_cleanup_pdev(struct sdw_intel_ctx *ctx)
|
||||||
{
|
{
|
||||||
struct sdw_link_data *link = ctx->links;
|
struct sdw_intel_link_res *link = ctx->links;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
if (!link)
|
if (!link)
|
||||||
@ -62,7 +52,7 @@ static struct sdw_intel_ctx
|
|||||||
{
|
{
|
||||||
struct platform_device_info pdevinfo;
|
struct platform_device_info pdevinfo;
|
||||||
struct platform_device *pdev;
|
struct platform_device *pdev;
|
||||||
struct sdw_link_data *link;
|
struct sdw_intel_link_res *link;
|
||||||
struct sdw_intel_ctx *ctx;
|
struct sdw_intel_ctx *ctx;
|
||||||
struct acpi_device *adev;
|
struct acpi_device *adev;
|
||||||
int ret, i;
|
int ret, i;
|
||||||
@ -123,14 +113,13 @@ static struct sdw_intel_ctx
|
|||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
link->res.irq = res->irq;
|
link->registers = res->mmio_base + SDW_LINK_BASE
|
||||||
link->res.registers = res->mmio_base + SDW_LINK_BASE
|
|
||||||
+ (SDW_LINK_SIZE * i);
|
+ (SDW_LINK_SIZE * i);
|
||||||
link->res.shim = res->mmio_base + SDW_SHIM_BASE;
|
link->shim = res->mmio_base + SDW_SHIM_BASE;
|
||||||
link->res.alh = res->mmio_base + SDW_ALH_BASE;
|
link->alh = res->mmio_base + SDW_ALH_BASE;
|
||||||
|
|
||||||
link->res.ops = res->ops;
|
link->ops = res->ops;
|
||||||
link->res.arg = res->arg;
|
link->dev = res->dev;
|
||||||
|
|
||||||
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
||||||
|
|
||||||
@ -138,8 +127,6 @@ static struct sdw_intel_ctx
|
|||||||
pdevinfo.name = "int-sdw";
|
pdevinfo.name = "int-sdw";
|
||||||
pdevinfo.id = i;
|
pdevinfo.id = i;
|
||||||
pdevinfo.fwnode = acpi_fwnode_handle(adev);
|
pdevinfo.fwnode = acpi_fwnode_handle(adev);
|
||||||
pdevinfo.data = &link->res;
|
|
||||||
pdevinfo.size_data = sizeof(link->res);
|
|
||||||
|
|
||||||
pdev = platform_device_register_full(&pdevinfo);
|
pdev = platform_device_register_full(&pdevinfo);
|
||||||
if (IS_ERR(pdev)) {
|
if (IS_ERR(pdev)) {
|
||||||
@ -216,7 +203,6 @@ void *sdw_intel_init(acpi_handle *parent_handle, struct sdw_intel_res *res)
|
|||||||
|
|
||||||
return sdw_intel_add_controller(res);
|
return sdw_intel_add_controller(res);
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(sdw_intel_init);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* sdw_intel_exit() - SoundWire Intel exit
|
* sdw_intel_exit() - SoundWire Intel exit
|
||||||
@ -224,10 +210,8 @@ EXPORT_SYMBOL(sdw_intel_init);
|
|||||||
*
|
*
|
||||||
* Delete the controller instances created and cleanup
|
* Delete the controller instances created and cleanup
|
||||||
*/
|
*/
|
||||||
void sdw_intel_exit(void *arg)
|
void sdw_intel_exit(struct sdw_intel_ctx *ctx)
|
||||||
{
|
{
|
||||||
struct sdw_intel_ctx *ctx = arg;
|
|
||||||
|
|
||||||
sdw_intel_cleanup_pdev(ctx);
|
sdw_intel_cleanup_pdev(ctx);
|
||||||
kfree(ctx);
|
kfree(ctx);
|
||||||
}
|
}
|
||||||
|
861
drivers/soundwire/qcom.c
Normal file
861
drivers/soundwire/qcom.c
Normal file
@ -0,0 +1,861 @@
|
|||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
// Copyright (c) 2019, Linaro Limited
|
||||||
|
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <linux/completion.h>
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/of.h>
|
||||||
|
#include <linux/of_irq.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
#include <linux/slimbus.h>
|
||||||
|
#include <linux/soundwire/sdw.h>
|
||||||
|
#include <linux/soundwire/sdw_registers.h>
|
||||||
|
#include <sound/pcm_params.h>
|
||||||
|
#include <sound/soc.h>
|
||||||
|
#include "bus.h"
|
||||||
|
|
||||||
|
#define SWRM_COMP_HW_VERSION 0x00
|
||||||
|
#define SWRM_COMP_CFG_ADDR 0x04
|
||||||
|
#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
|
||||||
|
#define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
|
||||||
|
#define SWRM_COMP_PARAMS 0x100
|
||||||
|
#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
|
||||||
|
#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
|
||||||
|
#define SWRM_INTERRUPT_STATUS 0x200
|
||||||
|
#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
|
||||||
|
#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
|
||||||
|
#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
|
||||||
|
#define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
|
||||||
|
#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
|
||||||
|
#define SWRM_INTERRUPT_MASK_ADDR 0x204
|
||||||
|
#define SWRM_INTERRUPT_CLEAR 0x208
|
||||||
|
#define SWRM_CMD_FIFO_WR_CMD 0x300
|
||||||
|
#define SWRM_CMD_FIFO_RD_CMD 0x304
|
||||||
|
#define SWRM_CMD_FIFO_CMD 0x308
|
||||||
|
#define SWRM_CMD_FIFO_STATUS 0x30C
|
||||||
|
#define SWRM_CMD_FIFO_CFG_ADDR 0x314
|
||||||
|
#define SWRM_RD_WR_CMD_RETRIES 0x7
|
||||||
|
#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
|
||||||
|
#define SWRM_ENUMERATOR_CFG_ADDR 0x500
|
||||||
|
#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
|
||||||
|
#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3
|
||||||
|
#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
|
||||||
|
#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
|
||||||
|
#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0
|
||||||
|
#define SWRM_MCP_CFG_ADDR 0x1048
|
||||||
|
#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
|
||||||
|
#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT 0x11
|
||||||
|
#define SWRM_DEF_CMD_NO_PINGS 0x1f
|
||||||
|
#define SWRM_MCP_STATUS 0x104C
|
||||||
|
#define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
|
||||||
|
#define SWRM_MCP_SLV_STATUS 0x1090
|
||||||
|
#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
|
||||||
|
#define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
|
||||||
|
#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
|
||||||
|
#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
|
||||||
|
#define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
|
||||||
|
#define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
|
||||||
|
#define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
|
||||||
|
#define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
|
||||||
|
#define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
|
||||||
|
|
||||||
|
#define SWRM_REG_VAL_PACK(data, dev, id, reg) \
|
||||||
|
((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
|
||||||
|
|
||||||
|
#define SWRM_MAX_ROW_VAL 0 /* Rows = 48 */
|
||||||
|
#define SWRM_DEFAULT_ROWS 48
|
||||||
|
#define SWRM_MIN_COL_VAL 0 /* Cols = 2 */
|
||||||
|
#define SWRM_DEFAULT_COL 16
|
||||||
|
#define SWRM_MAX_COL_VAL 7
|
||||||
|
#define SWRM_SPECIAL_CMD_ID 0xF
|
||||||
|
#define MAX_FREQ_NUM 1
|
||||||
|
#define TIMEOUT_MS (2 * HZ)
|
||||||
|
#define QCOM_SWRM_MAX_RD_LEN 0xf
|
||||||
|
#define QCOM_SDW_MAX_PORTS 14
|
||||||
|
#define DEFAULT_CLK_FREQ 9600000
|
||||||
|
#define SWRM_MAX_DAIS 0xF
|
||||||
|
|
||||||
|
struct qcom_swrm_port_config {
|
||||||
|
u8 si;
|
||||||
|
u8 off1;
|
||||||
|
u8 off2;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct qcom_swrm_ctrl {
|
||||||
|
struct sdw_bus bus;
|
||||||
|
struct device *dev;
|
||||||
|
struct regmap *regmap;
|
||||||
|
struct completion *comp;
|
||||||
|
struct work_struct slave_work;
|
||||||
|
/* read/write lock */
|
||||||
|
spinlock_t comp_lock;
|
||||||
|
/* Port alloc/free lock */
|
||||||
|
struct mutex port_lock;
|
||||||
|
struct clk *hclk;
|
||||||
|
u8 wr_cmd_id;
|
||||||
|
u8 rd_cmd_id;
|
||||||
|
int irq;
|
||||||
|
unsigned int version;
|
||||||
|
int num_din_ports;
|
||||||
|
int num_dout_ports;
|
||||||
|
unsigned long dout_port_mask;
|
||||||
|
unsigned long din_port_mask;
|
||||||
|
struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
|
||||||
|
struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
|
||||||
|
enum sdw_slave_status status[SDW_MAX_DEVICES];
|
||||||
|
int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
|
||||||
|
int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
|
||||||
|
};
|
||||||
|
|
||||||
|
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
|
||||||
|
|
||||||
|
static int qcom_swrm_abh_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
|
||||||
|
u32 *val)
|
||||||
|
{
|
||||||
|
struct regmap *wcd_regmap = ctrl->regmap;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* pg register + offset */
|
||||||
|
ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
|
||||||
|
(u8 *)®, 4);
|
||||||
|
if (ret < 0)
|
||||||
|
return SDW_CMD_FAIL;
|
||||||
|
|
||||||
|
ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
|
||||||
|
val, 4);
|
||||||
|
if (ret < 0)
|
||||||
|
return SDW_CMD_FAIL;
|
||||||
|
|
||||||
|
return SDW_CMD_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
|
||||||
|
int reg, int val)
|
||||||
|
{
|
||||||
|
struct regmap *wcd_regmap = ctrl->regmap;
|
||||||
|
int ret;
|
||||||
|
/* pg register + offset */
|
||||||
|
ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
|
||||||
|
(u8 *)&val, 4);
|
||||||
|
if (ret)
|
||||||
|
return SDW_CMD_FAIL;
|
||||||
|
|
||||||
|
/* write address register */
|
||||||
|
ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
|
||||||
|
(u8 *)®, 4);
|
||||||
|
if (ret)
|
||||||
|
return SDW_CMD_FAIL;
|
||||||
|
|
||||||
|
return SDW_CMD_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
|
||||||
|
u8 dev_addr, u16 reg_addr)
|
||||||
|
{
|
||||||
|
DECLARE_COMPLETION_ONSTACK(comp);
|
||||||
|
unsigned long flags;
|
||||||
|
u32 val;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ctrl->comp_lock, flags);
|
||||||
|
ctrl->comp = ∁
|
||||||
|
spin_unlock_irqrestore(&ctrl->comp_lock, flags);
|
||||||
|
val = SWRM_REG_VAL_PACK(cmd_data, dev_addr,
|
||||||
|
SWRM_SPECIAL_CMD_ID, reg_addr);
|
||||||
|
ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
ret = wait_for_completion_timeout(ctrl->comp,
|
||||||
|
msecs_to_jiffies(TIMEOUT_MS));
|
||||||
|
|
||||||
|
if (!ret)
|
||||||
|
ret = SDW_CMD_IGNORED;
|
||||||
|
else
|
||||||
|
ret = SDW_CMD_OK;
|
||||||
|
err:
|
||||||
|
spin_lock_irqsave(&ctrl->comp_lock, flags);
|
||||||
|
ctrl->comp = NULL;
|
||||||
|
spin_unlock_irqrestore(&ctrl->comp_lock, flags);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
|
||||||
|
u8 dev_addr, u16 reg_addr,
|
||||||
|
u32 len, u8 *rval)
|
||||||
|
{
|
||||||
|
int i, ret;
|
||||||
|
u32 val;
|
||||||
|
DECLARE_COMPLETION_ONSTACK(comp);
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
spin_lock_irqsave(&ctrl->comp_lock, flags);
|
||||||
|
ctrl->comp = ∁
|
||||||
|
spin_unlock_irqrestore(&ctrl->comp_lock, flags);
|
||||||
|
|
||||||
|
val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);
|
||||||
|
ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
ret = wait_for_completion_timeout(ctrl->comp,
|
||||||
|
msecs_to_jiffies(TIMEOUT_MS));
|
||||||
|
|
||||||
|
if (!ret) {
|
||||||
|
ret = SDW_CMD_IGNORED;
|
||||||
|
goto err;
|
||||||
|
} else {
|
||||||
|
ret = SDW_CMD_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < len; i++) {
|
||||||
|
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
|
||||||
|
rval[i] = val & 0xFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
err:
|
||||||
|
spin_lock_irqsave(&ctrl->comp_lock, flags);
|
||||||
|
ctrl->comp = NULL;
|
||||||
|
spin_unlock_irqrestore(&ctrl->comp_lock, flags);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
|
||||||
|
|
||||||
|
for (i = 0; i < SDW_MAX_DEVICES; i++) {
|
||||||
|
u32 s;
|
||||||
|
|
||||||
|
s = (val >> (i * 2));
|
||||||
|
s &= SWRM_MCP_SLV_STATUS_MASK;
|
||||||
|
ctrl->status[i] = s;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_id;
|
||||||
|
u32 sts, value;
|
||||||
|
unsigned long flags;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
|
||||||
|
|
||||||
|
if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) {
|
||||||
|
ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
|
||||||
|
dev_err_ratelimited(ctrl->dev,
|
||||||
|
"CMD error, fifo status 0x%x\n",
|
||||||
|
value);
|
||||||
|
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
|
||||||
|
sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
|
||||||
|
schedule_work(&ctrl->slave_work);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* clear the interrupt before complete() is called, as complete can
|
||||||
|
* schedule new read/writes which require interrupts, clearing the
|
||||||
|
* interrupt would avoid missing interrupts in such cases.
|
||||||
|
*/
|
||||||
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
|
||||||
|
|
||||||
|
if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
|
||||||
|
spin_lock_irqsave(&ctrl->comp_lock, flags);
|
||||||
|
if (ctrl->comp)
|
||||||
|
complete(ctrl->comp);
|
||||||
|
spin_unlock_irqrestore(&ctrl->comp_lock, flags);
|
||||||
|
}
|
||||||
|
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
/* Clear Rows and Cols */
|
||||||
|
val = (SWRM_MAX_ROW_VAL << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT |
|
||||||
|
SWRM_MIN_COL_VAL << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT);
|
||||||
|
|
||||||
|
ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
|
||||||
|
|
||||||
|
/* Disable Auto enumeration */
|
||||||
|
ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
|
||||||
|
|
||||||
|
/* Mask soundwire interrupts */
|
||||||
|
ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
|
||||||
|
SWRM_INTERRUPT_STATUS_RMSK);
|
||||||
|
|
||||||
|
/* Configure No pings */
|
||||||
|
ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
|
||||||
|
val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK;
|
||||||
|
val |= (SWRM_DEF_CMD_NO_PINGS <<
|
||||||
|
SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT);
|
||||||
|
ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
|
||||||
|
|
||||||
|
/* Configure number of retries of a read/write cmd */
|
||||||
|
ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
|
||||||
|
|
||||||
|
/* Set IRQ to PULSE */
|
||||||
|
ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
|
||||||
|
SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
|
||||||
|
SWRM_COMP_CFG_ENABLE_MSK);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
|
||||||
|
struct sdw_msg *msg)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
||||||
|
int ret, i, len;
|
||||||
|
|
||||||
|
if (msg->flags == SDW_MSG_FLAG_READ) {
|
||||||
|
for (i = 0; i < msg->len;) {
|
||||||
|
if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
|
||||||
|
len = msg->len - i;
|
||||||
|
else
|
||||||
|
len = QCOM_SWRM_MAX_RD_LEN;
|
||||||
|
|
||||||
|
ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
|
||||||
|
msg->addr + i, len,
|
||||||
|
&msg->buf[i]);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
i = i + len;
|
||||||
|
}
|
||||||
|
} else if (msg->flags == SDW_MSG_FLAG_WRITE) {
|
||||||
|
for (i = 0; i < msg->len; i++) {
|
||||||
|
ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
|
||||||
|
msg->dev_num,
|
||||||
|
msg->addr + i);
|
||||||
|
if (ret)
|
||||||
|
return SDW_CMD_IGNORED;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return SDW_CMD_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
|
||||||
|
{
|
||||||
|
u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
|
||||||
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, reg, &val);
|
||||||
|
|
||||||
|
val &= ~SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK;
|
||||||
|
val &= ~SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK;
|
||||||
|
|
||||||
|
val |= (SWRM_MAX_ROW_VAL << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT |
|
||||||
|
SWRM_MAX_COL_VAL << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT);
|
||||||
|
|
||||||
|
return ctrl->reg_write(ctrl, reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_port_params(struct sdw_bus *bus,
|
||||||
|
struct sdw_port_params *p_params,
|
||||||
|
unsigned int bank)
|
||||||
|
{
|
||||||
|
/* TBD */
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_transport_params(struct sdw_bus *bus,
|
||||||
|
struct sdw_transport_params *params,
|
||||||
|
enum sdw_reg_bank bank)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
||||||
|
u32 value;
|
||||||
|
|
||||||
|
value = params->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
|
||||||
|
value |= params->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
|
||||||
|
value |= params->sample_interval - 1;
|
||||||
|
|
||||||
|
return ctrl->reg_write(ctrl,
|
||||||
|
SWRM_DP_PORT_CTRL_BANK((params->port_num), bank),
|
||||||
|
value);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_port_enable(struct sdw_bus *bus,
|
||||||
|
struct sdw_enable_ch *enable_ch,
|
||||||
|
unsigned int bank)
|
||||||
|
{
|
||||||
|
u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
|
||||||
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, reg, &val);
|
||||||
|
|
||||||
|
if (enable_ch->enable)
|
||||||
|
val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
|
||||||
|
else
|
||||||
|
val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
|
||||||
|
|
||||||
|
return ctrl->reg_write(ctrl, reg, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct sdw_master_port_ops qcom_swrm_port_ops = {
|
||||||
|
.dpn_set_port_params = qcom_swrm_port_params,
|
||||||
|
.dpn_set_port_transport_params = qcom_swrm_transport_params,
|
||||||
|
.dpn_port_enable_ch = qcom_swrm_port_enable,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct sdw_master_ops qcom_swrm_ops = {
|
||||||
|
.xfer_msg = qcom_swrm_xfer_msg,
|
||||||
|
.pre_bank_switch = qcom_swrm_pre_bank_switch,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int qcom_swrm_compute_params(struct sdw_bus *bus)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
|
||||||
|
struct sdw_master_runtime *m_rt;
|
||||||
|
struct sdw_slave_runtime *s_rt;
|
||||||
|
struct sdw_port_runtime *p_rt;
|
||||||
|
struct qcom_swrm_port_config *pcfg;
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
|
||||||
|
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
|
||||||
|
pcfg = &ctrl->pconfig[p_rt->num - 1];
|
||||||
|
p_rt->transport_params.port_num = p_rt->num;
|
||||||
|
p_rt->transport_params.sample_interval = pcfg->si + 1;
|
||||||
|
p_rt->transport_params.offset1 = pcfg->off1;
|
||||||
|
p_rt->transport_params.offset2 = pcfg->off2;
|
||||||
|
}
|
||||||
|
|
||||||
|
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
|
||||||
|
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
|
||||||
|
pcfg = &ctrl->pconfig[i];
|
||||||
|
p_rt->transport_params.port_num = p_rt->num;
|
||||||
|
p_rt->transport_params.sample_interval =
|
||||||
|
pcfg->si + 1;
|
||||||
|
p_rt->transport_params.offset1 = pcfg->off1;
|
||||||
|
p_rt->transport_params.offset2 = pcfg->off2;
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
|
||||||
|
DEFAULT_CLK_FREQ,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void qcom_swrm_slave_wq(struct work_struct *work)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl =
|
||||||
|
container_of(work, struct qcom_swrm_ctrl, slave_work);
|
||||||
|
|
||||||
|
qcom_swrm_get_device_status(ctrl);
|
||||||
|
sdw_handle_slave_status(&ctrl->bus, ctrl->status);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
|
||||||
|
struct sdw_stream_runtime *stream)
|
||||||
|
{
|
||||||
|
struct sdw_master_runtime *m_rt;
|
||||||
|
struct sdw_port_runtime *p_rt;
|
||||||
|
unsigned long *port_mask;
|
||||||
|
|
||||||
|
mutex_lock(&ctrl->port_lock);
|
||||||
|
|
||||||
|
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
|
||||||
|
if (m_rt->direction == SDW_DATA_DIR_RX)
|
||||||
|
port_mask = &ctrl->dout_port_mask;
|
||||||
|
else
|
||||||
|
port_mask = &ctrl->din_port_mask;
|
||||||
|
|
||||||
|
list_for_each_entry(p_rt, &m_rt->port_list, port_node)
|
||||||
|
clear_bit(p_rt->num - 1, port_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_unlock(&ctrl->port_lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
|
||||||
|
struct sdw_stream_runtime *stream,
|
||||||
|
struct snd_pcm_hw_params *params,
|
||||||
|
int direction)
|
||||||
|
{
|
||||||
|
struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
|
||||||
|
struct sdw_stream_config sconfig;
|
||||||
|
struct sdw_master_runtime *m_rt;
|
||||||
|
struct sdw_slave_runtime *s_rt;
|
||||||
|
struct sdw_port_runtime *p_rt;
|
||||||
|
unsigned long *port_mask;
|
||||||
|
int i, maxport, pn, nports = 0, ret = 0;
|
||||||
|
|
||||||
|
mutex_lock(&ctrl->port_lock);
|
||||||
|
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
|
||||||
|
if (m_rt->direction == SDW_DATA_DIR_RX) {
|
||||||
|
maxport = ctrl->num_dout_ports;
|
||||||
|
port_mask = &ctrl->dout_port_mask;
|
||||||
|
} else {
|
||||||
|
maxport = ctrl->num_din_ports;
|
||||||
|
port_mask = &ctrl->din_port_mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
|
||||||
|
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
|
||||||
|
/* Port numbers start from 1 - 14*/
|
||||||
|
pn = find_first_zero_bit(port_mask, maxport);
|
||||||
|
if (pn > (maxport - 1)) {
|
||||||
|
dev_err(ctrl->dev, "All ports busy\n");
|
||||||
|
ret = -EBUSY;
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
set_bit(pn, port_mask);
|
||||||
|
pconfig[nports].num = pn + 1;
|
||||||
|
pconfig[nports].ch_mask = p_rt->ch_mask;
|
||||||
|
nports++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (direction == SNDRV_PCM_STREAM_CAPTURE)
|
||||||
|
sconfig.direction = SDW_DATA_DIR_TX;
|
||||||
|
else
|
||||||
|
sconfig.direction = SDW_DATA_DIR_RX;
|
||||||
|
|
||||||
|
/* hw parameters wil be ignored as we only support PDM */
|
||||||
|
sconfig.ch_count = 1;
|
||||||
|
sconfig.frame_rate = params_rate(params);
|
||||||
|
sconfig.type = stream->type;
|
||||||
|
sconfig.bps = 1;
|
||||||
|
sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
|
||||||
|
nports, stream);
|
||||||
|
err:
|
||||||
|
if (ret) {
|
||||||
|
for (i = 0; i < nports; i++)
|
||||||
|
clear_bit(pconfig[i].num - 1, port_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_unlock(&ctrl->port_lock);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
|
||||||
|
struct snd_pcm_hw_params *params,
|
||||||
|
struct snd_soc_dai *dai)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
||||||
|
struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
|
||||||
|
substream->stream);
|
||||||
|
if (ret)
|
||||||
|
qcom_swrm_stream_free_ports(ctrl, sruntime);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
|
||||||
|
struct snd_soc_dai *dai)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
||||||
|
struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
|
||||||
|
|
||||||
|
qcom_swrm_stream_free_ports(ctrl, sruntime);
|
||||||
|
sdw_stream_remove_master(&ctrl->bus, sruntime);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
|
||||||
|
void *stream, int direction)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
||||||
|
|
||||||
|
ctrl->sruntime[dai->id] = stream;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_startup(struct snd_pcm_substream *substream,
|
||||||
|
struct snd_soc_dai *dai)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
||||||
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||||
|
struct sdw_stream_runtime *sruntime;
|
||||||
|
int ret, i;
|
||||||
|
|
||||||
|
sruntime = sdw_alloc_stream(dai->name);
|
||||||
|
if (!sruntime)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
ctrl->sruntime[dai->id] = sruntime;
|
||||||
|
|
||||||
|
for (i = 0; i < rtd->num_codecs; i++) {
|
||||||
|
ret = snd_soc_dai_set_sdw_stream(rtd->codec_dais[i], sruntime,
|
||||||
|
substream->stream);
|
||||||
|
if (ret < 0 && ret != -ENOTSUPP) {
|
||||||
|
dev_err(dai->dev, "Failed to set sdw stream on %s",
|
||||||
|
rtd->codec_dais[i]->name);
|
||||||
|
sdw_release_stream(sruntime);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
|
||||||
|
struct snd_soc_dai *dai)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
|
||||||
|
|
||||||
|
sdw_release_stream(ctrl->sruntime[dai->id]);
|
||||||
|
ctrl->sruntime[dai->id] = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
|
||||||
|
.hw_params = qcom_swrm_hw_params,
|
||||||
|
.hw_free = qcom_swrm_hw_free,
|
||||||
|
.startup = qcom_swrm_startup,
|
||||||
|
.shutdown = qcom_swrm_shutdown,
|
||||||
|
.set_sdw_stream = qcom_swrm_set_sdw_stream,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct snd_soc_component_driver qcom_swrm_dai_component = {
|
||||||
|
.name = "soundwire",
|
||||||
|
};
|
||||||
|
|
||||||
|
static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
|
||||||
|
{
|
||||||
|
int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
|
||||||
|
struct snd_soc_dai_driver *dais;
|
||||||
|
struct snd_soc_pcm_stream *stream;
|
||||||
|
struct device *dev = ctrl->dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* PDM dais are only tested for now */
|
||||||
|
dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
|
||||||
|
if (!dais)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
for (i = 0; i < num_dais; i++) {
|
||||||
|
dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
|
||||||
|
if (!dais[i].name)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
if (i < ctrl->num_dout_ports)
|
||||||
|
stream = &dais[i].playback;
|
||||||
|
else
|
||||||
|
stream = &dais[i].capture;
|
||||||
|
|
||||||
|
stream->channels_min = 1;
|
||||||
|
stream->channels_max = 1;
|
||||||
|
stream->rates = SNDRV_PCM_RATE_48000;
|
||||||
|
stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
|
||||||
|
|
||||||
|
dais[i].ops = &qcom_swrm_pdm_dai_ops;
|
||||||
|
dais[i].id = i;
|
||||||
|
}
|
||||||
|
|
||||||
|
return devm_snd_soc_register_component(ctrl->dev,
|
||||||
|
&qcom_swrm_dai_component,
|
||||||
|
dais, num_dais);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
|
||||||
|
{
|
||||||
|
struct device_node *np = ctrl->dev->of_node;
|
||||||
|
u8 off1[QCOM_SDW_MAX_PORTS];
|
||||||
|
u8 off2[QCOM_SDW_MAX_PORTS];
|
||||||
|
u8 si[QCOM_SDW_MAX_PORTS];
|
||||||
|
int i, ret, nports, val;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
|
||||||
|
|
||||||
|
ctrl->num_dout_ports = val & SWRM_COMP_PARAMS_DOUT_PORTS_MASK;
|
||||||
|
ctrl->num_din_ports = (val & SWRM_COMP_PARAMS_DIN_PORTS_MASK) >> 5;
|
||||||
|
|
||||||
|
ret = of_property_read_u32(np, "qcom,din-ports", &val);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (val > ctrl->num_din_ports)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
ctrl->num_din_ports = val;
|
||||||
|
|
||||||
|
ret = of_property_read_u32(np, "qcom,dout-ports", &val);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (val > ctrl->num_dout_ports)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
ctrl->num_dout_ports = val;
|
||||||
|
|
||||||
|
nports = ctrl->num_dout_ports + ctrl->num_din_ports;
|
||||||
|
|
||||||
|
ret = of_property_read_u8_array(np, "qcom,ports-offset1",
|
||||||
|
off1, nports);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = of_property_read_u8_array(np, "qcom,ports-offset2",
|
||||||
|
off2, nports);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
|
||||||
|
si, nports);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
for (i = 0; i < nports; i++) {
|
||||||
|
ctrl->pconfig[i].si = si[i];
|
||||||
|
ctrl->pconfig[i].off1 = off1[i];
|
||||||
|
ctrl->pconfig[i].off2 = off2[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
struct sdw_master_prop *prop;
|
||||||
|
struct sdw_bus_params *params;
|
||||||
|
struct qcom_swrm_ctrl *ctrl;
|
||||||
|
int ret;
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
|
||||||
|
if (!ctrl)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
if (dev->parent->bus == &slimbus_bus) {
|
||||||
|
ctrl->reg_read = qcom_swrm_abh_reg_read;
|
||||||
|
ctrl->reg_write = qcom_swrm_ahb_reg_write;
|
||||||
|
ctrl->regmap = dev_get_regmap(dev->parent, NULL);
|
||||||
|
if (!ctrl->regmap)
|
||||||
|
return -EINVAL;
|
||||||
|
} else {
|
||||||
|
/* Only WCD based SoundWire controller is supported */
|
||||||
|
return -ENOTSUPP;
|
||||||
|
}
|
||||||
|
|
||||||
|
ctrl->irq = of_irq_get(dev->of_node, 0);
|
||||||
|
if (ctrl->irq < 0)
|
||||||
|
return ctrl->irq;
|
||||||
|
|
||||||
|
ctrl->hclk = devm_clk_get(dev, "iface");
|
||||||
|
if (IS_ERR(ctrl->hclk))
|
||||||
|
return PTR_ERR(ctrl->hclk);
|
||||||
|
|
||||||
|
clk_prepare_enable(ctrl->hclk);
|
||||||
|
|
||||||
|
ctrl->dev = dev;
|
||||||
|
dev_set_drvdata(&pdev->dev, ctrl);
|
||||||
|
spin_lock_init(&ctrl->comp_lock);
|
||||||
|
mutex_init(&ctrl->port_lock);
|
||||||
|
INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
|
||||||
|
|
||||||
|
ctrl->bus.dev = dev;
|
||||||
|
ctrl->bus.ops = &qcom_swrm_ops;
|
||||||
|
ctrl->bus.port_ops = &qcom_swrm_port_ops;
|
||||||
|
ctrl->bus.compute_params = &qcom_swrm_compute_params;
|
||||||
|
|
||||||
|
ret = qcom_swrm_get_port_config(ctrl);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
params = &ctrl->bus.params;
|
||||||
|
params->max_dr_freq = DEFAULT_CLK_FREQ;
|
||||||
|
params->curr_dr_freq = DEFAULT_CLK_FREQ;
|
||||||
|
params->col = SWRM_DEFAULT_COL;
|
||||||
|
params->row = SWRM_DEFAULT_ROWS;
|
||||||
|
ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
|
||||||
|
params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
|
||||||
|
params->next_bank = !params->curr_bank;
|
||||||
|
|
||||||
|
prop = &ctrl->bus.prop;
|
||||||
|
prop->max_clk_freq = DEFAULT_CLK_FREQ;
|
||||||
|
prop->num_clk_gears = 0;
|
||||||
|
prop->num_clk_freq = MAX_FREQ_NUM;
|
||||||
|
prop->clk_freq = &qcom_swrm_freq_tbl[0];
|
||||||
|
prop->default_col = SWRM_DEFAULT_COL;
|
||||||
|
prop->default_row = SWRM_DEFAULT_ROWS;
|
||||||
|
|
||||||
|
ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
|
||||||
|
|
||||||
|
ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
|
||||||
|
qcom_swrm_irq_handler,
|
||||||
|
IRQF_TRIGGER_RISING,
|
||||||
|
"soundwire", ctrl);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "Failed to request soundwire irq\n");
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = sdw_add_bus_master(&ctrl->bus);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "Failed to register Soundwire controller (%d)\n",
|
||||||
|
ret);
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
qcom_swrm_init(ctrl);
|
||||||
|
ret = qcom_swrm_register_dais(ctrl);
|
||||||
|
if (ret)
|
||||||
|
goto err;
|
||||||
|
|
||||||
|
dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
|
||||||
|
(ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
|
||||||
|
ctrl->version & 0xffff);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
err:
|
||||||
|
clk_disable_unprepare(ctrl->hclk);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int qcom_swrm_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
|
||||||
|
|
||||||
|
sdw_delete_bus_master(&ctrl->bus);
|
||||||
|
clk_disable_unprepare(ctrl->hclk);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id qcom_swrm_of_match[] = {
|
||||||
|
{ .compatible = "qcom,soundwire-v1.3.0", },
|
||||||
|
{/* sentinel */},
|
||||||
|
};
|
||||||
|
|
||||||
|
MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
|
||||||
|
|
||||||
|
static struct platform_driver qcom_swrm_driver = {
|
||||||
|
.probe = &qcom_swrm_probe,
|
||||||
|
.remove = &qcom_swrm_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = "qcom-soundwire",
|
||||||
|
.of_match_table = qcom_swrm_of_match,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
module_platform_driver(qcom_swrm_driver);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("Qualcomm soundwire driver");
|
||||||
|
MODULE_LICENSE("GPL v2");
|
@ -1554,8 +1554,6 @@ int sdw_prepare_stream(struct sdw_stream_runtime *stream)
|
|||||||
sdw_acquire_bus_lock(stream);
|
sdw_acquire_bus_lock(stream);
|
||||||
|
|
||||||
ret = _sdw_prepare_stream(stream);
|
ret = _sdw_prepare_stream(stream);
|
||||||
if (ret < 0)
|
|
||||||
pr_err("Prepare for stream:%s failed: %d\n", stream->name, ret);
|
|
||||||
|
|
||||||
sdw_release_bus_lock(stream);
|
sdw_release_bus_lock(stream);
|
||||||
return ret;
|
return ret;
|
||||||
@ -1622,8 +1620,6 @@ int sdw_enable_stream(struct sdw_stream_runtime *stream)
|
|||||||
sdw_acquire_bus_lock(stream);
|
sdw_acquire_bus_lock(stream);
|
||||||
|
|
||||||
ret = _sdw_enable_stream(stream);
|
ret = _sdw_enable_stream(stream);
|
||||||
if (ret < 0)
|
|
||||||
pr_err("Enable for stream:%s failed: %d\n", stream->name, ret);
|
|
||||||
|
|
||||||
sdw_release_bus_lock(stream);
|
sdw_release_bus_lock(stream);
|
||||||
return ret;
|
return ret;
|
||||||
@ -1698,8 +1694,6 @@ int sdw_disable_stream(struct sdw_stream_runtime *stream)
|
|||||||
sdw_acquire_bus_lock(stream);
|
sdw_acquire_bus_lock(stream);
|
||||||
|
|
||||||
ret = _sdw_disable_stream(stream);
|
ret = _sdw_disable_stream(stream);
|
||||||
if (ret < 0)
|
|
||||||
pr_err("Disable for stream:%s failed: %d\n", stream->name, ret);
|
|
||||||
|
|
||||||
sdw_release_bus_lock(stream);
|
sdw_release_bus_lock(stream);
|
||||||
return ret;
|
return ret;
|
||||||
@ -1756,8 +1750,6 @@ int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
|
|||||||
|
|
||||||
sdw_acquire_bus_lock(stream);
|
sdw_acquire_bus_lock(stream);
|
||||||
ret = _sdw_deprepare_stream(stream);
|
ret = _sdw_deprepare_stream(stream);
|
||||||
if (ret < 0)
|
|
||||||
pr_err("De-prepare for stream:%d failed: %d\n", ret, ret);
|
|
||||||
|
|
||||||
sdw_release_bus_lock(stream);
|
sdw_release_bus_lock(stream);
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -546,7 +546,22 @@ struct sdw_slave_ops {
|
|||||||
* @debugfs: Slave debugfs
|
* @debugfs: Slave debugfs
|
||||||
* @node: node for bus list
|
* @node: node for bus list
|
||||||
* @port_ready: Port ready completion flag for each Slave port
|
* @port_ready: Port ready completion flag for each Slave port
|
||||||
* @dev_num: Device Number assigned by Bus
|
* @dev_num: Current Device Number, values can be 0 or dev_num_sticky
|
||||||
|
* @dev_num_sticky: one-time static Device Number assigned by Bus
|
||||||
|
* @probed: boolean tracking driver state
|
||||||
|
* @probe_complete: completion utility to control potential races
|
||||||
|
* on startup between driver probe/initialization and SoundWire
|
||||||
|
* Slave state changes/implementation-defined interrupts
|
||||||
|
* @enumeration_complete: completion utility to control potential races
|
||||||
|
* on startup between device enumeration and read/write access to the
|
||||||
|
* Slave device
|
||||||
|
* @initialization_complete: completion utility to control potential races
|
||||||
|
* on startup between device enumeration and settings being restored
|
||||||
|
* @unattach_request: mask field to keep track why the Slave re-attached and
|
||||||
|
* was re-initialized. This is useful to deal with potential race conditions
|
||||||
|
* between the Master suspending and the codec resuming, and make sure that
|
||||||
|
* when the Master triggered a reset the Slave is properly enumerated and
|
||||||
|
* initialized
|
||||||
*/
|
*/
|
||||||
struct sdw_slave {
|
struct sdw_slave {
|
||||||
struct sdw_slave_id id;
|
struct sdw_slave_id id;
|
||||||
@ -561,6 +576,12 @@ struct sdw_slave {
|
|||||||
struct list_head node;
|
struct list_head node;
|
||||||
struct completion *port_ready;
|
struct completion *port_ready;
|
||||||
u16 dev_num;
|
u16 dev_num;
|
||||||
|
u16 dev_num_sticky;
|
||||||
|
bool probed;
|
||||||
|
struct completion probe_complete;
|
||||||
|
struct completion enumeration_complete;
|
||||||
|
struct completion initialization_complete;
|
||||||
|
u32 unattach_request;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
|
#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
|
||||||
|
@ -4,36 +4,185 @@
|
|||||||
#ifndef __SDW_INTEL_H
|
#ifndef __SDW_INTEL_H
|
||||||
#define __SDW_INTEL_H
|
#define __SDW_INTEL_H
|
||||||
|
|
||||||
|
#include <linux/irqreturn.h>
|
||||||
|
#include <linux/soundwire/sdw.h>
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct sdw_intel_ops: Intel audio driver callback ops
|
* struct sdw_intel_stream_params_data: configuration passed during
|
||||||
*
|
* the @params_stream callback, e.g. for interaction with DSP
|
||||||
* @config_stream: configure the stream with the hw_params
|
* firmware.
|
||||||
* the first argument containing the context is mandatory
|
|
||||||
*/
|
*/
|
||||||
struct sdw_intel_ops {
|
struct sdw_intel_stream_params_data {
|
||||||
int (*config_stream)(void *arg, void *substream,
|
struct snd_pcm_substream *substream;
|
||||||
void *dai, void *hw_params, int stream_num);
|
struct snd_soc_dai *dai;
|
||||||
|
struct snd_pcm_hw_params *hw_params;
|
||||||
|
int link_id;
|
||||||
|
int alh_stream_id;
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct sdw_intel_res - Soundwire Intel resource structure
|
* struct sdw_intel_stream_free_data: configuration passed during
|
||||||
|
* the @free_stream callback, e.g. for interaction with DSP
|
||||||
|
* firmware.
|
||||||
|
*/
|
||||||
|
struct sdw_intel_stream_free_data {
|
||||||
|
struct snd_pcm_substream *substream;
|
||||||
|
struct snd_soc_dai *dai;
|
||||||
|
int link_id;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct sdw_intel_ops: Intel audio driver callback ops
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
struct sdw_intel_ops {
|
||||||
|
int (*params_stream)(struct device *dev,
|
||||||
|
struct sdw_intel_stream_params_data *params_data);
|
||||||
|
int (*free_stream)(struct device *dev,
|
||||||
|
struct sdw_intel_stream_free_data *free_data);
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
|
||||||
|
* @handle: ACPI controller handle
|
||||||
|
* @count: link count found with "sdw-master-count" property
|
||||||
|
* @link_mask: bit-wise mask listing links enabled by BIOS menu
|
||||||
|
*
|
||||||
|
* this structure could be expanded to e.g. provide all the _ADR
|
||||||
|
* information in case the link_mask is not sufficient to identify
|
||||||
|
* platform capabilities.
|
||||||
|
*/
|
||||||
|
struct sdw_intel_acpi_info {
|
||||||
|
acpi_handle handle;
|
||||||
|
int count;
|
||||||
|
u32 link_mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sdw_intel_link_res;
|
||||||
|
|
||||||
|
/* Intel clock-stop/pm_runtime quirk definitions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Force the clock to remain on during pm_runtime suspend. This might
|
||||||
|
* be needed if Slave devices do not have an alternate clock source or
|
||||||
|
* if the latency requirements are very strict.
|
||||||
|
*/
|
||||||
|
#define SDW_INTEL_CLK_STOP_NOT_ALLOWED BIT(0)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Stop the bus during pm_runtime suspend. If set, a complete bus
|
||||||
|
* reset and re-enumeration will be performed when the bus
|
||||||
|
* restarts. This mode shall not be used if Slave devices can generate
|
||||||
|
* in-band wakes.
|
||||||
|
*/
|
||||||
|
#define SDW_INTEL_CLK_STOP_TEARDOWN BIT(1)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Stop the bus during pm_suspend if Slaves are not wake capable
|
||||||
|
* (e.g. speaker amplifiers). The clock-stop mode is typically
|
||||||
|
* slightly higher power than when the IP is completely powered-off.
|
||||||
|
*/
|
||||||
|
#define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY BIT(2)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Require a bus reset (and complete re-enumeration) when exiting
|
||||||
|
* clock stop modes. This may be needed if the controller power was
|
||||||
|
* turned off and all context lost. This quirk shall not be used if a
|
||||||
|
* Slave device needs to remain enumerated and keep its context,
|
||||||
|
* e.g. to provide the reasons for the wake, report acoustic events or
|
||||||
|
* pass a history buffer.
|
||||||
|
*/
|
||||||
|
#define SDW_INTEL_CLK_STOP_BUS_RESET BIT(3)
|
||||||
|
|
||||||
|
struct sdw_intel_slave_id {
|
||||||
|
int link_id;
|
||||||
|
struct sdw_slave_id id;
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct sdw_intel_ctx - context allocated by the controller
|
||||||
|
* driver probe
|
||||||
|
* @count: link count
|
||||||
|
* @mmio_base: mmio base of SoundWire registers, only used to check
|
||||||
|
* hardware capabilities after all power dependencies are settled.
|
||||||
|
* @link_mask: bit-wise mask listing SoundWire links reported by the
|
||||||
|
* Controller
|
||||||
|
* @num_slaves: total number of devices exposed across all enabled links
|
||||||
|
* @handle: ACPI parent handle
|
||||||
|
* @links: information for each link (controller-specific and kept
|
||||||
|
* opaque here)
|
||||||
|
* @ids: array of slave_id, representing Slaves exposed across all enabled
|
||||||
|
* links
|
||||||
|
* @link_list: list to handle interrupts across all links
|
||||||
|
* @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers.
|
||||||
|
*/
|
||||||
|
struct sdw_intel_ctx {
|
||||||
|
int count;
|
||||||
|
void __iomem *mmio_base;
|
||||||
|
u32 link_mask;
|
||||||
|
int num_slaves;
|
||||||
|
acpi_handle handle;
|
||||||
|
struct sdw_intel_link_res *links;
|
||||||
|
struct sdw_intel_slave_id *ids;
|
||||||
|
struct list_head link_list;
|
||||||
|
struct mutex shim_lock; /* lock for access to shared SHIM registers */
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* struct sdw_intel_res - Soundwire Intel global resource structure,
|
||||||
|
* typically populated by the DSP driver
|
||||||
|
*
|
||||||
|
* @count: link count
|
||||||
* @mmio_base: mmio base of SoundWire registers
|
* @mmio_base: mmio base of SoundWire registers
|
||||||
* @irq: interrupt number
|
* @irq: interrupt number
|
||||||
* @handle: ACPI parent handle
|
* @handle: ACPI parent handle
|
||||||
* @parent: parent device
|
* @parent: parent device
|
||||||
* @ops: callback ops
|
* @ops: callback ops
|
||||||
* @arg: callback arg
|
* @dev: device implementing hwparams and free callbacks
|
||||||
|
* @link_mask: bit-wise mask listing links selected by the DSP driver
|
||||||
|
* This mask may be a subset of the one reported by the controller since
|
||||||
|
* machine-specific quirks are handled in the DSP driver.
|
||||||
|
* @clock_stop_quirks: mask array of possible behaviors requested by the
|
||||||
|
* DSP driver. The quirks are common for all links for now.
|
||||||
*/
|
*/
|
||||||
struct sdw_intel_res {
|
struct sdw_intel_res {
|
||||||
|
int count;
|
||||||
void __iomem *mmio_base;
|
void __iomem *mmio_base;
|
||||||
int irq;
|
int irq;
|
||||||
acpi_handle handle;
|
acpi_handle handle;
|
||||||
struct device *parent;
|
struct device *parent;
|
||||||
const struct sdw_intel_ops *ops;
|
const struct sdw_intel_ops *ops;
|
||||||
void *arg;
|
struct device *dev;
|
||||||
|
u32 link_mask;
|
||||||
|
u32 clock_stop_quirks;
|
||||||
};
|
};
|
||||||
|
|
||||||
void *sdw_intel_init(acpi_handle *parent_handle, struct sdw_intel_res *res);
|
/*
|
||||||
void sdw_intel_exit(void *arg);
|
* On Intel platforms, the SoundWire IP has dependencies on power
|
||||||
|
* rails shared with the DSP, and the initialization steps are split
|
||||||
|
* in three. First an ACPI scan to check what the firmware describes
|
||||||
|
* in DSDT tables, then an allocation step (with no hardware
|
||||||
|
* configuration but with all the relevant devices created) and last
|
||||||
|
* the actual hardware configuration. The final stage is a global
|
||||||
|
* interrupt enable which is controlled by the DSP driver. Splitting
|
||||||
|
* these phases helps simplify the boot flow and make early decisions
|
||||||
|
* on e.g. which machine driver to select (I2S mode, HDaudio or
|
||||||
|
* SoundWire).
|
||||||
|
*/
|
||||||
|
int sdw_intel_acpi_scan(acpi_handle *parent_handle,
|
||||||
|
struct sdw_intel_acpi_info *info);
|
||||||
|
|
||||||
|
void sdw_intel_process_wakeen_event(struct sdw_intel_ctx *ctx);
|
||||||
|
|
||||||
|
struct sdw_intel_ctx *
|
||||||
|
sdw_intel_probe(struct sdw_intel_res *res);
|
||||||
|
|
||||||
|
int sdw_intel_startup(struct sdw_intel_ctx *ctx);
|
||||||
|
|
||||||
|
void sdw_intel_exit(struct sdw_intel_ctx *ctx);
|
||||||
|
|
||||||
|
void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable);
|
||||||
|
|
||||||
|
irqreturn_t sdw_intel_thread(int irq, void *dev_id);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
Loading…
Reference in New Issue
Block a user