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drm/amd/display: dce_link_encoder: add DCE6 specific macros,functions
[Why] DCE6 has no DP_DPHY_SCRAM_CNTL register [How] Add DCE6 specific macros definitions for LE registers DCE6 LE macros will avoid buiding errors when using DCE6 headers Add dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2() w/o Scramble Control programming Add dce60_set_dp_phy_pattern_passthrough_mode() w/o Scramble Control programming Add dce60_configure_encoder() w/o Scramble Control programming Add dce60_link_encoder_enable_dp_output() w/ dce60_configure_encoder Add dce60_link_encoder_enable_dp_mst_output() w/ dce60_configure_encoder Add dce60_link_encoder_dp_set_phy_pattern() w/ dce60_set_dp_phy_pattern_passthrough_mode Use dce60_link_encoder_enable_dp_output() in dce60_lnk_enc_funcs Use dce60_link_encoder_enable_dp_mst_output() in dce60_lnk_enc_funcs Use dce60_link_encoder_dp_set_phy_pattern() in dce60_lnk_enc_funcs Add DCE6 specific dce60_link_encoder_construct Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mauro Rossi
Alex Deucher
parent
89571d7c31
commit
c1a64ebd4d
@ -425,6 +425,59 @@ static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
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enable_phy_bypass_mode(enc110, false);
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static void dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(
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struct dce110_link_encoder *enc110,
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unsigned int cp2520_pattern)
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{
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/* previously there is a register DP_HBR2_EYE_PATTERN
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* that is enabled to get the pattern.
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* But it does not work with the latest spec change,
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* so we are programming the following registers manually.
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*
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* The following settings have been confirmed
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* by Nick Chorney and Sandra Liu */
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/* Disable PHY Bypass mode to setup the test pattern */
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enable_phy_bypass_mode(enc110, false);
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/* Setup DIG encoder in DP SST mode */
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enc110->base.funcs->setup(&enc110->base, SIGNAL_TYPE_DISPLAY_PORT);
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/* ensure normal panel mode. */
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setup_panel_mode(enc110, DP_PANEL_MODE_DEFAULT);
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/* no vbid after BS (SR)
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* DP_LINK_FRAMING_CNTL changed history Sandra Liu
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* 11000260 / 11000104 / 110000FC */
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REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
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DP_IDLE_BS_INTERVAL, 0xFC,
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DP_VBID_DISABLE, 1,
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DP_VID_ENHANCED_FRAME_MODE, 1);
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/* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip swap BS with SR */
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/* select cp2520 patterns */
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if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
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REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
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DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
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else
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/* pre-DCE11 can only generate CP2520 pattern 2 */
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ASSERT(cp2520_pattern == 2);
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/* set link training complete */
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set_link_training_complete(enc110, true);
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/* disable video stream */
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REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
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/* Disable PHY Bypass mode to setup the test pattern */
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enable_phy_bypass_mode(enc110, false);
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}
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#endif
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static void set_dp_phy_pattern_passthrough_mode(
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struct dce110_link_encoder *enc110,
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enum dp_panel_mode panel_mode)
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@ -452,6 +505,35 @@ static void set_dp_phy_pattern_passthrough_mode(
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disable_prbs_mode(enc110);
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static void dce60_set_dp_phy_pattern_passthrough_mode(
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struct dce110_link_encoder *enc110,
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enum dp_panel_mode panel_mode)
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{
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/* program correct panel mode */
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setup_panel_mode(enc110, panel_mode);
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/* restore LINK_FRAMING_CNTL
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* in case we were doing HBR2 compliance pattern before
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*/
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REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
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DP_IDLE_BS_INTERVAL, 0x2000,
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DP_VBID_DISABLE, 0,
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DP_VID_ENHANCED_FRAME_MODE, 1);
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/* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip DPHY_SCRAMBLER_BS_COUNT restore */
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/* set link training complete */
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set_link_training_complete(enc110, true);
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/* Disable PHY Bypass mode to setup the test pattern */
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enable_phy_bypass_mode(enc110, false);
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/* Disable PRBS mode */
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disable_prbs_mode(enc110);
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}
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#endif
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/* return value is bit-vector */
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static uint8_t get_frontend_source(
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enum engine_id engine)
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@ -490,6 +572,20 @@ static void configure_encoder(
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REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static void dce60_configure_encoder(
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struct dce110_link_encoder *enc110,
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const struct dc_link_settings *link_settings)
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{
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/* set number of lanes */
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REG_SET(DP_CONFIG, 0,
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DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
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/* DCE6 has no DP_DPHY_SCRAM_CNTL register, skip setup scrambler */
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}
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#endif
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static void aux_initialize(
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struct dce110_link_encoder *enc110)
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{
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@ -1059,6 +1155,87 @@ void dce110_link_encoder_enable_dp_mst_output(
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BREAK_TO_DEBUGGER();
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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/* enables DP PHY output */
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void dce60_link_encoder_enable_dp_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source)
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{
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struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
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struct bp_transmitter_control cntl = { 0 };
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enum bp_result result;
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/* Enable the PHY */
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/* number_of_lanes is used for pixel clock adjust,
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* but it's not passed to asic_control.
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* We need to set number of lanes manually.
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*/
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dce60_configure_encoder(enc110, link_settings);
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cntl.connector_obj_id = enc110->base.connector;
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cntl.action = TRANSMITTER_CONTROL_ENABLE;
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cntl.engine_id = enc->preferred_engine;
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cntl.transmitter = enc110->base.transmitter;
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cntl.pll_id = clock_source;
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cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
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cntl.lanes_number = link_settings->lane_count;
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cntl.hpd_sel = enc110->base.hpd_source;
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cntl.pixel_clock = link_settings->link_rate
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* LINK_RATE_REF_FREQ_IN_KHZ;
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/* TODO: check if undefined works */
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cntl.color_depth = COLOR_DEPTH_UNDEFINED;
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result = link_transmitter_control(enc110, &cntl);
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if (result != BP_RESULT_OK) {
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DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
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__func__);
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BREAK_TO_DEBUGGER();
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}
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}
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/* enables DP PHY output in MST mode */
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void dce60_link_encoder_enable_dp_mst_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source)
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{
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struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
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struct bp_transmitter_control cntl = { 0 };
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enum bp_result result;
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/* Enable the PHY */
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/* number_of_lanes is used for pixel clock adjust,
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* but it's not passed to asic_control.
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* We need to set number of lanes manually.
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*/
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dce60_configure_encoder(enc110, link_settings);
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cntl.action = TRANSMITTER_CONTROL_ENABLE;
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cntl.engine_id = ENGINE_ID_UNKNOWN;
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cntl.transmitter = enc110->base.transmitter;
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cntl.pll_id = clock_source;
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cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
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cntl.lanes_number = link_settings->lane_count;
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cntl.hpd_sel = enc110->base.hpd_source;
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cntl.pixel_clock = link_settings->link_rate
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* LINK_RATE_REF_FREQ_IN_KHZ;
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/* TODO: check if undefined works */
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cntl.color_depth = COLOR_DEPTH_UNDEFINED;
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result = link_transmitter_control(enc110, &cntl);
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if (result != BP_RESULT_OK) {
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DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
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__func__);
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BREAK_TO_DEBUGGER();
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}
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}
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#endif
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/*
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* @brief
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* Disable transmitter and its encoder
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@ -1208,6 +1385,63 @@ void dce110_link_encoder_dp_set_phy_pattern(
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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/* set DP PHY test and training patterns */
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void dce60_link_encoder_dp_set_phy_pattern(
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struct link_encoder *enc,
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const struct encoder_set_dp_phy_pattern_param *param)
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{
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struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
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switch (param->dp_phy_pattern) {
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case DP_TEST_PATTERN_TRAINING_PATTERN1:
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dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
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break;
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case DP_TEST_PATTERN_TRAINING_PATTERN2:
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dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
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break;
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case DP_TEST_PATTERN_TRAINING_PATTERN3:
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dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
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break;
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case DP_TEST_PATTERN_TRAINING_PATTERN4:
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dce110_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
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break;
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case DP_TEST_PATTERN_D102:
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set_dp_phy_pattern_d102(enc110);
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break;
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case DP_TEST_PATTERN_SYMBOL_ERROR:
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set_dp_phy_pattern_symbol_error(enc110);
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break;
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case DP_TEST_PATTERN_PRBS7:
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set_dp_phy_pattern_prbs7(enc110);
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break;
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case DP_TEST_PATTERN_80BIT_CUSTOM:
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set_dp_phy_pattern_80bit_custom(
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enc110, param->custom_pattern);
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break;
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case DP_TEST_PATTERN_CP2520_1:
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dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 1);
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break;
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case DP_TEST_PATTERN_CP2520_2:
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dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 2);
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break;
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case DP_TEST_PATTERN_CP2520_3:
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dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc110, 3);
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break;
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case DP_TEST_PATTERN_VIDEO_MODE: {
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dce60_set_dp_phy_pattern_passthrough_mode(
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enc110, param->dp_panel_mode);
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break;
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}
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default:
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/* invalid phy pattern */
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ASSERT_CRITICAL(false);
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break;
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}
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}
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#endif
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static void fill_stream_allocation_row_info(
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const struct link_mst_stream_allocation *stream_allocation,
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uint32_t *src,
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@ -1407,3 +1641,138 @@ void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
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*link_settings = max_link_cap;
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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static const struct link_encoder_funcs dce60_lnk_enc_funcs = {
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.validate_output_with_stream =
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dce110_link_encoder_validate_output_with_stream,
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.hw_init = dce110_link_encoder_hw_init,
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.setup = dce110_link_encoder_setup,
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.enable_tmds_output = dce110_link_encoder_enable_tmds_output,
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.enable_dp_output = dce60_link_encoder_enable_dp_output,
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.enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output,
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.enable_lvds_output = dce110_link_encoder_enable_lvds_output,
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.disable_output = dce110_link_encoder_disable_output,
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.dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
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.dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern,
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.update_mst_stream_allocation_table =
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dce110_link_encoder_update_mst_stream_allocation_table,
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.psr_program_dp_dphy_fast_training =
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dce110_psr_program_dp_dphy_fast_training,
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.psr_program_secondary_packet = dce110_psr_program_secondary_packet,
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.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
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.enable_hpd = dce110_link_encoder_enable_hpd,
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.disable_hpd = dce110_link_encoder_disable_hpd,
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.is_dig_enabled = dce110_is_dig_enabled,
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.destroy = dce110_link_encoder_destroy,
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.get_max_link_cap = dce110_link_encoder_get_max_link_cap
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};
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void dce60_link_encoder_construct(
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struct dce110_link_encoder *enc110,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dce110_link_enc_registers *link_regs,
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const struct dce110_link_enc_aux_registers *aux_regs,
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const struct dce110_link_enc_hpd_registers *hpd_regs)
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{
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struct bp_encoder_cap_info bp_cap_info = {0};
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const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
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enum bp_result result = BP_RESULT_OK;
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enc110->base.funcs = &dce60_lnk_enc_funcs;
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enc110->base.ctx = init_data->ctx;
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enc110->base.id = init_data->encoder;
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enc110->base.hpd_source = init_data->hpd_source;
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enc110->base.connector = init_data->connector;
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enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
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enc110->base.features = *enc_features;
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enc110->base.transmitter = init_data->transmitter;
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/* set the flag to indicate whether driver poll the I2C data pin
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* while doing the DP sink detect
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*/
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/* if (dal_adapter_service_is_feature_supported(as,
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FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
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enc110->base.features.flags.bits.
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DP_SINK_DETECT_POLL_DATA_PIN = true;*/
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enc110->base.output_signals =
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SIGNAL_TYPE_DVI_SINGLE_LINK |
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SIGNAL_TYPE_DVI_DUAL_LINK |
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SIGNAL_TYPE_LVDS |
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SIGNAL_TYPE_DISPLAY_PORT |
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SIGNAL_TYPE_DISPLAY_PORT_MST |
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SIGNAL_TYPE_EDP |
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SIGNAL_TYPE_HDMI_TYPE_A;
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/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
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* SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
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* SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
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* DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
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* Prefer DIG assignment is decided by board design.
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* For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
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* and VBIOS will filter out 7 UNIPHY for DCE 8.0.
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* By this, adding DIGG should not hurt DCE 8.0.
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* This will let DCE 8.1 share DCE 8.0 as much as possible
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*/
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enc110->link_regs = link_regs;
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enc110->aux_regs = aux_regs;
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enc110->hpd_regs = hpd_regs;
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switch (enc110->base.transmitter) {
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case TRANSMITTER_UNIPHY_A:
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enc110->base.preferred_engine = ENGINE_ID_DIGA;
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break;
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case TRANSMITTER_UNIPHY_B:
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enc110->base.preferred_engine = ENGINE_ID_DIGB;
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break;
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case TRANSMITTER_UNIPHY_C:
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enc110->base.preferred_engine = ENGINE_ID_DIGC;
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break;
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case TRANSMITTER_UNIPHY_D:
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enc110->base.preferred_engine = ENGINE_ID_DIGD;
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break;
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case TRANSMITTER_UNIPHY_E:
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enc110->base.preferred_engine = ENGINE_ID_DIGE;
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break;
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case TRANSMITTER_UNIPHY_F:
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enc110->base.preferred_engine = ENGINE_ID_DIGF;
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break;
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case TRANSMITTER_UNIPHY_G:
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enc110->base.preferred_engine = ENGINE_ID_DIGG;
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break;
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default:
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ASSERT_CRITICAL(false);
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enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
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}
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/* default to one to mirror Windows behavior */
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enc110->base.features.flags.bits.HDMI_6GB_EN = 1;
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result = bp_funcs->get_encoder_cap_info(enc110->base.ctx->dc_bios,
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enc110->base.id, &bp_cap_info);
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/* Override features with DCE-specific values */
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if (BP_RESULT_OK == result) {
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enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
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bp_cap_info.DP_HBR2_EN;
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enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
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bp_cap_info.DP_HBR3_EN;
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||||
enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
|
||||
} else {
|
||||
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
|
||||
__func__,
|
||||
result);
|
||||
}
|
||||
if (enc110->base.ctx->dc->debug.hdmi20_disable) {
|
||||
enc110->base.features.flags.bits.HDMI_6GB_EN = 0;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -75,6 +75,34 @@
|
||||
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
|
||||
SR(DCI_MEM_PWR_STATUS)
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_SI)
|
||||
#define LE_DCE60_REG_LIST(id)\
|
||||
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
|
||||
SR(DMCU_RAM_ACCESS_CTRL), \
|
||||
SR(DMCU_IRAM_RD_CTRL), \
|
||||
SR(DMCU_IRAM_RD_DATA), \
|
||||
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
|
||||
SRI(DIG_BE_CNTL, DIG, id), \
|
||||
SRI(DIG_BE_EN_CNTL, DIG, id), \
|
||||
SRI(DP_CONFIG, DP, id), \
|
||||
SRI(DP_DPHY_CNTL, DP, id), \
|
||||
SRI(DP_DPHY_PRBS_CNTL, DP, id), \
|
||||
SRI(DP_DPHY_SYM0, DP, id), \
|
||||
SRI(DP_DPHY_SYM1, DP, id), \
|
||||
SRI(DP_DPHY_SYM2, DP, id), \
|
||||
SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
|
||||
SRI(DP_LINK_CNTL, DP, id), \
|
||||
SRI(DP_LINK_FRAMING_CNTL, DP, id), \
|
||||
SRI(DP_MSE_SAT0, DP, id), \
|
||||
SRI(DP_MSE_SAT1, DP, id), \
|
||||
SRI(DP_MSE_SAT2, DP, id), \
|
||||
SRI(DP_MSE_SAT_UPDATE, DP, id), \
|
||||
SRI(DP_SEC_CNTL, DP, id), \
|
||||
SRI(DP_VID_STREAM_CNTL, DP, id), \
|
||||
SRI(DP_DPHY_FAST_TRAINING, DP, id), \
|
||||
SRI(DP_SEC_CNTL1, DP, id)
|
||||
#endif
|
||||
|
||||
#define LE_DCE80_REG_LIST(id)\
|
||||
SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
|
||||
LE_COMMON_REG_LIST_BASE(id)
|
||||
@ -169,6 +197,16 @@ void dce110_link_encoder_construct(
|
||||
const struct dce110_link_enc_aux_registers *aux_regs,
|
||||
const struct dce110_link_enc_hpd_registers *hpd_regs);
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_SI)
|
||||
void dce60_link_encoder_construct(
|
||||
struct dce110_link_encoder *enc110,
|
||||
const struct encoder_init_data *init_data,
|
||||
const struct encoder_feature_support *enc_features,
|
||||
const struct dce110_link_enc_registers *link_regs,
|
||||
const struct dce110_link_enc_aux_registers *aux_regs,
|
||||
const struct dce110_link_enc_hpd_registers *hpd_regs);
|
||||
#endif
|
||||
|
||||
bool dce110_link_encoder_validate_dvi_output(
|
||||
const struct dce110_link_encoder *enc110,
|
||||
enum signal_type connector_signal,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user