mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 19:57:38 +07:00
mtd: nand: denali: rework interrupt handling
Simplify the interrupt handling and fix issues:
- The register field view of INTR_EN / INTR_STATUS is different
among IP versions. The global macro DENALI_IRQ_ALL is hard-coded
for Intel platforms. The interrupt mask should be determined at
run-time depending on the running platform.
- wait_for_irq() loops do {} while() until interested flags are
asserted. The logic can be simplified.
- The spin_lock() guard seems too complex (and suspicious in a race
condition if wait_for_completion_timeout() bails out by timeout).
- denali->complete is reused again and again, but reinit_completion()
is missing. Add it.
Re-work the code to make it more robust and easier to handle.
While we are here, also rename the jump label "failed_req_irq" to
more appropriate "disable_irq".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Masahiro Yamada
Boris Brezillon
parent
1bb8866677
commit
c19e31d0a3
@ -30,27 +30,14 @@ MODULE_LICENSE("GPL");
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#define DENALI_NAND_NAME "denali-nand"
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/*
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* We define a macro here that combines all interrupts this driver uses into
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* a single constant value, for convenience.
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*/
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#define DENALI_IRQ_ALL (INTR__DMA_CMD_COMP | \
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INTR__ECC_TRANSACTION_DONE | \
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INTR__ECC_ERR | \
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INTR__PROGRAM_FAIL | \
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INTR__LOAD_COMP | \
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INTR__PROGRAM_COMP | \
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INTR__TIME_OUT | \
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INTR__ERASE_FAIL | \
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INTR__RST_COMP | \
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INTR__ERASE_COMP)
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/*
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* indicates whether or not the internal value for the flash bank is
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* valid or not
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*/
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#define CHIP_SELECT_INVALID -1
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#define DENALI_NR_BANKS 4
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/*
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* The bus interface clock, clk_x, is phase aligned with the core clock. The
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* clk_x is an integral multiple N of the core clk. The value N is configured
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@ -85,14 +72,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
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*/
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#define BANK(x) ((x) << 24)
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/* forward declarations */
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static void clear_interrupts(struct denali_nand_info *denali);
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static uint32_t wait_for_irq(struct denali_nand_info *denali,
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uint32_t irq_mask);
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static void denali_irq_enable(struct denali_nand_info *denali,
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uint32_t int_mask);
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static uint32_t read_interrupt_status(struct denali_nand_info *denali);
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/*
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* Certain operations for the denali NAND controller use an indexed mode to
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* read/write data. The operation is performed by writing the address value
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@ -143,22 +122,6 @@ static void read_status(struct denali_nand_info *denali)
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write_byte_to_buf(denali, 0);
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}
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/* resets a specific device connected to the core */
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static void reset_bank(struct denali_nand_info *denali)
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{
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uint32_t irq_status;
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uint32_t irq_mask = INTR__RST_COMP | INTR__TIME_OUT;
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clear_interrupts(denali);
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iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status & INTR__TIME_OUT)
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dev_err(denali->dev, "reset bank failed.\n");
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}
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/* Reset the flash controller */
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static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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{
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@ -201,169 +164,124 @@ static void detect_max_banks(struct denali_nand_info *denali)
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denali->max_banks <<= 1;
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}
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static void denali_set_intr_modes(struct denali_nand_info *denali,
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uint16_t INT_ENABLE)
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{
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if (INT_ENABLE)
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iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
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else
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iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
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}
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/*
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* validation function to verify that the controlling software is making
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* a valid request
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*/
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static inline bool is_flash_bank_valid(int flash_bank)
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{
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return flash_bank >= 0 && flash_bank < 4;
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}
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static void denali_irq_init(struct denali_nand_info *denali)
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{
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uint32_t int_mask;
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int i;
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/* Disable global interrupts */
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denali_set_intr_modes(denali, false);
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int_mask = DENALI_IRQ_ALL;
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/* Clear all status bits */
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for (i = 0; i < denali->max_banks; ++i)
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iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
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denali_irq_enable(denali, int_mask);
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}
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static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
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{
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denali_set_intr_modes(denali, false);
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}
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static void denali_irq_enable(struct denali_nand_info *denali,
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uint32_t int_mask)
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static void denali_enable_irq(struct denali_nand_info *denali)
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{
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int i;
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for (i = 0; i < denali->max_banks; ++i)
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iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
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for (i = 0; i < DENALI_NR_BANKS; i++)
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iowrite32(U32_MAX, denali->flash_reg + INTR_EN(i));
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iowrite32(GLOBAL_INT_EN_FLAG, denali->flash_reg + GLOBAL_INT_ENABLE);
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}
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/*
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* This function only returns when an interrupt that this driver cares about
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* occurs. This is to reduce the overhead of servicing interrupts
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*/
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static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
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static void denali_disable_irq(struct denali_nand_info *denali)
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{
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return read_interrupt_status(denali) & DENALI_IRQ_ALL;
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int i;
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for (i = 0; i < DENALI_NR_BANKS; i++)
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iowrite32(0, denali->flash_reg + INTR_EN(i));
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iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
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}
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/* Interrupts are cleared by writing a 1 to the appropriate status bit */
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static inline void clear_interrupt(struct denali_nand_info *denali,
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uint32_t irq_mask)
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static void denali_clear_irq(struct denali_nand_info *denali,
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int bank, uint32_t irq_status)
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{
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uint32_t intr_status_reg;
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intr_status_reg = INTR_STATUS(denali->flash_bank);
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iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
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/* write one to clear bits */
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iowrite32(irq_status, denali->flash_reg + INTR_STATUS(bank));
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}
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static void clear_interrupts(struct denali_nand_info *denali)
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static void denali_clear_irq_all(struct denali_nand_info *denali)
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{
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uint32_t status;
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int i;
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spin_lock_irq(&denali->irq_lock);
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status = read_interrupt_status(denali);
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clear_interrupt(denali, status);
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denali->irq_status = 0x0;
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spin_unlock_irq(&denali->irq_lock);
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for (i = 0; i < DENALI_NR_BANKS; i++)
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denali_clear_irq(denali, i, U32_MAX);
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}
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static uint32_t read_interrupt_status(struct denali_nand_info *denali)
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{
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uint32_t intr_status_reg;
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intr_status_reg = INTR_STATUS(denali->flash_bank);
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return ioread32(denali->flash_reg + intr_status_reg);
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}
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/*
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* This is the interrupt service routine. It handles all interrupts
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* sent to this device. Note that on CE4100, this is a shared interrupt.
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*/
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static irqreturn_t denali_isr(int irq, void *dev_id)
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{
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struct denali_nand_info *denali = dev_id;
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irqreturn_t ret = IRQ_NONE;
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uint32_t irq_status;
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irqreturn_t result = IRQ_NONE;
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int i;
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spin_lock(&denali->irq_lock);
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/* check to see if a valid NAND chip has been selected. */
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if (is_flash_bank_valid(denali->flash_bank)) {
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/*
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* check to see if controller generated the interrupt,
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* since this is a shared interrupt
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*/
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irq_status = denali_irq_detected(denali);
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if (irq_status != 0) {
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/* handle interrupt */
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/* first acknowledge it */
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clear_interrupt(denali, irq_status);
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/*
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* store the status in the device context for someone
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* to read
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*/
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denali->irq_status |= irq_status;
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/* notify anyone who cares that it happened */
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for (i = 0; i < DENALI_NR_BANKS; i++) {
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irq_status = ioread32(denali->flash_reg + INTR_STATUS(i));
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if (irq_status)
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ret = IRQ_HANDLED;
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denali_clear_irq(denali, i, irq_status);
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if (i != denali->flash_bank)
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continue;
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denali->irq_status |= irq_status;
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if (denali->irq_status & denali->irq_mask)
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complete(&denali->complete);
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/* tell the OS that we've handled this */
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result = IRQ_HANDLED;
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}
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}
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spin_unlock(&denali->irq_lock);
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return result;
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return ret;
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}
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static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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static void denali_reset_irq(struct denali_nand_info *denali)
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{
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unsigned long comp_res;
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uint32_t intr_status;
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unsigned long timeout = msecs_to_jiffies(1000);
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unsigned long flags;
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do {
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comp_res =
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wait_for_completion_timeout(&denali->complete, timeout);
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spin_lock_irq(&denali->irq_lock);
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intr_status = denali->irq_status;
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spin_lock_irqsave(&denali->irq_lock, flags);
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denali->irq_status = 0;
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denali->irq_mask = 0;
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spin_unlock_irqrestore(&denali->irq_lock, flags);
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}
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if (intr_status & irq_mask) {
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denali->irq_status &= ~irq_mask;
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spin_unlock_irq(&denali->irq_lock);
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/* our interrupt was detected */
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break;
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}
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static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
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uint32_t irq_mask)
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{
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unsigned long time_left, flags;
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uint32_t irq_status;
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/*
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* these are not the interrupts you are looking for -
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* need to wait again
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*/
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spin_unlock_irq(&denali->irq_lock);
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} while (comp_res != 0);
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spin_lock_irqsave(&denali->irq_lock, flags);
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if (comp_res == 0) {
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/* timeout */
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pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
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intr_status, irq_mask);
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irq_status = denali->irq_status;
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intr_status = 0;
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if (irq_mask & irq_status) {
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/* return immediately if the IRQ has already happened. */
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spin_unlock_irqrestore(&denali->irq_lock, flags);
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return irq_status;
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}
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return intr_status;
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denali->irq_mask = irq_mask;
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reinit_completion(&denali->complete);
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spin_unlock_irqrestore(&denali->irq_lock, flags);
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time_left = wait_for_completion_timeout(&denali->complete,
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msecs_to_jiffies(1000));
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if (!time_left) {
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dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
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denali->irq_mask);
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return 0;
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}
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return denali->irq_status;
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}
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/* resets a specific device connected to the core */
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static void reset_bank(struct denali_nand_info *denali)
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{
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uint32_t irq_status;
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denali_reset_irq(denali);
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iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
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irq_status = denali_wait_for_irq(denali,
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INTR__RST_COMP | INTR__TIME_OUT);
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if (!(irq_status & INTR__RST_COMP))
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dev_err(denali->dev, "reset bank failed.\n");
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}
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/*
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@ -397,7 +315,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
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clear_interrupts(denali);
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denali_reset_irq(denali);
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addr = BANK(denali->flash_bank) | denali->page;
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@ -479,9 +397,9 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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write_data_to_flash_mem(denali, buf, mtd->oobsize);
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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irq_status = denali_wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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if (!(irq_status & INTR__PROGRAM_COMP)) {
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dev_err(denali->dev, "OOB write failed\n");
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status = -EIO;
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}
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@ -510,9 +428,9 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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* can always use status0 bit as the
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* mask is identical for each bank.
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*/
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irq_status = wait_for_irq(denali, irq_mask);
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irq_status = denali_wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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if (!(irq_status & INTR__LOAD_COMP))
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dev_err(denali->dev, "page on OOB timeout %d\n",
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denali->page);
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@ -620,9 +538,9 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd,
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unsigned int err_byte, err_sector, err_device;
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uint8_t err_cor_value;
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unsigned int prev_sector = 0;
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uint32_t irq_status;
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/* read the ECC errors. we'll ignore them for now */
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denali_set_intr_modes(denali, false);
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denali_reset_irq(denali);
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do {
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err_addr = ioread32(denali->flash_reg + ECC_ERROR_ADDRESS);
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@ -674,10 +592,9 @@ static int denali_sw_ecc_fixup(struct mtd_info *mtd,
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* ECC_TRANSACTION_DONE interrupt, so here just wait for
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* a while for this interrupt
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*/
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while (!(read_interrupt_status(denali) & INTR__ECC_TRANSACTION_DONE))
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cpu_relax();
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clear_interrupts(denali);
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denali_set_intr_modes(denali, true);
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irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
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if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
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return -EIO;
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return max_bitflips;
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}
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@ -778,15 +695,14 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
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dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
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clear_interrupts(denali);
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denali_reset_irq(denali);
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denali_enable_dma(denali, true);
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denali_setup_dma(denali, DENALI_WRITE);
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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irq_status = denali_wait_for_irq(denali, irq_mask);
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if (!(irq_status & INTR__DMA_CMD_COMP)) {
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dev_err(denali->dev, "timeout on write_page (type = %d)\n",
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raw_xfer);
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ret = -EIO;
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@ -865,11 +781,11 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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denali_enable_dma(denali, true);
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dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
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clear_interrupts(denali);
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denali_reset_irq(denali);
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denali_setup_dma(denali, DENALI_READ);
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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irq_status = denali_wait_for_irq(denali, irq_mask);
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dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
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@ -901,6 +817,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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dma_addr_t addr = denali->buf.dma_buf;
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size_t size = mtd->writesize + mtd->oobsize;
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uint32_t irq_mask = INTR__DMA_CMD_COMP;
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uint32_t irq_status;
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denali->page = page;
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@ -909,11 +826,13 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
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clear_interrupts(denali);
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denali_reset_irq(denali);
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denali_setup_dma(denali, DENALI_READ);
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/* wait for operation to complete */
|
||||
wait_for_irq(denali, irq_mask);
|
||||
irq_status = denali_wait_for_irq(denali, irq_mask);
|
||||
if (irq_status & INTR__DMA_CMD_COMP)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
|
||||
|
||||
@ -940,9 +859,7 @@ static void denali_select_chip(struct mtd_info *mtd, int chip)
|
||||
{
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
|
||||
spin_lock_irq(&denali->irq_lock);
|
||||
denali->flash_bank = chip;
|
||||
spin_unlock_irq(&denali->irq_lock);
|
||||
}
|
||||
|
||||
static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
|
||||
@ -953,19 +870,19 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
|
||||
static int denali_erase(struct mtd_info *mtd, int page)
|
||||
{
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
|
||||
uint32_t cmd, irq_status;
|
||||
|
||||
clear_interrupts(denali);
|
||||
denali_reset_irq(denali);
|
||||
|
||||
/* setup page read request for access type */
|
||||
cmd = MODE_10 | BANK(denali->flash_bank) | page;
|
||||
index_addr(denali, cmd, 0x1);
|
||||
|
||||
/* wait for erase to complete or failure to occur */
|
||||
irq_status = wait_for_irq(denali, INTR__ERASE_COMP | INTR__ERASE_FAIL);
|
||||
irq_status = denali_wait_for_irq(denali,
|
||||
INTR__ERASE_COMP | INTR__ERASE_FAIL);
|
||||
|
||||
return irq_status & INTR__ERASE_FAIL ? NAND_STATUS_FAIL : PASS;
|
||||
return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
|
||||
}
|
||||
|
||||
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
|
||||
@ -1152,7 +1069,6 @@ static void denali_hw_init(struct denali_nand_info *denali)
|
||||
/* Should set value for these registers when init */
|
||||
iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
|
||||
iowrite32(1, denali->flash_reg + ECC_ENABLE);
|
||||
denali_irq_init(denali);
|
||||
}
|
||||
|
||||
int denali_calc_ecc_bytes(int step_size, int strength)
|
||||
@ -1264,9 +1180,6 @@ static void denali_drv_init(struct denali_nand_info *denali)
|
||||
|
||||
/* indicate that MTD has not selected a valid bank yet */
|
||||
denali->flash_bank = CHIP_SELECT_INVALID;
|
||||
|
||||
/* initialize our irq_status variable to indicate no interrupts */
|
||||
denali->irq_status = 0;
|
||||
}
|
||||
|
||||
static int denali_multidev_fixup(struct denali_nand_info *denali)
|
||||
@ -1336,6 +1249,8 @@ int denali_init(struct denali_nand_info *denali)
|
||||
denali_hw_init(denali);
|
||||
denali_drv_init(denali);
|
||||
|
||||
denali_clear_irq_all(denali);
|
||||
|
||||
/* Request IRQ after all the hardware initialization is finished */
|
||||
ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
|
||||
IRQF_SHARED, DENALI_NAND_NAME, denali);
|
||||
@ -1344,8 +1259,8 @@ int denali_init(struct denali_nand_info *denali)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* now that our ISR is registered, we can enable interrupts */
|
||||
denali_set_intr_modes(denali, true);
|
||||
denali_enable_irq(denali);
|
||||
|
||||
nand_set_flash_node(chip, denali->dev->of_node);
|
||||
/* Fallback to the default name if DT did not give "label" property */
|
||||
if (!mtd->name)
|
||||
@ -1370,7 +1285,7 @@ int denali_init(struct denali_nand_info *denali)
|
||||
*/
|
||||
ret = nand_scan_ident(mtd, denali->max_banks, NULL);
|
||||
if (ret)
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
|
||||
/* allocate the right size buffer now */
|
||||
devm_kfree(denali->dev, denali->buf.buf);
|
||||
@ -1379,7 +1294,7 @@ int denali_init(struct denali_nand_info *denali)
|
||||
GFP_KERNEL);
|
||||
if (!denali->buf.buf) {
|
||||
ret = -ENOMEM;
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
}
|
||||
|
||||
ret = dma_set_mask(denali->dev,
|
||||
@ -1387,7 +1302,7 @@ int denali_init(struct denali_nand_info *denali)
|
||||
64 : 32));
|
||||
if (ret) {
|
||||
dev_err(denali->dev, "No usable DMA configuration\n");
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
}
|
||||
|
||||
denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
|
||||
@ -1396,7 +1311,7 @@ int denali_init(struct denali_nand_info *denali)
|
||||
if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
|
||||
dev_err(denali->dev, "Failed to map DMA buffer\n");
|
||||
ret = -EIO;
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1420,7 +1335,7 @@ int denali_init(struct denali_nand_info *denali)
|
||||
ret = denali_ecc_setup(mtd, chip, denali);
|
||||
if (ret) {
|
||||
dev_err(denali->dev, "Failed to setup ECC settings.\n");
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
}
|
||||
|
||||
dev_dbg(denali->dev,
|
||||
@ -1454,21 +1369,21 @@ int denali_init(struct denali_nand_info *denali)
|
||||
|
||||
ret = denali_multidev_fixup(denali);
|
||||
if (ret)
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret)
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
|
||||
ret = mtd_device_register(mtd, NULL, 0);
|
||||
if (ret) {
|
||||
dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
|
||||
goto failed_req_irq;
|
||||
goto disable_irq;
|
||||
}
|
||||
return 0;
|
||||
|
||||
failed_req_irq:
|
||||
denali_irq_cleanup(denali->irq, denali);
|
||||
disable_irq:
|
||||
denali_disable_irq(denali);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1486,7 +1401,7 @@ void denali_remove(struct denali_nand_info *denali)
|
||||
int bufsize = mtd->writesize + mtd->oobsize;
|
||||
|
||||
nand_release(mtd);
|
||||
denali_irq_cleanup(denali->irq, denali);
|
||||
denali_disable_irq(denali);
|
||||
dma_unmap_single(denali->dev, denali->buf.dma_buf, bufsize,
|
||||
DMA_BIDIRECTIONAL);
|
||||
}
|
||||
|
||||
@ -325,6 +325,7 @@ struct denali_nand_info {
|
||||
/* elements used by ISR */
|
||||
struct completion complete;
|
||||
spinlock_t irq_lock;
|
||||
uint32_t irq_mask;
|
||||
uint32_t irq_status;
|
||||
int irq;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user