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drivers/net: support hdlc function for QE-UCC
The driver add hdlc support for Freescale QUICC Engine. It support NMSI and TSA mode. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Zhao Qiang
David S. Miller
parent
35ef1c20fd
commit
c19b6d246a
@ -4870,6 +4870,13 @@ F: drivers/net/ethernet/freescale/gianfar*
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X: drivers/net/ethernet/freescale/gianfar_ptp.c
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F: Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
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FREESCALE QUICC ENGINE UCC HDLC DRIVER
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M: Zhao Qiang <qiang.zhao@nxp.com>
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L: netdev@vger.kernel.org
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L: linuxppc-dev@lists.ozlabs.org
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S: Maintained
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F: drivers/net/wan/fsl_ucc_hdlc*
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FREESCALE QUICC ENGINE UCC UART DRIVER
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M: Timur Tabi <timur@tabi.org>
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L: linuxppc-dev@lists.ozlabs.org
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@ -280,6 +280,17 @@ config DSCC4
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To compile this driver as a module, choose M here: the
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module will be called dscc4.
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config FSL_UCC_HDLC
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tristate "Freescale QUICC Engine HDLC support"
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depends on HDLC
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depends on QUICC_ENGINE
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help
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Driver for Freescale QUICC Engine HDLC controller. The driver
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supports HDLC in NMSI and TDM mode.
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To compile this driver as a module, choose M here: the
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module will be called fsl_ucc_hdlc.
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config DSCC4_PCISYNC
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bool "Etinc PCISYNC features"
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depends on DSCC4
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@ -32,6 +32,7 @@ obj-$(CONFIG_WANXL) += wanxl.o
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obj-$(CONFIG_PCI200SYN) += pci200syn.o
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obj-$(CONFIG_PC300TOO) += pc300too.o
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obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
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obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o
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clean-files := wanxlfw.inc
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$(obj)/wanxl.o: $(obj)/wanxlfw.inc
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1192
drivers/net/wan/fsl_ucc_hdlc.c
Normal file
1192
drivers/net/wan/fsl_ucc_hdlc.c
Normal file
File diff suppressed because it is too large
Load Diff
147
drivers/net/wan/fsl_ucc_hdlc.h
Normal file
147
drivers/net/wan/fsl_ucc_hdlc.h
Normal file
@ -0,0 +1,147 @@
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/* Freescale QUICC Engine HDLC Device Driver
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef CONFIG_UCC_HDLC_H
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#define CONFIG_UCC_HDLC_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/ucc.h>
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#include <soc/fsl/qe/ucc_fast.h>
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/* UCC HDLC event register */
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#define UCCE_HDLC_RX_EVENTS \
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(UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
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#define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
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struct ucc_hdlc_param {
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__be16 riptr;
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__be16 tiptr;
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__be16 res0;
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__be16 mrblr;
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__be32 rstate;
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__be32 rbase;
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__be16 rbdstat;
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__be16 rbdlen;
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__be32 rdptr;
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__be32 tstate;
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__be32 tbase;
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__be16 tbdstat;
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__be16 tbdlen;
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__be32 tdptr;
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__be32 rbptr;
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__be32 tbptr;
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__be32 rcrc;
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__be32 res1;
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__be32 tcrc;
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__be32 res2;
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__be32 res3;
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__be32 c_mask;
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__be32 c_pres;
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__be16 disfc;
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__be16 crcec;
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__be16 abtsc;
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__be16 nmarc;
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__be32 max_cnt;
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__be16 mflr;
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__be16 rfthr;
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__be16 rfcnt;
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__be16 hmask;
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__be16 haddr1;
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__be16 haddr2;
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__be16 haddr3;
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__be16 haddr4;
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__be16 ts_tmp;
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__be16 tmp_mb;
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};
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struct ucc_hdlc_private {
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struct ucc_tdm *utdm;
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struct ucc_tdm_info *ut_info;
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struct ucc_fast_private *uccf;
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struct device *dev;
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struct net_device *ndev;
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struct napi_struct napi;
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struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */
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struct ucc_hdlc_param __iomem *ucc_pram;
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u16 tsa;
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bool hdlc_busy;
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bool loopback;
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u8 *tx_buffer;
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u8 *rx_buffer;
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dma_addr_t dma_tx_addr;
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dma_addr_t dma_rx_addr;
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struct qe_bd *tx_bd_base;
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struct qe_bd *rx_bd_base;
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dma_addr_t dma_tx_bd;
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dma_addr_t dma_rx_bd;
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struct qe_bd *curtx_bd;
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struct qe_bd *currx_bd;
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struct qe_bd *dirty_tx;
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u16 currx_bdnum;
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struct sk_buff **tx_skbuff;
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struct sk_buff **rx_skbuff;
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u16 skb_curtx;
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u16 skb_currx;
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unsigned short skb_dirtytx;
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unsigned short tx_ring_size;
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unsigned short rx_ring_size;
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u32 ucc_pram_offset;
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unsigned short encoding;
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unsigned short parity;
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u32 clocking;
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spinlock_t lock; /* lock for Tx BD and Tx buffer */
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#ifdef CONFIG_PM
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struct ucc_hdlc_param *ucc_pram_bak;
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u32 gumr;
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u8 guemr;
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u32 cmxsi1cr_l, cmxsi1cr_h;
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u32 cmxsi1syr;
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u32 cmxucr[4];
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#endif
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};
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#define TX_BD_RING_LEN 0x10
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#define RX_BD_RING_LEN 0x20
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#define RX_CLEAN_MAX 0x10
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#define NUM_OF_BUF 4
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#define MAX_RX_BUF_LENGTH (48 * 0x20)
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#define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
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#define ALIGNMENT_OF_UCC_HDLC_PRAM 64
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#define SI_BANK_SIZE 128
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#define MAX_HDLC_NUM 4
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#define HDLC_HEAD_LEN 2
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#define HDLC_CRC_SIZE 2
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#define TX_RING_MOD_MASK(size) (size - 1)
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#define RX_RING_MOD_MASK(size) (size - 1)
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#define HDLC_HEAD_MASK 0x0000
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#define DEFAULT_HDLC_HEAD 0xff44
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#define DEFAULT_ADDR_MASK 0x00ff
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#define DEFAULT_HDLC_ADDR 0x00ff
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#define BMR_GBL 0x20000000
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#define BMR_BIG_ENDIAN 0x10000000
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#define CRC_16BIT_MASK 0x0000F0B8
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#define CRC_16BIT_PRES 0x0000FFFF
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#define DEFAULT_RFTHR 1
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#define DEFAULT_PPP_HEAD 0xff03
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#endif
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@ -657,6 +657,7 @@ struct ucc_slow_pram {
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#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
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/* General UCC FAST Mode Register */
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#define UCC_FAST_GUMR_LOOPBACK 0x40000000
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#define UCC_FAST_GUMR_TCI 0x20000000
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#define UCC_FAST_GUMR_TRX 0x10000000
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#define UCC_FAST_GUMR_TTX 0x08000000
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@ -21,19 +21,37 @@
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#include <soc/fsl/qe/ucc.h>
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/* Receive BD's status */
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/* Receive BD's status and length*/
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#define R_E 0x80000000 /* buffer empty */
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#define R_W 0x20000000 /* wrap bit */
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#define R_I 0x10000000 /* interrupt on reception */
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#define R_L 0x08000000 /* last */
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#define R_F 0x04000000 /* first */
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/* transmit BD's status */
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/* transmit BD's status and length*/
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#define T_R 0x80000000 /* ready bit */
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#define T_W 0x20000000 /* wrap bit */
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#define T_I 0x10000000 /* interrupt on completion */
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#define T_L 0x08000000 /* last */
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/* Receive BD's status */
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#define R_E_S 0x8000 /* buffer empty */
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#define R_W_S 0x2000 /* wrap bit */
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#define R_I_S 0x1000 /* interrupt on reception */
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#define R_L_S 0x0800 /* last */
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#define R_F_S 0x0400 /* first */
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#define R_CM_S 0x0200 /* continuous mode */
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#define R_CR_S 0x0004 /* crc */
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#define R_OV_S 0x0002 /* crc */
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/* transmit BD's status */
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#define T_R_S 0x8000 /* ready bit */
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#define T_W_S 0x2000 /* wrap bit */
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#define T_I_S 0x1000 /* interrupt on completion */
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#define T_L_S 0x0800 /* last */
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#define T_TC_S 0x0400 /* crc */
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#define T_TM_S 0x0200 /* continuous mode */
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/* Rx Data buffer must be 4 bytes aligned in most cases */
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#define UCC_FAST_RX_ALIGN 4
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#define UCC_FAST_MRBLR_ALIGNMENT 4
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