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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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KVM: x86 emulator: streamline decode of segment registers
The opcodes push %seg pop %seg l%seg, %mem, %reg (e.g. lds/les/lss/lfs/lgs) all have an segment register encoded in the instruction. To allow reuse, decode the segment number into src2 during the decode stage instead of the execution stage. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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Avi Kivity
parent
41ddf9784c
commit
c191a7a0f4
@ -51,6 +51,12 @@
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#define OpImmFAddr 17ull /* Immediate far address */
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#define OpMemFAddr 18ull /* Far address in memory */
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#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
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#define OpES 20ull /* ES */
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#define OpCS 21ull /* CS */
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#define OpSS 22ull /* SS */
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#define OpDS 23ull /* DS */
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#define OpFS 24ull /* FS */
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#define OpGS 25ull /* GS */
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#define OpBits 5 /* Width of operand field */
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#define OpMask ((1ull << OpBits) - 1)
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@ -126,6 +132,12 @@
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#define Src2ImmByte (OpImmByte << Src2Shift)
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#define Src2One (OpOne << Src2Shift)
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#define Src2Imm (OpImm << Src2Shift)
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#define Src2ES (OpES << Src2Shift)
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#define Src2CS (OpCS << Src2Shift)
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#define Src2SS (OpSS << Src2Shift)
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#define Src2DS (OpDS << Src2Shift)
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#define Src2FS (OpFS << Src2Shift)
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#define Src2GS (OpGS << Src2Shift)
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#define Src2Mask (OpMask << Src2Shift)
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#define X2(x...) x, x
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@ -3101,16 +3113,19 @@ static struct gprefix pfx_0f_6f_0f_7f = {
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static struct opcode opcode_table[256] = {
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/* 0x00 - 0x07 */
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I6ALU(Lock, em_add),
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D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
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D(ImplicitOps | Stack | No64 | Src2ES),
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D(ImplicitOps | Stack | No64 | Src2ES),
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/* 0x08 - 0x0F */
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I6ALU(Lock, em_or),
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D(ImplicitOps | Stack | No64), N,
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D(ImplicitOps | Stack | No64 | Src2CS), N,
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/* 0x10 - 0x17 */
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I6ALU(Lock, em_adc),
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D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
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D(ImplicitOps | Stack | No64 | Src2SS),
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D(ImplicitOps | Stack | No64 | Src2SS),
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/* 0x18 - 0x1F */
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I6ALU(Lock, em_sbb),
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D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
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D(ImplicitOps | Stack | No64 | Src2DS),
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D(ImplicitOps | Stack | No64 | Src2DS),
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/* 0x20 - 0x27 */
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I6ALU(Lock, em_and), N, N,
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/* 0x28 - 0x2F */
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@ -3178,7 +3193,8 @@ static struct opcode opcode_table[256] = {
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D2bv(DstMem | SrcImmByte | ModRM),
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I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
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I(ImplicitOps | Stack, em_ret),
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D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
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D(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES),
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D(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS),
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G(ByteOp, group11), G(0, group11),
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/* 0xC8 - 0xCF */
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N, N, N, I(ImplicitOps | Stack, em_ret_far),
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@ -3253,20 +3269,22 @@ static struct opcode twobyte_table[256] = {
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/* 0x90 - 0x9F */
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X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
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/* 0xA0 - 0xA7 */
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D(ImplicitOps | Stack), D(ImplicitOps | Stack),
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D(Stack | Src2FS), D(Stack | Src2FS),
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DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
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D(DstMem | SrcReg | Src2ImmByte | ModRM),
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D(DstMem | SrcReg | Src2CL | ModRM), N, N,
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/* 0xA8 - 0xAF */
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D(ImplicitOps | Stack), D(ImplicitOps | Stack),
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D(Stack | Src2GS), D(Stack | Src2GS),
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DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
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D(DstMem | SrcReg | Src2ImmByte | ModRM),
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D(DstMem | SrcReg | Src2CL | ModRM),
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D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
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/* 0xB0 - 0xB7 */
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D2bv(DstMem | SrcReg | ModRM | Lock),
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D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
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D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
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D(DstReg | SrcMemFAddr | ModRM | Src2SS),
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D(DstMem | SrcReg | ModRM | BitOp | Lock),
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D(DstReg | SrcMemFAddr | ModRM | Src2FS),
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D(DstReg | SrcMemFAddr | ModRM | Src2GS),
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D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
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/* 0xB8 - 0xBF */
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N, N,
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@ -3436,6 +3454,24 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
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case OpMemFAddr:
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ctxt->memop.bytes = ctxt->op_bytes + 2;
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goto mem_common;
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case OpES:
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op->val = VCPU_SREG_ES;
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break;
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case OpCS:
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op->val = VCPU_SREG_CS;
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break;
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case OpSS:
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op->val = VCPU_SREG_SS;
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break;
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case OpDS:
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op->val = VCPU_SREG_DS;
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break;
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case OpFS:
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op->val = VCPU_SREG_FS;
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break;
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case OpGS:
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op->val = VCPU_SREG_GS;
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break;
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case OpImplicit:
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/* Special instructions do their own operand decoding. */
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default:
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@ -3803,26 +3839,15 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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switch (ctxt->b) {
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case 0x06: /* push es */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
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case 0x0e: /* push cs */
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case 0x16: /* push ss */
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case 0x1e: /* push ds */
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rc = emulate_push_sreg(ctxt, ctxt->src2.val);
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break;
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case 0x07: /* pop es */
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rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
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break;
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case 0x0e: /* push cs */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
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break;
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case 0x16: /* push ss */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
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break;
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case 0x17: /* pop ss */
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rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
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break;
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case 0x1e: /* push ds */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
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break;
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case 0x1f: /* pop ds */
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rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
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break;
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rc = emulate_pop_sreg(ctxt, ctxt->src2.val);
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case 0x40 ... 0x47: /* inc r16/r32 */
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emulate_1op(ctxt, "inc");
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break;
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@ -3869,10 +3894,8 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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rc = em_grp2(ctxt);
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break;
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case 0xc4: /* les */
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rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
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break;
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case 0xc5: /* lds */
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rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
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rc = emulate_load_segment(ctxt, ctxt->src2.val);
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break;
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case 0xcc: /* int3 */
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rc = emulate_int(ctxt, 3);
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@ -4078,10 +4101,12 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
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break;
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case 0xa0: /* push fs */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
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case 0xa8: /* push gs */
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rc = emulate_push_sreg(ctxt, ctxt->src2.val);
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break;
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case 0xa1: /* pop fs */
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rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
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case 0xa9: /* pop gs */
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rc = emulate_pop_sreg(ctxt, ctxt->src2.val);
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break;
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case 0xa3:
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bt: /* bt */
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@ -4094,12 +4119,6 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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case 0xa5: /* shld cl, r, r/m */
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emulate_2op_cl(ctxt, "shld");
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break;
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case 0xa8: /* push gs */
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rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
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break;
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case 0xa9: /* pop gs */
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rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
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break;
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case 0xab:
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bts: /* bts */
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emulate_2op_SrcV_nobyte(ctxt, "bts");
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@ -4128,18 +4147,14 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
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}
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break;
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case 0xb2: /* lss */
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rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
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case 0xb4: /* lfs */
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case 0xb5: /* lgs */
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rc = emulate_load_segment(ctxt, ctxt->src2.val);
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break;
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case 0xb3:
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btr: /* btr */
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emulate_2op_SrcV_nobyte(ctxt, "btr");
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break;
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case 0xb4: /* lfs */
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rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
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break;
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case 0xb5: /* lgs */
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rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
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break;
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case 0xb6 ... 0xb7: /* movzx */
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ctxt->dst.bytes = ctxt->op_bytes;
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ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
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