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drm/amd/display: only include FEC overhead if both asic and display support FEC

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[why]
Some asics don't support FEC but FEC overhead is added into link
bandwidth calculation by mistake. This causes certain timing cannot be
validated.

[how]
Only include FEC overhead if both asic and display support FEC.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu 2020-02-11 15:33:38 -05:00 committed by Alex Deucher
parent e625c1eae2
commit c14b726ee0
6 changed files with 18 additions and 5 deletions
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11
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -3406,7 +3406,7 @@ uint32_t dc_link_bandwidth_kbps(
link_bw_kbps *= 8; /* 8 bits per byte*/
link_bw_kbps *= link_setting->lane_count;
if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
if (dc_link_is_fec_supported(link)) {
/* Account for FEC overhead.
* We have to do it based on caps,
* and not based on FEC being set ready,
@ -3450,3 +3450,12 @@ void dc_link_overwrite_extended_receiver_cap(
dp_overwrite_extended_receiver_cap(link);
}
bool dc_link_is_fec_supported(const struct dc_link *link)
{
return (dc_is_dp_signal(link->connector_signal) &&
link->link_enc->features.fec_supported &&
link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
!link->dc->debug.disable_fec &&
!IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
}

6
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -4126,8 +4126,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
struct link_encoder *link_enc = link->link_enc;
uint8_t fec_config = 0;
if (link->dc->debug.disable_fec ||
IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
if (!dc_link_is_fec_supported(link))
return;
if (link_enc->funcs->fec_set_ready &&
@ -4162,8 +4161,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
{
struct link_encoder *link_enc = link->link_enc;
if (link->dc->debug.disable_fec ||
IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
if (!dc_link_is_fec_supported(link))
return;
if (link_enc->funcs->fec_set_enable &&

3
drivers/gpu/drm/amd/display/dc/dc_link.h
View File

@ -333,4 +333,7 @@ bool dc_submit_i2c_oem(
uint32_t dc_bandwidth_in_kbps_from_timing(
const struct dc_crtc_timing *timing);
bool dc_link_is_fec_supported(const struct dc_link *link);
#endif /* DC_LINK_H_ */

1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -1143,6 +1143,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_pixel_clock = 600000,
.hdmi_ycbcr420_supported = true,
.dp_ycbcr420_supported = true,
.fec_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,

1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
View File

@ -1589,6 +1589,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_pixel_clock = 600000,
.hdmi_ycbcr420_supported = true,
.dp_ycbcr420_supported = true,
.fec_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,

1
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View File

@ -68,6 +68,7 @@ struct encoder_feature_support {
unsigned int max_hdmi_pixel_clock;
bool hdmi_ycbcr420_supported;
bool dp_ycbcr420_supported;
bool fec_supported;
};
union dpcd_psr_configuration {