mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 20:56:41 +07:00
drm/radeon: add initial support for R6xx/R7xx GPUs
This adds support for 2D/Xv acceleration in the X.org 2D driver, to the drm. It doesn't yet provide any 3D support hooks. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
80b3334a4d
commit
c05ce0834a
@ -3,7 +3,7 @@
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# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
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ccflags-y := -Iinclude/drm
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o r600_cp.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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2247
drivers/gpu/drm/radeon/r600_cp.c
Normal file
2247
drivers/gpu/drm/radeon/r600_cp.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -43,7 +43,7 @@
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static int radeon_do_cleanup_cp(struct drm_device * dev);
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static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
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static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
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u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
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{
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u32 val;
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@ -62,11 +62,15 @@ u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
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{
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if (dev_priv->writeback_works)
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return radeon_read_ring_rptr(dev_priv, 0);
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else
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return RADEON_READ(RADEON_CP_RB_RPTR);
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else {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return RADEON_READ(R600_CP_RB_RPTR);
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else
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return RADEON_READ(RADEON_CP_RB_RPTR);
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}
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}
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static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
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void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
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{
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if (dev_priv->flags & RADEON_IS_AGP)
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DRM_WRITE32(dev_priv->ring_rptr, off, val);
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@ -82,11 +86,19 @@ void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
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u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
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{
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if (dev_priv->writeback_works)
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return radeon_read_ring_rptr(dev_priv,
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RADEON_SCRATCHOFF(index));
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else
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return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
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if (dev_priv->writeback_works) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return radeon_read_ring_rptr(dev_priv,
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R600_SCRATCHOFF(index));
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else
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return radeon_read_ring_rptr(dev_priv,
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RADEON_SCRATCHOFF(index));
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} else {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
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else
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return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
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}
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}
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u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
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@ -142,7 +154,11 @@ static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
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return RADEON_READ(R700_MC_VM_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return RADEON_READ(R600_MC_VM_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
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else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
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@ -155,7 +171,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
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RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
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else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
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@ -166,9 +186,16 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
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}
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static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
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void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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/*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
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RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
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RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
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} else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
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RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
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RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
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} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
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else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
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@ -179,12 +206,18 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
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RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
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}
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static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
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void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
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{
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u32 agp_base_hi = upper_32_bits(agp_base);
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u32 agp_base_lo = agp_base & 0xffffffff;
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u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
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/* R6xx/R7xx must be aligned to a 4MB boundry */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
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RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
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R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
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R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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@ -205,7 +238,7 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
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}
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}
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static void radeon_enable_bm(struct drm_radeon_private *dev_priv)
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void radeon_enable_bm(struct drm_radeon_private *dev_priv)
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{
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u32 tmp;
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/* Turn on bus mastering */
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@ -1440,6 +1473,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri
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int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_init_t *init = data;
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LOCK_TEST_WITH_RETURN(dev, file_priv);
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@ -1452,8 +1486,13 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
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case RADEON_INIT_R200_CP:
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case RADEON_INIT_R300_CP:
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return radeon_do_init_cp(dev, init, file_priv);
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case RADEON_INIT_R600_CP:
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return r600_do_init_cp(dev, init, file_priv);
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case RADEON_CLEANUP_CP:
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return radeon_do_cleanup_cp(dev);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return r600_do_cleanup_cp(dev);
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else
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return radeon_do_cleanup_cp(dev);
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}
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return -EINVAL;
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@ -1476,7 +1515,10 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
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return 0;
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}
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radeon_do_cp_start(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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r600_do_cp_start(dev_priv);
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else
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radeon_do_cp_start(dev_priv);
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return 0;
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}
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@ -1507,7 +1549,10 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
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* code so that the DRM ioctl wrapper can try again.
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*/
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if (stop->idle) {
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ret = radeon_do_cp_idle(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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ret = r600_do_cp_idle(dev_priv);
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else
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ret = radeon_do_cp_idle(dev_priv);
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if (ret)
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return ret;
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}
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@ -1516,10 +1561,16 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
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* we will get some dropped triangles as they won't be fully
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* rendered before the CP is shut down.
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*/
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radeon_do_cp_stop(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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r600_do_cp_stop(dev_priv);
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else
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radeon_do_cp_stop(dev_priv);
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/* Reset the engine */
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radeon_do_engine_reset(dev);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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r600_do_engine_reset(dev);
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else
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radeon_do_engine_reset(dev);
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return 0;
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}
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@ -1532,29 +1583,47 @@ void radeon_do_release(struct drm_device * dev)
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if (dev_priv) {
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if (dev_priv->cp_running) {
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/* Stop the cp */
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while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
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DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
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while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
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DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
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#ifdef __linux__
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schedule();
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schedule();
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#else
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tsleep(&ret, PZERO, "rdnrel", 1);
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tsleep(&ret, PZERO, "rdnrel", 1);
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#endif
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}
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} else {
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while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
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DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
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#ifdef __linux__
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schedule();
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#else
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tsleep(&ret, PZERO, "rdnrel", 1);
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#endif
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}
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}
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
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r600_do_cp_stop(dev_priv);
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r600_do_engine_reset(dev);
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} else {
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radeon_do_cp_stop(dev_priv);
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radeon_do_engine_reset(dev);
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}
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radeon_do_cp_stop(dev_priv);
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radeon_do_engine_reset(dev);
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}
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/* Disable *all* interrupts */
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if (dev_priv->mmio) /* remove this after permanent addmaps */
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
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/* Disable *all* interrupts */
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if (dev_priv->mmio) /* remove this after permanent addmaps */
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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if (dev_priv->mmio) { /* remove all surfaces */
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for (i = 0; i < RADEON_MAX_SURFACES; i++) {
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RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
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RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
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16 * i, 0);
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RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
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16 * i, 0);
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if (dev_priv->mmio) { /* remove all surfaces */
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for (i = 0; i < RADEON_MAX_SURFACES; i++) {
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RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
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RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
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16 * i, 0);
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RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
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16 * i, 0);
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}
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}
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}
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@ -1563,7 +1632,10 @@ void radeon_do_release(struct drm_device * dev)
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radeon_mem_takedown(&(dev_priv->fb_heap));
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/* deallocate kernel resources */
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radeon_do_cleanup_cp(dev);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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r600_do_cleanup_cp(dev);
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else
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radeon_do_cleanup_cp(dev);
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}
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}
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@ -1581,7 +1653,10 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
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return -EINVAL;
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}
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radeon_do_cp_reset(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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r600_do_cp_reset(dev_priv);
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else
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radeon_do_cp_reset(dev_priv);
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/* The CP is no longer running after an engine reset */
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dev_priv->cp_running = 0;
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@ -1596,23 +1671,36 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
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LOCK_TEST_WITH_RETURN(dev, file_priv);
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return radeon_do_cp_idle(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return r600_do_cp_idle(dev_priv);
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else
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return radeon_do_cp_idle(dev_priv);
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}
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/* Added by Charl P. Botha to call radeon_do_resume_cp().
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*/
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int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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return radeon_do_resume_cp(dev, file_priv);
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drm_radeon_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return r600_do_resume_cp(dev, file_priv);
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else
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return radeon_do_resume_cp(dev, file_priv);
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}
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int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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LOCK_TEST_WITH_RETURN(dev, file_priv);
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return radeon_do_engine_reset(dev);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
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return r600_do_engine_reset(dev);
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else
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return radeon_do_engine_reset(dev);
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}
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/* ================================================================
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@ -1997,7 +2085,13 @@ void radeon_commit_ring(drm_radeon_private_t *dev_priv)
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DRM_MEMORYBARRIER();
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GET_RING_HEAD( dev_priv );
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RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );
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/* read from PCI bus to ensure correct posting */
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RADEON_READ( RADEON_CP_RB_RPTR );
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
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RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
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/* read from PCI bus to ensure correct posting */
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RADEON_READ(R600_CP_RB_RPTR);
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} else {
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RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
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/* read from PCI bus to ensure correct posting */
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RADEON_READ(RADEON_CP_RB_RPTR);
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}
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}
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@ -396,6 +396,8 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
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extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
|
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extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
|
||||
extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
|
||||
extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
|
||||
extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
|
||||
extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
|
||||
|
||||
extern void radeon_freelist_reset(struct drm_device * dev);
|
||||
@ -416,6 +418,10 @@ extern void radeon_mem_takedown(struct mem_block **heap);
|
||||
extern void radeon_mem_release(struct drm_file *file_priv,
|
||||
struct mem_block *heap);
|
||||
|
||||
extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
|
||||
extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
|
||||
extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
|
||||
|
||||
/* radeon_irq.c */
|
||||
extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
|
||||
extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
|
||||
@ -456,6 +462,19 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
|
||||
struct drm_file *file_priv,
|
||||
drm_radeon_kcmd_buffer_t *cmdbuf);
|
||||
|
||||
/* r600_cp.c */
|
||||
extern int r600_do_engine_reset(struct drm_device *dev);
|
||||
extern int r600_do_cleanup_cp(struct drm_device *dev);
|
||||
extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
|
||||
struct drm_file *file_priv);
|
||||
extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
|
||||
extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
|
||||
extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
|
||||
extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
|
||||
extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
|
||||
extern int r600_cp_dispatch_indirect(struct drm_device *dev,
|
||||
struct drm_buf *buf, int start, int end);
|
||||
|
||||
/* Flags for stats.boxes
|
||||
*/
|
||||
#define RADEON_BOX_DMA_IDLE 0x1
|
||||
@ -1832,7 +1851,11 @@ do { \
|
||||
struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
|
||||
drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
|
||||
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
|
||||
int __ret = radeon_do_cp_idle( dev_priv ); \
|
||||
int __ret; \
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
|
||||
__ret = r600_do_cp_idle(dev_priv); \
|
||||
else \
|
||||
__ret = radeon_do_cp_idle(dev_priv); \
|
||||
if ( __ret ) return __ret; \
|
||||
sarea_priv->last_dispatch = 0; \
|
||||
radeon_freelist_reset( dev ); \
|
||||
|
||||
@ -1556,9 +1556,15 @@ static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *
|
||||
buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
|
||||
|
||||
/* Emit the vertex buffer age */
|
||||
BEGIN_RING(2);
|
||||
RADEON_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
|
||||
BEGIN_RING(3);
|
||||
R600_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
} else {
|
||||
BEGIN_RING(2);
|
||||
RADEON_DISPATCH_AGE(buf_priv->age);
|
||||
ADVANCE_RING();
|
||||
}
|
||||
|
||||
buf->pending = 1;
|
||||
buf->used = 0;
|
||||
@ -2473,24 +2479,25 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
|
||||
|
||||
buf->used = indirect->end;
|
||||
|
||||
/* Wait for the 3D stream to idle before the indirect buffer
|
||||
* containing 2D acceleration commands is processed.
|
||||
*/
|
||||
BEGIN_RING(2);
|
||||
|
||||
RADEON_WAIT_UNTIL_3D_IDLE();
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
/* Dispatch the indirect buffer full of commands from the
|
||||
* X server. This is insecure and is thus only available to
|
||||
* privileged clients.
|
||||
*/
|
||||
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
if (indirect->discard) {
|
||||
radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
|
||||
r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
else {
|
||||
/* Wait for the 3D stream to idle before the indirect buffer
|
||||
* containing 2D acceleration commands is processed.
|
||||
*/
|
||||
BEGIN_RING(2);
|
||||
RADEON_WAIT_UNTIL_3D_IDLE();
|
||||
ADVANCE_RING();
|
||||
radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
|
||||
}
|
||||
|
||||
if (indirect->discard)
|
||||
radeon_cp_discard_buffer(dev, file_priv->master, buf);
|
||||
|
||||
COMMIT_RING();
|
||||
return 0;
|
||||
}
|
||||
@ -3052,7 +3059,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
|
||||
case RADEON_PARAM_SCRATCH_OFFSET:
|
||||
if (!dev_priv->writeback_works)
|
||||
return -EINVAL;
|
||||
value = RADEON_SCRATCH_REG_OFFSET;
|
||||
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
|
||||
value = R600_SCRATCH_REG_OFFSET;
|
||||
else
|
||||
value = RADEON_SCRATCH_REG_OFFSET;
|
||||
break;
|
||||
case RADEON_PARAM_CARD_TYPE:
|
||||
if (dev_priv->flags & RADEON_IS_PCIE)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user