mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 01:46:48 +07:00
iwlwifi: allocate more receive buffers for HE devices
For HE-capable devices, we need to allocate more receive buffers as there could be 256 frames aggregated into a single A-MPDU, and then they might contain A-MSDUs as well. Until 22000 family, the devices are able to put multiple frames into a single RB and the default RB size is 4k, but starting from AX210 family this is no longer true. On the other hand, those newer devices only use 2k receive buffers (by default). Modify the code and configuration to allocate an appropriate number of RBs depending on the device capabilities: * 4096 for AX210 HE devices, which use 2k buffers by default, * 2048 for 22000 family devices which use 4k buffers by default, * 512 for existing 9000 family devices, which doesn't really change anything since that's the default before this patch, * 512 also for AX210/22000 family devices that don't do HE. Theoretically, for devices lower than AX210, we wouldn't have to allocate that many RBs if the RB size was manually increased, but to support that the code got more complex, and it didn't really seem necessary as that's a use case for monitor mode only, where hopefully the wasted memory isn't really much of a concern. Note that AX210 devices actually support bigger than 12-bit VID, which is required here as we want to allocate 4096 buffers plus some for quick recycling, so adjust the code for that as well. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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b1a6db1320
commit
c042f0c77f
@ -236,10 +236,22 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
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}, \
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}
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/*
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* If the device doesn't support HE, no need to have that many buffers.
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* 22000 devices can split multiple frames into a single RB, so fewer are
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* needed; AX210 cannot (but use smaller RBs by default) - these sizes
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* were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
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* additional overhead to account for processing time.
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*/
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#define IWL_NUM_RBDS_NON_HE 512
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#define IWL_NUM_RBDS_22000_HE 2048
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#define IWL_NUM_RBDS_AX210_HE 4096
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const struct iwl_cfg iwl22000_2ac_cfg_hr = {
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.name = "Intel(R) Dual Band Wireless AC 22000",
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.fw_name_pre = IWL_22000_HR_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb = {
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@ -247,12 +259,14 @@ const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb = {
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.fw_name_pre = IWL_22000_HR_CDB_FW_PRE,
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IWL_DEVICE_22500,
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.cdb = true,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl22000_2ac_cfg_jf = {
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.name = "Intel(R) Dual Band Wireless AC 22000",
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.fw_name_pre = IWL_22000_JF_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl_ax101_cfg_qu_hr = {
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@ -266,6 +280,7 @@ const struct iwl_cfg iwl_ax101_cfg_qu_hr = {
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.tx_with_siso_diversity = true,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
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@ -278,6 +293,7 @@ const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax101_cfg_qu_c0_hr_b0 = {
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@ -290,6 +306,7 @@ const struct iwl_cfg iwl_ax101_cfg_qu_c0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
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@ -302,6 +319,7 @@ const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax101_cfg_quz_hr = {
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@ -314,6 +332,7 @@ const struct iwl_cfg iwl_ax101_cfg_quz_hr = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
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@ -326,6 +345,7 @@ const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
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@ -338,6 +358,7 @@ const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
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@ -350,6 +371,7 @@ const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl_ax200_cfg_cc = {
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@ -363,6 +385,7 @@ const struct iwl_cfg iwl_ax200_cfg_cc = {
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.trans.bisr_workaround = 1,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg killer1650x_2ax_cfg = {
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@ -376,6 +399,7 @@ const struct iwl_cfg killer1650x_2ax_cfg = {
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.trans.bisr_workaround = 1,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg killer1650w_2ax_cfg = {
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@ -389,6 +413,7 @@ const struct iwl_cfg killer1650w_2ax_cfg = {
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.trans.bisr_workaround = 1,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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/*
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@ -400,48 +425,56 @@ const struct iwl_cfg iwl9461_2ac_cfg_qu_b0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9461",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9462_2ac_cfg_qu_b0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9462",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_cfg_qu_b0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9560",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_160_cfg_qu_b0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9560 160MHz",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9461_2ac_cfg_qu_c0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9461",
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.fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9462_2ac_cfg_qu_c0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9462",
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.fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_cfg_qu_c0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9560",
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.fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_160_cfg_qu_c0_jf_b0 = {
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.name = "Intel(R) Wireless-AC 9560 160MHz",
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.fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_cfg_qnj_jf_b0 = {
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@ -454,6 +487,7 @@ const struct iwl_cfg iwl9560_2ac_cfg_qnj_jf_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_cfg_quz_a0_jf_b0_soc = {
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@ -468,6 +502,7 @@ const struct iwl_cfg iwl9560_2ac_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_2ac_160_cfg_quz_a0_jf_b0_soc = {
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@ -482,6 +517,7 @@ const struct iwl_cfg iwl9560_2ac_160_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9461_2ac_cfg_quz_a0_jf_b0_soc = {
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@ -496,6 +532,7 @@ const struct iwl_cfg iwl9461_2ac_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9462_2ac_cfg_quz_a0_jf_b0_soc = {
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@ -510,6 +547,7 @@ const struct iwl_cfg iwl9462_2ac_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_killer_s_2ac_cfg_quz_a0_jf_b0_soc = {
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@ -524,6 +562,7 @@ const struct iwl_cfg iwl9560_killer_s_2ac_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwl9560_killer_i_2ac_cfg_quz_a0_jf_b0_soc = {
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@ -538,18 +577,21 @@ const struct iwl_cfg iwl9560_killer_i_2ac_cfg_quz_a0_jf_b0_soc = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.integrated = true,
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.soc_latency = 5000,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg killer1550i_2ac_cfg_qu_b0_jf_b0 = {
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.name = "Killer (R) Wireless-AC 1550i Wireless Network Adapter (9560NGW)",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg killer1550s_2ac_cfg_qu_b0_jf_b0 = {
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.name = "Killer (R) Wireless-AC 1550s Wireless Network Adapter (9560NGW)",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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IWL_DEVICE_22500,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
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@ -562,6 +604,7 @@ const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
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@ -574,6 +617,7 @@ const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
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@ -586,6 +630,7 @@ const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
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@ -598,6 +643,7 @@ const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl22000_2ax_cfg_jf = {
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@ -610,6 +656,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_jf = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0_f0 = {
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@ -622,6 +669,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0_f0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0 = {
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@ -634,6 +682,7 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0 = {
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@ -646,18 +695,21 @@ const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0 = {
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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.num_rbds = IWL_NUM_RBDS_22000_HE,
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};
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const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0 = {
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.name = "Intel(R) Wireless-AC 9560 160MHz",
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.fw_name_pre = IWL_22000_SO_A_JF_B_FW_PRE,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_NON_HE,
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};
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const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0 = {
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.name = "Intel(R) Wi-Fi 7 AX210 160MHz",
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.fw_name_pre = IWL_22000_SO_A_HR_B_FW_PRE,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
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const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
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@ -665,6 +717,7 @@ const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
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.fw_name_pre = IWL_22000_SO_A_GF_A_FW_PRE,
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.uhb_supported = true,
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IWL_DEVICE_AX210,
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.num_rbds = IWL_NUM_RBDS_AX210_HE,
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};
|
||||
|
||||
const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
|
||||
@ -672,12 +725,14 @@ const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
|
||||
.fw_name_pre = IWL_22000_TY_A_GF_A_FW_PRE,
|
||||
.uhb_supported = true,
|
||||
IWL_DEVICE_AX210,
|
||||
.num_rbds = IWL_NUM_RBDS_AX210_HE,
|
||||
};
|
||||
|
||||
const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
|
||||
.name = "Intel(R) Wi-Fi 7 AX411 160MHz",
|
||||
.fw_name_pre = IWL_22000_SO_A_GF4_A_FW_PRE,
|
||||
IWL_DEVICE_AX210,
|
||||
.num_rbds = IWL_NUM_RBDS_AX210_HE,
|
||||
};
|
||||
|
||||
MODULE_FIRMWARE(IWL_22000_HR_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
|
||||
|
@ -138,6 +138,7 @@ static const struct iwl_tt_params iwl9000_tt_params = {
|
||||
.thermal_params = &iwl9000_tt_params, \
|
||||
.apmg_not_supported = true, \
|
||||
.trans.mq_rx_supported = true, \
|
||||
.num_rbds = 512, \
|
||||
.vht_mu_mimo_supported = true, \
|
||||
.mac_addr_from_csr = true, \
|
||||
.trans.rf_id = true, \
|
||||
|
@ -431,6 +431,8 @@ struct iwl_fw_mon_regs {
|
||||
* @uhb_supported: ultra high band channels supported
|
||||
* @min_256_ba_txq_size: minimum number of slots required in a TX queue which
|
||||
* supports 256 BA aggregation
|
||||
* @num_rbds: number of receive buffer descriptors to use
|
||||
* (only used for multi-queue capable devices)
|
||||
*
|
||||
* We enable the driver to be backward compatible wrt. hardware features.
|
||||
* API differences in uCode shouldn't be handled here but through TLVs
|
||||
@ -485,6 +487,7 @@ struct iwl_cfg {
|
||||
u8 max_vht_ampdu_exponent;
|
||||
u8 ucode_api_max;
|
||||
u8 ucode_api_min;
|
||||
u16 num_rbds;
|
||||
u32 min_umac_error_event_table;
|
||||
u32 extra_phy_cfg_flags;
|
||||
u32 d3_debug_data_base_addr;
|
||||
|
@ -6,7 +6,7 @@
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright(c) 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* Copyright(c) 2018 - 2019 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
@ -20,7 +20,7 @@
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2017 Intel Deutschland GmbH
|
||||
* Copyright(c) 2018 Intel Corporation
|
||||
* Copyright(c) 2018 - 2019 Intel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -64,12 +64,12 @@
|
||||
* the init done for driver command that configures several system modes
|
||||
* @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
|
||||
* @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
|
||||
* @IWL_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
|
||||
* @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
|
||||
* exponent, the actual size is 2**value, valid sizes are 8-2048.
|
||||
* The value is four bits long. Maximum valid exponent is 12
|
||||
* @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
|
||||
* default is short format - not supported by the driver)
|
||||
* @IWL_CTXT_INFO_RB_SIZE_POS: RB size position
|
||||
* @IWL_CTXT_INFO_RB_SIZE: RB size mask
|
||||
* (values are IWL_CTXT_INFO_RB_SIZE_*K)
|
||||
* @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
|
||||
* @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
|
||||
@ -83,12 +83,12 @@
|
||||
* @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
|
||||
*/
|
||||
enum iwl_context_info_flags {
|
||||
IWL_CTXT_INFO_AUTO_FUNC_INIT = BIT(0),
|
||||
IWL_CTXT_INFO_EARLY_DEBUG = BIT(1),
|
||||
IWL_CTXT_INFO_ENABLE_CDMP = BIT(2),
|
||||
IWL_CTXT_INFO_RB_CB_SIZE_POS = 4,
|
||||
IWL_CTXT_INFO_TFD_FORMAT_LONG = BIT(8),
|
||||
IWL_CTXT_INFO_RB_SIZE_POS = 9,
|
||||
IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001,
|
||||
IWL_CTXT_INFO_EARLY_DEBUG = 0x0002,
|
||||
IWL_CTXT_INFO_ENABLE_CDMP = 0x0004,
|
||||
IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0,
|
||||
IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100,
|
||||
IWL_CTXT_INFO_RB_SIZE = 0x1e00,
|
||||
IWL_CTXT_INFO_RB_SIZE_1K = 0x1,
|
||||
IWL_CTXT_INFO_RB_SIZE_2K = 0x2,
|
||||
IWL_CTXT_INFO_RB_SIZE_4K = 0x4,
|
||||
|
@ -611,10 +611,7 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans,
|
||||
*/
|
||||
#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
|
||||
|
||||
#define MQ_RX_TABLE_SIZE 512
|
||||
#define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1)
|
||||
#define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1)
|
||||
#define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \
|
||||
#define RX_POOL_SIZE(rbds) ((rbds) - 1 + \
|
||||
IWL_MAX_RX_HW_QUEUES * \
|
||||
(RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
|
||||
/* cb size is the exponent */
|
||||
|
@ -206,7 +206,7 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
|
||||
ctxt_info_gen3->mtr_size =
|
||||
cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
|
||||
ctxt_info_gen3->mcr_size =
|
||||
cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE));
|
||||
cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
|
||||
|
||||
trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
|
||||
trans_pcie->prph_info = prph_info;
|
||||
|
@ -193,11 +193,12 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
|
||||
rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
|
||||
}
|
||||
|
||||
BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
|
||||
control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG |
|
||||
(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
|
||||
IWL_CTXT_INFO_RB_CB_SIZE_POS) |
|
||||
(rb_size << IWL_CTXT_INFO_RB_SIZE_POS);
|
||||
WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
|
||||
control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
|
||||
control_flags |=
|
||||
u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
|
||||
IWL_CTXT_INFO_RB_CB_SIZE);
|
||||
control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
|
||||
ctxt_info->control.control_flags = cpu_to_le32(control_flags);
|
||||
|
||||
/* initialize RX default queue */
|
||||
|
@ -995,6 +995,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
const struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
|
||||
const struct iwl_cfg *cfg_7265d __maybe_unused = NULL;
|
||||
struct iwl_trans *iwl_trans;
|
||||
struct iwl_trans_pcie *trans_pcie;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
@ -1002,6 +1003,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
if (IS_ERR(iwl_trans))
|
||||
return PTR_ERR(iwl_trans);
|
||||
|
||||
trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
|
||||
|
||||
/* the trans_cfg should never change, so set it now */
|
||||
iwl_trans->trans_cfg = &cfg->trans;
|
||||
|
||||
@ -1129,6 +1132,16 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
/* now set the real cfg we decided to use */
|
||||
iwl_trans->cfg = cfg;
|
||||
|
||||
if (cfg->trans.mq_rx_supported) {
|
||||
if (WARN_ON(!cfg->num_rbds)) {
|
||||
ret = -EINVAL;
|
||||
goto out_free_trans;
|
||||
}
|
||||
trans_pcie->num_rx_bufs = cfg->num_rbds;
|
||||
} else {
|
||||
trans_pcie->num_rx_bufs = RX_QUEUE_SIZE;
|
||||
}
|
||||
|
||||
if (iwl_trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000 &&
|
||||
iwl_trans_grab_nic_access(iwl_trans, &flags)) {
|
||||
u32 hw_step;
|
||||
|
@ -513,8 +513,8 @@ struct cont_rec {
|
||||
*/
|
||||
struct iwl_trans_pcie {
|
||||
struct iwl_rxq *rxq;
|
||||
struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
|
||||
struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
|
||||
struct iwl_rx_mem_buffer *rx_pool;
|
||||
struct iwl_rx_mem_buffer **global_table;
|
||||
struct iwl_rb_allocator rba;
|
||||
union {
|
||||
struct iwl_context_info *ctxt_info;
|
||||
@ -573,6 +573,7 @@ struct iwl_trans_pcie {
|
||||
u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
|
||||
u8 max_tbs;
|
||||
u16 tfd_size;
|
||||
u16 num_rx_bufs;
|
||||
|
||||
enum iwl_amsdu_size rx_buf_size;
|
||||
bool bc_table_dword;
|
||||
|
@ -510,7 +510,7 @@ void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
|
||||
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < RX_POOL_SIZE; i++) {
|
||||
for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) {
|
||||
if (!trans_pcie->rx_pool[i].page)
|
||||
continue;
|
||||
dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
|
||||
@ -738,7 +738,7 @@ static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
|
||||
|
||||
spin_lock_init(&rxq->lock);
|
||||
if (trans->trans_cfg->mq_rx_supported)
|
||||
rxq->queue_size = MQ_RX_TABLE_SIZE;
|
||||
rxq->queue_size = trans->cfg->num_rbds;
|
||||
else
|
||||
rxq->queue_size = RX_QUEUE_SIZE;
|
||||
|
||||
@ -807,8 +807,18 @@ static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
|
||||
|
||||
trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
|
||||
GFP_KERNEL);
|
||||
if (!trans_pcie->rxq)
|
||||
return -ENOMEM;
|
||||
trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
|
||||
sizeof(trans_pcie->rx_pool[0]),
|
||||
GFP_KERNEL);
|
||||
trans_pcie->global_table =
|
||||
kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
|
||||
sizeof(trans_pcie->global_table[0]),
|
||||
GFP_KERNEL);
|
||||
if (!trans_pcie->rxq || !trans_pcie->rx_pool ||
|
||||
!trans_pcie->global_table) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
spin_lock_init(&rba->lock);
|
||||
|
||||
@ -845,6 +855,8 @@ static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
|
||||
trans_pcie->base_rb_stts = NULL;
|
||||
trans_pcie->base_rb_stts_dma = 0;
|
||||
}
|
||||
kfree(trans_pcie->rx_pool);
|
||||
kfree(trans_pcie->global_table);
|
||||
kfree(trans_pcie->rxq);
|
||||
|
||||
return ret;
|
||||
@ -1081,12 +1093,11 @@ static int _iwl_pcie_rx_init(struct iwl_trans *trans)
|
||||
|
||||
/* move the pool to the default queue and allocator ownerships */
|
||||
queue_size = trans->trans_cfg->mq_rx_supported ?
|
||||
MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
|
||||
trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE;
|
||||
allocator_pool_size = trans->num_rx_queues *
|
||||
(RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
|
||||
num_alloc = queue_size + allocator_pool_size;
|
||||
BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
|
||||
ARRAY_SIZE(trans_pcie->rx_pool));
|
||||
|
||||
for (i = 0; i < num_alloc; i++) {
|
||||
struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
|
||||
|
||||
@ -1177,6 +1188,8 @@ void iwl_pcie_rx_free(struct iwl_trans *trans)
|
||||
if (rxq->napi.poll)
|
||||
netif_napi_del(&rxq->napi);
|
||||
}
|
||||
kfree(trans_pcie->rx_pool);
|
||||
kfree(trans_pcie->global_table);
|
||||
kfree(trans_pcie->rxq);
|
||||
}
|
||||
|
||||
@ -1390,13 +1403,12 @@ static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
|
||||
return rxb;
|
||||
}
|
||||
|
||||
/* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */
|
||||
if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
|
||||
vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF;
|
||||
vid = le16_to_cpu(rxq->cd[i].rbid);
|
||||
else
|
||||
vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF;
|
||||
vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF; /* 12-bit VID */
|
||||
|
||||
if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table))
|
||||
if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs))
|
||||
goto out_err;
|
||||
|
||||
rxb = trans_pcie->global_table[vid - 1];
|
||||
|
Loading…
Reference in New Issue
Block a user