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drm/amdgpu:change VEGA booting with firmware loaded by PSP
With PSP firmware loading, TMR mc address is supposed to be used. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -671,9 +671,14 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
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continue;
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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i == 0 ?
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adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
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adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
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WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
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i == 0 ?
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adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
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adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
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WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
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offset = 0;
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} else {
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WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
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@ -681,10 +686,10 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
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WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
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upper_32_bits(adev->uvd.inst[i].gpu_addr));
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offset = size;
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}
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WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
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AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
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}
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WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
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WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
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