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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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xen/PMU: PMU emulation code
Add PMU emulation code that runs when we are processing a PMU interrupt. This code will allow us not to trap to hypervisor on each MSR/LVTPC access (of which there may be quite a few in the handler). Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
This commit is contained in:
Boris Ostrovsky
David Vrabel
parent
6b08cd6328
commit
bf6dfb154d
@ -13,11 +13,20 @@
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/* x86_pmu.handle_irq definition */
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#include "../kernel/cpu/perf_event.h"
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#define XENPMU_IRQ_PROCESSING 1
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struct xenpmu {
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/* Shared page between hypervisor and domain */
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struct xen_pmu_data *xenpmu_data;
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/* Shared page between hypervisor and domain */
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static DEFINE_PER_CPU(struct xen_pmu_data *, xenpmu_shared);
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#define get_xenpmu_data() per_cpu(xenpmu_shared, smp_processor_id())
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uint8_t flags;
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};
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static DEFINE_PER_CPU(struct xenpmu, xenpmu_shared);
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#define get_xenpmu_data() (this_cpu_ptr(&xenpmu_shared)->xenpmu_data)
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#define get_xenpmu_flags() (this_cpu_ptr(&xenpmu_shared)->flags)
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/* Macro for computing address of a PMU MSR bank */
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#define field_offset(ctxt, field) ((void *)((uintptr_t)ctxt + \
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(uintptr_t)ctxt->field))
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/* AMD PMU */
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#define F15H_NUM_COUNTERS 6
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@ -169,19 +178,124 @@ static int is_intel_pmu_msr(u32 msr_index, int *type, int *index)
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}
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}
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static bool xen_intel_pmu_emulate(unsigned int msr, u64 *val, int type,
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int index, bool is_read)
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{
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uint64_t *reg = NULL;
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struct xen_pmu_intel_ctxt *ctxt;
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uint64_t *fix_counters;
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struct xen_pmu_cntr_pair *arch_cntr_pair;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
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return false;
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ctxt = &xenpmu_data->pmu.c.intel;
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switch (msr) {
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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reg = &ctxt->global_ovf_ctrl;
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break;
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case MSR_CORE_PERF_GLOBAL_STATUS:
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reg = &ctxt->global_status;
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break;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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reg = &ctxt->global_ctrl;
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break;
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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reg = &ctxt->fixed_ctrl;
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break;
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default:
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switch (type) {
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case MSR_TYPE_COUNTER:
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fix_counters = field_offset(ctxt, fixed_counters);
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reg = &fix_counters[index];
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break;
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case MSR_TYPE_ARCH_COUNTER:
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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reg = &arch_cntr_pair[index].counter;
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break;
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case MSR_TYPE_ARCH_CTRL:
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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reg = &arch_cntr_pair[index].control;
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break;
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default:
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return false;
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}
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}
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if (reg) {
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if (is_read)
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*val = *reg;
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else {
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*reg = *val;
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if (msr == MSR_CORE_PERF_GLOBAL_OVF_CTRL)
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ctxt->global_status &= (~(*val));
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}
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return true;
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}
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return false;
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}
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static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val, bool is_read)
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{
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uint64_t *reg = NULL;
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int i, off = 0;
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struct xen_pmu_amd_ctxt *ctxt;
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uint64_t *counter_regs, *ctrl_regs;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING))
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return false;
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if (k7_counters_mirrored &&
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((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3)))
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msr = get_fam15h_addr(msr);
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ctxt = &xenpmu_data->pmu.c.amd;
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for (i = 0; i < amd_num_counters; i++) {
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if (msr == amd_ctrls_base + off) {
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ctrl_regs = field_offset(ctxt, ctrls);
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reg = &ctrl_regs[i];
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break;
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} else if (msr == amd_counters_base + off) {
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counter_regs = field_offset(ctxt, counters);
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reg = &counter_regs[i];
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break;
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}
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off += amd_msr_step;
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}
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if (reg) {
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if (is_read)
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*val = *reg;
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else
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*reg = *val;
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return true;
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}
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return false;
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}
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bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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if (is_amd_pmu_msr(msr)) {
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*val = native_read_msr_safe(msr, err);
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if (!xen_amd_pmu_emulate(msr, val, 1))
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*val = native_read_msr_safe(msr, err);
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return true;
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}
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} else {
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int type, index;
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if (is_intel_pmu_msr(msr, &type, &index)) {
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*val = native_read_msr_safe(msr, err);
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if (!xen_intel_pmu_emulate(msr, val, type, index, 1))
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*val = native_read_msr_safe(msr, err);
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return true;
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}
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}
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@ -191,16 +305,20 @@ bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
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bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
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{
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uint64_t val = ((uint64_t)high << 32) | low;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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if (is_amd_pmu_msr(msr)) {
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*err = native_write_msr_safe(msr, low, high);
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if (!xen_amd_pmu_emulate(msr, &val, 0))
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*err = native_write_msr_safe(msr, low, high);
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return true;
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}
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} else {
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int type, index;
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if (is_intel_pmu_msr(msr, &type, &index)) {
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*err = native_write_msr_safe(msr, low, high);
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if (!xen_intel_pmu_emulate(msr, &val, type, index, 0))
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*err = native_write_msr_safe(msr, low, high);
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return true;
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}
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}
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@ -210,24 +328,52 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err)
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static unsigned long long xen_amd_read_pmc(int counter)
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{
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uint32_t msr;
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int err;
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struct xen_pmu_amd_ctxt *ctxt;
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uint64_t *counter_regs;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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msr = amd_counters_base + (counter * amd_msr_step);
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return native_read_msr_safe(msr, &err);
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
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uint32_t msr;
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int err;
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msr = amd_counters_base + (counter * amd_msr_step);
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return native_read_msr_safe(msr, &err);
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}
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ctxt = &xenpmu_data->pmu.c.amd;
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counter_regs = field_offset(ctxt, counters);
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return counter_regs[counter];
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}
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static unsigned long long xen_intel_read_pmc(int counter)
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{
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int err;
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uint32_t msr;
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struct xen_pmu_intel_ctxt *ctxt;
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uint64_t *fixed_counters;
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struct xen_pmu_cntr_pair *arch_cntr_pair;
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struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (counter & (1<<INTEL_PMC_TYPE_SHIFT))
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msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);
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else
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msr = MSR_IA32_PERFCTR0 + counter;
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if (!xenpmu_data || !(xenpmu_flags & XENPMU_IRQ_PROCESSING)) {
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uint32_t msr;
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int err;
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return native_read_msr_safe(msr, &err);
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if (counter & (1 << INTEL_PMC_TYPE_SHIFT))
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msr = MSR_CORE_PERF_FIXED_CTR0 + (counter & 0xffff);
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else
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msr = MSR_IA32_PERFCTR0 + counter;
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return native_read_msr_safe(msr, &err);
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}
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ctxt = &xenpmu_data->pmu.c.intel;
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if (counter & (1 << INTEL_PMC_TYPE_SHIFT)) {
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fixed_counters = field_offset(ctxt, fixed_counters);
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return fixed_counters[counter & 0xffff];
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}
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arch_cntr_pair = field_offset(ctxt, arch_counters);
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return arch_cntr_pair[counter].counter;
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}
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unsigned long long xen_read_pmc(int counter)
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@ -249,6 +395,10 @@ int pmu_apic_update(uint32_t val)
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}
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xenpmu_data->pmu.l.lapic_lvtpc = val;
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if (get_xenpmu_flags() & XENPMU_IRQ_PROCESSING)
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return 0;
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ret = HYPERVISOR_xenpmu_op(XENPMU_lvtpc_set, NULL);
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return ret;
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@ -329,29 +479,34 @@ irqreturn_t xen_pmu_irq_handler(int irq, void *dev_id)
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int err, ret = IRQ_NONE;
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struct pt_regs regs;
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const struct xen_pmu_data *xenpmu_data = get_xenpmu_data();
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uint8_t xenpmu_flags = get_xenpmu_flags();
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if (!xenpmu_data) {
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pr_warn_once("%s: pmudata not initialized\n", __func__);
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return ret;
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}
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err = HYPERVISOR_xenpmu_op(XENPMU_flush, NULL);
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if (err) {
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pr_warn_once("%s: failed hypercall, err: %d\n", __func__, err);
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return ret;
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}
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this_cpu_ptr(&xenpmu_shared)->flags =
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xenpmu_flags | XENPMU_IRQ_PROCESSING;
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xen_convert_regs(&xenpmu_data->pmu.r.regs, ®s,
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xenpmu_data->pmu.pmu_flags);
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if (x86_pmu.handle_irq(®s))
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ret = IRQ_HANDLED;
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/* Write out cached context to HW */
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err = HYPERVISOR_xenpmu_op(XENPMU_flush, NULL);
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this_cpu_ptr(&xenpmu_shared)->flags = xenpmu_flags;
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if (err) {
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pr_warn_once("%s: failed hypercall, err: %d\n", __func__, err);
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return IRQ_NONE;
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}
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return ret;
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}
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bool is_xen_pmu(int cpu)
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{
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return (per_cpu(xenpmu_shared, cpu) != NULL);
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return (get_xenpmu_data() != NULL);
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}
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void xen_pmu_init(int cpu)
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@ -381,7 +536,8 @@ void xen_pmu_init(int cpu)
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if (err)
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goto fail;
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per_cpu(xenpmu_shared, cpu) = xenpmu_data;
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per_cpu(xenpmu_shared, cpu).xenpmu_data = xenpmu_data;
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per_cpu(xenpmu_shared, cpu).flags = 0;
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if (cpu == 0) {
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perf_register_guest_info_callbacks(&xen_guest_cbs);
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@ -409,6 +565,6 @@ void xen_pmu_finish(int cpu)
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(void)HYPERVISOR_xenpmu_op(XENPMU_finish, &xp);
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free_pages((unsigned long)per_cpu(xenpmu_shared, cpu), 0);
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per_cpu(xenpmu_shared, cpu) = NULL;
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free_pages((unsigned long)per_cpu(xenpmu_shared, cpu).xenpmu_data, 0);
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per_cpu(xenpmu_shared, cpu).xenpmu_data = NULL;
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}
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