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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 07:36:47 +07:00
pinctrl: nomadik: delete ancient pin control API
The pin control subsystem was created to do away with custom pin control APIs such as this one. It was kept for backward-compatibility but is completely unused in the current kernel, so let's delete it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
87311d0455
commit
bf4dae5ce1
@ -337,97 +337,6 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
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nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
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}
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static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
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pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
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{
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static const char *afnames[] = {
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[NMK_GPIO_ALT_GPIO] = "GPIO",
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[NMK_GPIO_ALT_A] = "A",
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[NMK_GPIO_ALT_B] = "B",
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[NMK_GPIO_ALT_C] = "C"
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};
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static const char *pullnames[] = {
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[NMK_GPIO_PULL_NONE] = "none",
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[NMK_GPIO_PULL_UP] = "up",
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[NMK_GPIO_PULL_DOWN] = "down",
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[3] /* illegal */ = "??"
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};
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static const char *slpmnames[] = {
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[NMK_GPIO_SLPM_INPUT] = "input/wakeup",
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[NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
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};
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int pin = PIN_NUM(cfg);
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int pull = PIN_PULL(cfg);
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int af = PIN_ALT(cfg);
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int slpm = PIN_SLPM(cfg);
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int output = PIN_DIR(cfg);
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int val = PIN_VAL(cfg);
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bool glitch = af == NMK_GPIO_ALT_C;
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dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
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pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
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output ? "output " : "input",
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output ? (val ? "high" : "low") : "");
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if (sleep) {
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int slpm_pull = PIN_SLPM_PULL(cfg);
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int slpm_output = PIN_SLPM_DIR(cfg);
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int slpm_val = PIN_SLPM_VAL(cfg);
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af = NMK_GPIO_ALT_GPIO;
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/*
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* The SLPM_* values are normal values + 1 to allow zero to
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* mean "same as normal".
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*/
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if (slpm_pull)
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pull = slpm_pull - 1;
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if (slpm_output)
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output = slpm_output - 1;
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if (slpm_val)
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val = slpm_val - 1;
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dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
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pin,
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slpm_pull ? pullnames[pull] : "same",
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slpm_output ? (output ? "output" : "input") : "same",
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slpm_val ? (val ? "high" : "low") : "same");
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}
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if (output)
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__nmk_gpio_make_output(nmk_chip, offset, val);
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else {
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__nmk_gpio_make_input(nmk_chip, offset);
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__nmk_gpio_set_pull(nmk_chip, offset, pull);
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}
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__nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
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/*
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* If the pin is switching to altfunc, and there was an interrupt
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* installed on it which has been lazy disabled, actually mask the
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* interrupt to prevent spurious interrupts that would occur while the
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* pin is under control of the peripheral. Only SKE does this.
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*/
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if (af != NMK_GPIO_ALT_GPIO)
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nmk_gpio_disable_lazy_irq(nmk_chip, offset);
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/*
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* If we've backed up the SLPM registers (glitch workaround), modify
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* the backups since they will be restored.
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*/
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if (slpmregs) {
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if (slpm == NMK_GPIO_SLPM_NOCHANGE)
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slpmregs[nmk_chip->bank] |= BIT(offset);
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else
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slpmregs[nmk_chip->bank] &= ~BIT(offset);
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} else
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__nmk_gpio_set_slpm(nmk_chip, offset, slpm);
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__nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
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}
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/*
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* Safe sequence used to switch IOs between GPIO and Alternate-C mode:
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* - Save SLPM registers
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@ -474,210 +383,6 @@ static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
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}
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}
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static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
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{
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static unsigned int slpm[NUM_BANKS];
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unsigned long flags;
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bool glitch = false;
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int ret = 0;
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int i;
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for (i = 0; i < num; i++) {
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if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
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glitch = true;
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break;
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}
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}
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spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
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if (glitch) {
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memset(slpm, 0xff, sizeof(slpm));
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for (i = 0; i < num; i++) {
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int pin = PIN_NUM(cfgs[i]);
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int offset = pin % NMK_GPIO_PER_CHIP;
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if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
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slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
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}
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nmk_gpio_glitch_slpm_init(slpm);
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}
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for (i = 0; i < num; i++) {
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struct nmk_gpio_chip *nmk_chip;
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int pin = PIN_NUM(cfgs[i]);
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nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
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if (!nmk_chip) {
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ret = -EINVAL;
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break;
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}
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clk_enable(nmk_chip->clk);
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spin_lock(&nmk_chip->lock);
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__nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
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cfgs[i], sleep, glitch ? slpm : NULL);
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spin_unlock(&nmk_chip->lock);
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clk_disable(nmk_chip->clk);
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}
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if (glitch)
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nmk_gpio_glitch_slpm_restore(slpm);
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spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
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return ret;
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}
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/**
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* nmk_config_pin - configure a pin's mux attributes
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* @cfg: pin confguration
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* @sleep: Non-zero to apply the sleep mode configuration
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* Configures a pin's mode (alternate function or GPIO), its pull up status,
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* and its sleep mode based on the specified configuration. The @cfg is
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* usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
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* are constructed using, and can be further enhanced with, the macros in
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* <linux/platform_data/pinctrl-nomadik.h>
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*
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* If a pin's mode is set to GPIO, it is configured as an input to avoid
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* side-effects. The gpio can be manipulated later using standard GPIO API
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* calls.
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*/
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int nmk_config_pin(pin_cfg_t cfg, bool sleep)
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{
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return __nmk_config_pins(&cfg, 1, sleep);
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}
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EXPORT_SYMBOL(nmk_config_pin);
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/**
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* nmk_config_pins - configure several pins at once
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* @cfgs: array of pin configurations
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* @num: number of elments in the array
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*
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* Configures several pins using nmk_config_pin(). Refer to that function for
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* further information.
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*/
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int nmk_config_pins(pin_cfg_t *cfgs, int num)
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{
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return __nmk_config_pins(cfgs, num, false);
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}
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EXPORT_SYMBOL(nmk_config_pins);
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int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
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{
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return __nmk_config_pins(cfgs, num, true);
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}
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EXPORT_SYMBOL(nmk_config_pins_sleep);
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/**
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* nmk_gpio_set_slpm() - configure the sleep mode of a pin
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* @gpio: pin number
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* @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
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*
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* This register is actually in the pinmux layer, not the GPIO block itself.
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* The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
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* mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
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* Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
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* HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
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* When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
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* the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
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*
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* If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
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* mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
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* entered) regardless of the altfunction selected. Also wake-up detection is
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* ENABLED.
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*
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* If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
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* controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
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* (for altfunction GPIO) or respective on-chip peripherals (for other
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* altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
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*
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* Note that enable_irq_wake() will automatically enable wakeup detection.
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*/
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int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
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{
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struct nmk_gpio_chip *nmk_chip;
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unsigned long flags;
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nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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if (!nmk_chip)
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return -EINVAL;
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clk_enable(nmk_chip->clk);
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spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
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spin_lock(&nmk_chip->lock);
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__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
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spin_unlock(&nmk_chip->lock);
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spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
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clk_disable(nmk_chip->clk);
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return 0;
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}
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/**
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* nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
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* @gpio: pin number
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* @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
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*
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* Enables/disables pull up/down on a specified pin. This only takes effect if
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* the pin is configured as an input (either explicitly or by the alternate
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* function).
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*
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* NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
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* configured as an input. Otherwise, due to the way the controller registers
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* work, this function will change the value output on the pin.
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*/
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int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
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{
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struct nmk_gpio_chip *nmk_chip;
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unsigned long flags;
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nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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if (!nmk_chip)
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return -EINVAL;
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clk_enable(nmk_chip->clk);
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spin_lock_irqsave(&nmk_chip->lock, flags);
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__nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
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spin_unlock_irqrestore(&nmk_chip->lock, flags);
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clk_disable(nmk_chip->clk);
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return 0;
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}
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/* Mode functions */
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/**
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* nmk_gpio_set_mode() - set the mux mode of a gpio pin
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* @gpio: pin number
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* @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
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* NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
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*
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* Sets the mode of the specified pin to one of the alternate functions or
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* plain GPIO.
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*/
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int nmk_gpio_set_mode(int gpio, int gpio_mode)
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{
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struct nmk_gpio_chip *nmk_chip;
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unsigned long flags;
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nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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if (!nmk_chip)
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return -EINVAL;
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clk_enable(nmk_chip->clk);
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spin_lock_irqsave(&nmk_chip->lock, flags);
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__nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
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spin_unlock_irqrestore(&nmk_chip->lock, flags);
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clk_disable(nmk_chip->clk);
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return 0;
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}
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EXPORT_SYMBOL(nmk_gpio_set_mode);
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static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
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{
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int i;
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@ -226,30 +226,6 @@ enum nmk_gpio_slpm {
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NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
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};
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/* Older deprecated pin config API that should go away soon */
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extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
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extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
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extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
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extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
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extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
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#ifdef CONFIG_PINCTRL_NOMADIK
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extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
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#else
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static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
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{
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return -ENODEV;
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}
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#endif
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extern int nmk_gpio_get_mode(int gpio);
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extern void nmk_gpio_wakeups_suspend(void);
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extern void nmk_gpio_wakeups_resume(void);
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extern void nmk_gpio_clocks_enable(void);
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extern void nmk_gpio_clocks_disable(void);
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extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up);
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/*
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* Platform data to register a block: only the initial gpio/irq number.
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*/
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