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ath9k: Use tsf offset helper in ath9k_hw_reset

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These changes make ath9k_hw_reset more consistent with other places that
handle the TSF value by using the same helper routine.

A slight improvement is to not assume that a fixed time of 1.5ms has
passed for the initval writes when compared to the first write attempt.
Instead the TSF value is re-calculated which will yield a higher accuracy
of the restored TSF timer.

Signed-off-by: Benjamin Berg <benjamin.berg@open-mesh.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Benjamin Berg 2016-07-04 14:37:22 +02:00 committed by Kalle Valo
parent 9580cb889f
commit bec9a94bc4
1 changed files with 8 additions and 8 deletions
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16
drivers/net/wireless/ath/ath9k/hw.c
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@ -1828,8 +1828,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
u32 saveLedState; u32 saveLedState;
u32 saveDefAntenna; u32 saveDefAntenna;
u32 macStaId1; u32 macStaId1;
struct timespec tsf_ts;
u32 tsf_offset;
u64 tsf = 0; u64 tsf = 0;
s64 usec = 0;
int r; int r;
bool start_mci_reset = false; bool start_mci_reset = false;
bool save_fullsleep = ah->chip_fullsleep; bool save_fullsleep = ah->chip_fullsleep;
@ -1873,8 +1874,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
/* Save TSF before chip reset, a cold reset clears it */ /* Save TSF before chip reset, a cold reset clears it */
getrawmonotonic(&tsf_ts);
tsf = ath9k_hw_gettsf64(ah); tsf = ath9k_hw_gettsf64(ah);
usec = ktime_to_us(ktime_get_raw());
saveLedState = REG_READ(ah, AR_CFG_LED) & saveLedState = REG_READ(ah, AR_CFG_LED) &
(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
@ -1907,8 +1908,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
} }
/* Restore TSF */ /* Restore TSF */
usec = ktime_to_us(ktime_get_raw()) - usec; tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
ath9k_hw_settsf64(ah, tsf + usec); ath9k_hw_settsf64(ah, tsf + tsf_offset);
if (AR_SREV_9280_20_OR_LATER(ah)) if (AR_SREV_9280_20_OR_LATER(ah))
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
@ -1928,12 +1929,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
/* /*
* Some AR91xx SoC devices frequently fail to accept TSF writes * Some AR91xx SoC devices frequently fail to accept TSF writes
* right after the chip reset. When that happens, write a new * right after the chip reset. When that happens, write a new
* value after the initvals have been applied, with an offset * value after the initvals have been applied.
* based on measured time difference
*/ */
if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
tsf += 1500; tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL);
ath9k_hw_settsf64(ah, tsf); ath9k_hw_settsf64(ah, tsf + tsf_offset);
} }
ath9k_hw_init_mfp(ah); ath9k_hw_init_mfp(ah);