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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-19 22:16:49 +07:00
usb: dwc2: Declare the core params struct statically
This makes it consistent with the hw_params struct and simplifies the memory management for future refactoring. Fix up usage in all files. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
John Youn
Felipe Balbi
parent
323230ef4e
commit
bea8e86c51
@ -135,7 +135,7 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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if (!hsotg->params.hibernation)
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return -ENOTSUPP;
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pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
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@ -188,7 +188,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->core_params->hibernation)
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if (!hsotg->params.hibernation)
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return -ENOTSUPP;
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/* Backup all registers */
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@ -541,7 +541,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
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addr = hsotg->regs + HAINTMSK;
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dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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if (hsotg->core_params->dma_desc_enable > 0) {
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if (hsotg->params.dma_desc_enable > 0) {
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addr = hsotg->regs + HFLBADDR;
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dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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@ -551,7 +551,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
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dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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for (i = 0; i < hsotg->core_params->host_channels; i++) {
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for (i = 0; i < hsotg->params.host_channels; i++) {
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dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
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addr = hsotg->regs + HCCHAR(i);
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dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
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@ -571,7 +571,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
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addr = hsotg->regs + HCDMA(i);
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dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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if (hsotg->core_params->dma_desc_enable > 0) {
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if (hsotg->params.dma_desc_enable > 0) {
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addr = hsotg->regs + HCDMAB(i);
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dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
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(unsigned long)addr, dwc2_readl(addr));
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@ -753,7 +753,7 @@ bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
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u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
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{
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return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
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return hsotg->params.otg_ver == 1 ? 0x0200 : 0x0103;
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}
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bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
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@ -850,7 +850,7 @@ struct dwc2_hsotg {
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/** Params detected from hardware */
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struct dwc2_hw_params hw_params;
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/** Params to actually use */
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struct dwc2_core_params *core_params;
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struct dwc2_core_params params;
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enum usb_otg_state op_state;
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enum usb_dr_mode dr_mode;
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unsigned int hcd_enabled:1;
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@ -159,9 +159,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
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" ++OTG Interrupt: Session Request Success Status Change++\n");
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gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
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if (gotgctl & GOTGCTL_SESREQSCS) {
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if (hsotg->core_params->phy_type ==
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if (hsotg->params.phy_type ==
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DWC2_PHY_TYPE_PARAM_FS
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&& hsotg->core_params->i2c_enable > 0) {
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&& hsotg->params.i2c_enable > 0) {
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hsotg->srp_success = 1;
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} else {
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/* Clear Session Request */
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@ -370,7 +370,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
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/* Change to L0 state */
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hsotg->lx_state = DWC2_L0;
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} else {
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if (hsotg->core_params->hibernation)
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if (hsotg->params.hibernation)
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return;
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if (hsotg->lx_state != DWC2_L1) {
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@ -2557,7 +2557,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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GINTSTS_USBSUSP | GINTSTS_WKUPINT |
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GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
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if (hsotg->core_params->external_id_pin_ctl <= 0)
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if (hsotg->params.external_id_pin_ctl <= 0)
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intmsk |= GINTSTS_CONIDSTSCHNG;
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dwc2_writel(intmsk, hsotg->regs + GINTMSK);
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@ -79,9 +79,9 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
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/* Enable the interrupts in the GINTMSK */
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intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
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if (hsotg->core_params->dma_enable <= 0)
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if (hsotg->params.dma_enable <= 0)
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intmsk |= GINTSTS_RXFLVL;
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if (hsotg->core_params->external_id_pin_ctl <= 0)
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if (hsotg->params.external_id_pin_ctl <= 0)
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intmsk |= GINTSTS_CONIDSTSCHNG;
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intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
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@ -100,8 +100,8 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
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if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
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hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
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hsotg->core_params->ulpi_fs_ls > 0) ||
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hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
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hsotg->params.ulpi_fs_ls > 0) ||
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hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
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/* Full speed PHY */
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val = HCFG_FSLSPCLKSEL_48_MHZ;
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} else {
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@ -152,7 +152,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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if (dwc2_is_host_mode(hsotg))
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dwc2_init_fs_ls_pclk_sel(hsotg);
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if (hsotg->core_params->i2c_enable > 0) {
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if (hsotg->params.i2c_enable > 0) {
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dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
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/* Program GUSBCFG.OtgUtmiFsSel to I2C */
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@ -189,20 +189,20 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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* so only program the first time. Do a soft reset immediately after
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* setting phyif.
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*/
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switch (hsotg->core_params->phy_type) {
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switch (hsotg->params.phy_type) {
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case DWC2_PHY_TYPE_PARAM_ULPI:
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/* ULPI interface */
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dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
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usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
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usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
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if (hsotg->core_params->phy_ulpi_ddr > 0)
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if (hsotg->params.phy_ulpi_ddr > 0)
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usbcfg |= GUSBCFG_DDRSEL;
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break;
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case DWC2_PHY_TYPE_PARAM_UTMI:
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/* UTMI+ interface */
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dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
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usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
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if (hsotg->core_params->phy_utmi_width == 16)
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if (hsotg->params.phy_utmi_width == 16)
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usbcfg |= GUSBCFG_PHYIF16;
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break;
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default:
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@ -230,8 +230,8 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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u32 usbcfg;
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int retval = 0;
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if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
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hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
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if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL &&
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hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
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/* If FS mode with FS PHY */
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retval = dwc2_fs_phy_init(hsotg, select_phy);
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if (retval)
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@ -245,7 +245,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
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hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
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hsotg->core_params->ulpi_fs_ls > 0) {
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hsotg->params.ulpi_fs_ls > 0) {
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dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
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usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
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usbcfg |= GUSBCFG_ULPI_FS_LS;
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@ -272,9 +272,9 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
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case GHWCFG2_INT_DMA_ARCH:
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dev_dbg(hsotg->dev, "Internal DMA Mode\n");
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if (hsotg->core_params->ahbcfg != -1) {
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if (hsotg->params.ahbcfg != -1) {
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ahbcfg &= GAHBCFG_CTRL_MASK;
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ahbcfg |= hsotg->core_params->ahbcfg &
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ahbcfg |= hsotg->params.ahbcfg &
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~GAHBCFG_CTRL_MASK;
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}
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break;
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@ -286,20 +286,20 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
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}
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dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
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hsotg->core_params->dma_enable,
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hsotg->core_params->dma_desc_enable);
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hsotg->params.dma_enable,
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hsotg->params.dma_desc_enable);
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if (hsotg->core_params->dma_enable > 0) {
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if (hsotg->core_params->dma_desc_enable > 0)
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if (hsotg->params.dma_enable > 0) {
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if (hsotg->params.dma_desc_enable > 0)
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dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
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else
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dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
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} else {
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dev_dbg(hsotg->dev, "Using Slave mode\n");
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hsotg->core_params->dma_desc_enable = 0;
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hsotg->params.dma_desc_enable = 0;
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}
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if (hsotg->core_params->dma_enable > 0)
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if (hsotg->params.dma_enable > 0)
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ahbcfg |= GAHBCFG_DMA_EN;
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dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
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@ -316,10 +316,10 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
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switch (hsotg->hw_params.op_mode) {
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case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
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if (hsotg->core_params->otg_cap ==
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if (hsotg->params.otg_cap ==
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DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
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usbcfg |= GUSBCFG_HNPCAP;
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if (hsotg->core_params->otg_cap !=
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if (hsotg->params.otg_cap !=
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DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
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usbcfg |= GUSBCFG_SRPCAP;
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break;
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@ -327,7 +327,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
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case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
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case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
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case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
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if (hsotg->core_params->otg_cap !=
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if (hsotg->params.otg_cap !=
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DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
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usbcfg |= GUSBCFG_SRPCAP;
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break;
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@ -390,7 +390,7 @@ static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
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*/
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static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_core_params *params = hsotg->core_params;
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struct dwc2_core_params *params = &hsotg->params;
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struct dwc2_hw_params *hw = &hsotg->hw_params;
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u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
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@ -449,7 +449,7 @@ static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
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static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_core_params *params = hsotg->core_params;
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struct dwc2_core_params *params = &hsotg->params;
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u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
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if (!params->enable_dynamic_fifo)
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@ -490,7 +490,7 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
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dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
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dwc2_readl(hsotg->regs + HPTXFSIZ));
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if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
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if (hsotg->params.en_multiple_tx_fifo > 0 &&
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hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
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/*
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* Global DFIFOCFG calculation for Host mode -
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@ -598,7 +598,7 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
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struct dwc2_host_chan *chan)
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{
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#ifdef VERBOSE_DEBUG
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int num_channels = hsotg->core_params->host_channels;
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int num_channels = hsotg->params.host_channels;
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struct dwc2_qh *qh;
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u32 hcchar;
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u32 hcsplt;
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@ -741,7 +741,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
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* For Descriptor DMA mode core halts the channel on AHB error.
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* Interrupt is not required.
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*/
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if (hsotg->core_params->dma_desc_enable <= 0) {
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if (hsotg->params.dma_desc_enable <= 0) {
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "desc DMA disabled\n");
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hcintmsk |= HCINTMSK_AHBERR;
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@ -774,7 +774,7 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
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{
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u32 intmsk;
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if (hsotg->core_params->dma_enable > 0) {
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if (hsotg->params.dma_enable > 0) {
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "DMA enabled\n");
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dwc2_hc_enable_dma_ints(hsotg, chan);
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@ -994,7 +994,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
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/* No need to set the bit in DDMA for disabling the channel */
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/* TODO check it everywhere channel is disabled */
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if (hsotg->core_params->dma_desc_enable <= 0) {
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if (hsotg->params.dma_desc_enable <= 0) {
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "desc DMA disabled\n");
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hcchar |= HCCHAR_CHENA;
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@ -1004,7 +1004,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
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}
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hcchar |= HCCHAR_CHDIS;
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if (hsotg->core_params->dma_enable <= 0) {
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if (hsotg->params.dma_enable <= 0) {
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "DMA not enabled\n");
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hcchar |= HCCHAR_CHENA;
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@ -1143,7 +1143,7 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
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fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
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TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
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bytes_in_fifo = sizeof(u32) *
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(hsotg->core_params->host_perio_tx_fifo_size -
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(hsotg->params.host_perio_tx_fifo_size -
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fifo_space);
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/*
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@ -1339,8 +1339,8 @@ static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
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static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
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struct dwc2_host_chan *chan)
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{
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u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
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u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
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u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
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u16 max_hc_pkt_count = hsotg->params.max_packet_count;
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u32 hcchar;
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u32 hctsiz = 0;
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u16 num_packets;
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@ -1350,7 +1350,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
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dev_vdbg(hsotg->dev, "%s()\n", __func__);
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if (chan->do_ping) {
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if (hsotg->core_params->dma_enable <= 0) {
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if (hsotg->params.dma_enable <= 0) {
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if (dbg_hc(chan))
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dev_vdbg(hsotg->dev, "ping, no DMA\n");
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dwc2_hc_do_ping(hsotg, chan);
|
||||
@ -1478,7 +1478,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
|
||||
TSIZ_SC_MC_PID_SHIFT);
|
||||
}
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
dwc2_writel((u32)chan->xfer_dma,
|
||||
hsotg->regs + HCDMA(chan->hc_num));
|
||||
if (dbg_hc(chan))
|
||||
@ -1521,7 +1521,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
|
||||
chan->xfer_started = 1;
|
||||
chan->requests++;
|
||||
|
||||
if (hsotg->core_params->dma_enable <= 0 &&
|
||||
if (hsotg->params.dma_enable <= 0 &&
|
||||
!chan->ep_is_in && chan->xfer_len > 0)
|
||||
/* Load OUT packet into the appropriate Tx FIFO */
|
||||
dwc2_hc_write_packet(hsotg, chan);
|
||||
@ -1799,12 +1799,12 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
|
||||
/* Must be called with interrupt disabled and spinlock held */
|
||||
static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
|
||||
{
|
||||
int num_channels = hsotg->core_params->host_channels;
|
||||
int num_channels = hsotg->params.host_channels;
|
||||
struct dwc2_host_chan *channel;
|
||||
u32 hcchar;
|
||||
int i;
|
||||
|
||||
if (hsotg->core_params->dma_enable <= 0) {
|
||||
if (hsotg->params.dma_enable <= 0) {
|
||||
/* Flush out any channel requests in slave mode */
|
||||
for (i = 0; i < num_channels; i++) {
|
||||
channel = hsotg->hc_ptr_array[i];
|
||||
@ -1840,9 +1840,9 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
|
||||
channel->qh = NULL;
|
||||
}
|
||||
/* All channels have been freed, mark them available */
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
hsotg->available_host_channels =
|
||||
hsotg->core_params->host_channels;
|
||||
hsotg->params.host_channels;
|
||||
} else {
|
||||
hsotg->non_periodic_channels = 0;
|
||||
hsotg->periodic_channels = 0;
|
||||
@ -2077,7 +2077,7 @@ static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
|
||||
* Free the QTD and clean up the associated QH. Leave the QH in the
|
||||
* schedule if it has any remaining QTDs.
|
||||
*/
|
||||
if (hsotg->core_params->dma_desc_enable <= 0) {
|
||||
if (hsotg->params.dma_desc_enable <= 0) {
|
||||
u8 in_process = urb_qtd->in_process;
|
||||
|
||||
dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
|
||||
@ -2185,13 +2185,13 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
|
||||
|
||||
/* Set ULPI External VBUS bit if needed */
|
||||
usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
|
||||
if (hsotg->core_params->phy_ulpi_ext_vbus ==
|
||||
if (hsotg->params.phy_ulpi_ext_vbus ==
|
||||
DWC2_PHY_ULPI_EXTERNAL_VBUS)
|
||||
usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
|
||||
|
||||
/* Set external TS Dline pulsing bit if needed */
|
||||
usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
|
||||
if (hsotg->core_params->ts_dline > 0)
|
||||
if (hsotg->params.ts_dline > 0)
|
||||
usbcfg |= GUSBCFG_TERMSELDLPULSE;
|
||||
|
||||
dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
|
||||
@ -2230,10 +2230,10 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
|
||||
/* Program the GOTGCTL register */
|
||||
otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
|
||||
otgctl &= ~GOTGCTL_OTGVER;
|
||||
if (hsotg->core_params->otg_ver > 0)
|
||||
if (hsotg->params.otg_ver > 0)
|
||||
otgctl |= GOTGCTL_OTGVER;
|
||||
dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
|
||||
dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
|
||||
dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->params.otg_ver);
|
||||
|
||||
/* Clear the SRP success bit for FS-I2c */
|
||||
hsotg->srp_success = 0;
|
||||
@ -2277,7 +2277,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
|
||||
|
||||
/* Initialize Host Configuration Register */
|
||||
dwc2_init_fs_ls_pclk_sel(hsotg);
|
||||
if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
|
||||
if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL) {
|
||||
hcfg = dwc2_readl(hsotg->regs + HCFG);
|
||||
hcfg |= HCFG_FSLSSUPP;
|
||||
dwc2_writel(hcfg, hsotg->regs + HCFG);
|
||||
@ -2288,13 +2288,13 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
|
||||
* runtime. This bit needs to be programmed during initial configuration
|
||||
* and its value must not be changed during runtime.
|
||||
*/
|
||||
if (hsotg->core_params->reload_ctl > 0) {
|
||||
if (hsotg->params.reload_ctl > 0) {
|
||||
hfir = dwc2_readl(hsotg->regs + HFIR);
|
||||
hfir |= HFIR_RLDCTRL;
|
||||
dwc2_writel(hfir, hsotg->regs + HFIR);
|
||||
}
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
u32 op_mode = hsotg->hw_params.op_mode;
|
||||
|
||||
if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
|
||||
@ -2306,7 +2306,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
|
||||
"Hardware does not support descriptor DMA mode -\n");
|
||||
dev_err(hsotg->dev,
|
||||
"falling back to buffer DMA mode.\n");
|
||||
hsotg->core_params->dma_desc_enable = 0;
|
||||
hsotg->params.dma_desc_enable = 0;
|
||||
} else {
|
||||
hcfg = dwc2_readl(hsotg->regs + HCFG);
|
||||
hcfg |= HCFG_DESCDMA;
|
||||
@ -2332,12 +2332,12 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
|
||||
otgctl &= ~GOTGCTL_HSTSETHNPEN;
|
||||
dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable <= 0) {
|
||||
if (hsotg->params.dma_desc_enable <= 0) {
|
||||
int num_channels, i;
|
||||
u32 hcchar;
|
||||
|
||||
/* Flush out any leftover queued requests */
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
for (i = 0; i < num_channels; i++) {
|
||||
hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
|
||||
hcchar &= ~HCCHAR_CHENA;
|
||||
@ -2399,9 +2399,9 @@ static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
|
||||
hsotg->flags.d32 = 0;
|
||||
hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
|
||||
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
hsotg->available_host_channels =
|
||||
hsotg->core_params->host_channels;
|
||||
hsotg->params.host_channels;
|
||||
} else {
|
||||
hsotg->non_periodic_channels = 0;
|
||||
hsotg->periodic_channels = 0;
|
||||
@ -2415,7 +2415,7 @@ static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
|
||||
hc_list_entry)
|
||||
list_del_init(&chan->hc_list_entry);
|
||||
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
for (i = 0; i < num_channels; i++) {
|
||||
chan = hsotg->hc_ptr_array[i];
|
||||
list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
|
||||
@ -2457,7 +2457,7 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
|
||||
chan->do_ping = 0;
|
||||
chan->ep_is_in = 0;
|
||||
chan->data_pid_start = DWC2_HC_PID_SETUP;
|
||||
if (hsotg->core_params->dma_enable > 0)
|
||||
if (hsotg->params.dma_enable > 0)
|
||||
chan->xfer_dma = urb->setup_dma;
|
||||
else
|
||||
chan->xfer_buf = urb->setup_packet;
|
||||
@ -2484,7 +2484,7 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
|
||||
chan->do_ping = 0;
|
||||
chan->data_pid_start = DWC2_HC_PID_DATA1;
|
||||
chan->xfer_len = 0;
|
||||
if (hsotg->core_params->dma_enable > 0)
|
||||
if (hsotg->params.dma_enable > 0)
|
||||
chan->xfer_dma = hsotg->status_buf_dma;
|
||||
else
|
||||
chan->xfer_buf = hsotg->status_buf;
|
||||
@ -2502,13 +2502,13 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
|
||||
|
||||
case USB_ENDPOINT_XFER_ISOC:
|
||||
chan->ep_type = USB_ENDPOINT_XFER_ISOC;
|
||||
if (hsotg->core_params->dma_desc_enable > 0)
|
||||
if (hsotg->params.dma_desc_enable > 0)
|
||||
break;
|
||||
|
||||
frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
|
||||
frame_desc->status = 0;
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
chan->xfer_dma = urb->dma;
|
||||
chan->xfer_dma += frame_desc->offset +
|
||||
qtd->isoc_split_offset;
|
||||
@ -2690,7 +2690,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
!dwc2_hcd_is_pipe_in(&urb->pipe_info))
|
||||
urb->actual_length = urb->length;
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0)
|
||||
if (hsotg->params.dma_enable > 0)
|
||||
chan->xfer_dma = urb->dma + urb->actual_length;
|
||||
else
|
||||
chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
|
||||
@ -2715,7 +2715,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
*/
|
||||
chan->multi_count = dwc2_hb_mult(qh->maxp);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
chan->desc_list_addr = qh->desc_list_dma;
|
||||
chan->desc_list_sz = qh->desc_list_sz;
|
||||
}
|
||||
@ -2752,7 +2752,7 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions(
|
||||
while (qh_ptr != &hsotg->periodic_sched_ready) {
|
||||
if (list_empty(&hsotg->free_hc_list))
|
||||
break;
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
if (hsotg->available_host_channels <= 1)
|
||||
break;
|
||||
hsotg->available_host_channels--;
|
||||
@ -2776,17 +2776,17 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions(
|
||||
* schedule. Some free host channels may not be used if they are
|
||||
* reserved for periodic transfers.
|
||||
*/
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
qh_ptr = hsotg->non_periodic_sched_inactive.next;
|
||||
while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
|
||||
if (hsotg->core_params->uframe_sched <= 0 &&
|
||||
if (hsotg->params.uframe_sched <= 0 &&
|
||||
hsotg->non_periodic_channels >= num_channels -
|
||||
hsotg->periodic_channels)
|
||||
break;
|
||||
if (list_empty(&hsotg->free_hc_list))
|
||||
break;
|
||||
qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
if (hsotg->available_host_channels < 1)
|
||||
break;
|
||||
hsotg->available_host_channels--;
|
||||
@ -2808,7 +2808,7 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions(
|
||||
else
|
||||
ret_val = DWC2_TRANSACTION_ALL;
|
||||
|
||||
if (hsotg->core_params->uframe_sched <= 0)
|
||||
if (hsotg->params.uframe_sched <= 0)
|
||||
hsotg->non_periodic_channels++;
|
||||
}
|
||||
|
||||
@ -2847,8 +2847,8 @@ static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
|
||||
list_move_tail(&chan->split_order_list_entry,
|
||||
&hsotg->split_order);
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
if (!chan->xfer_started ||
|
||||
chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
|
||||
dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
|
||||
@ -2957,7 +2957,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
|
||||
* The flag prevents any halts to get into the request queue in
|
||||
* the middle of multiple high-bandwidth packets getting queued.
|
||||
*/
|
||||
if (hsotg->core_params->dma_enable <= 0 &&
|
||||
if (hsotg->params.dma_enable <= 0 &&
|
||||
qh->channel->multi_count > 1)
|
||||
hsotg->queuing_high_bandwidth = 1;
|
||||
|
||||
@ -2976,7 +2976,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
|
||||
* controller automatically handles multiple packets for
|
||||
* high-bandwidth transfers.
|
||||
*/
|
||||
if (hsotg->core_params->dma_enable > 0 || status == 0 ||
|
||||
if (hsotg->params.dma_enable > 0 || status == 0 ||
|
||||
qh->channel->requests == qh->channel->multi_count) {
|
||||
qh_ptr = qh_ptr->next;
|
||||
/*
|
||||
@ -2993,7 +2993,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
|
||||
|
||||
exit:
|
||||
if (no_queue_space || no_fifo_space ||
|
||||
(hsotg->core_params->dma_enable <= 0 &&
|
||||
(hsotg->params.dma_enable <= 0 &&
|
||||
!list_empty(&hsotg->periodic_sched_assigned))) {
|
||||
/*
|
||||
* May need to queue more transactions as the request
|
||||
@ -3073,7 +3073,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
|
||||
tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
|
||||
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
|
||||
TXSTS_QSPCAVAIL_SHIFT;
|
||||
if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
|
||||
if (hsotg->params.dma_enable <= 0 && qspcavail == 0) {
|
||||
no_queue_space = 1;
|
||||
break;
|
||||
}
|
||||
@ -3106,7 +3106,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
|
||||
hsotg->non_periodic_qh_ptr->next;
|
||||
} while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
|
||||
|
||||
if (hsotg->core_params->dma_enable <= 0) {
|
||||
if (hsotg->params.dma_enable <= 0) {
|
||||
tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
|
||||
qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
|
||||
TXSTS_QSPCAVAIL_SHIFT;
|
||||
@ -3307,7 +3307,7 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
|
||||
* If hibernation is supported, Phy clock will be suspended
|
||||
* after registers are backuped.
|
||||
*/
|
||||
if (!hsotg->core_params->hibernation) {
|
||||
if (!hsotg->params.hibernation) {
|
||||
/* Suspend the Phy Clock */
|
||||
pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
|
||||
pcgctl |= PCGCTL_STOPPCLK;
|
||||
@ -3342,7 +3342,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
|
||||
* If hibernation is supported, Phy clock is already resumed
|
||||
* after registers restore.
|
||||
*/
|
||||
if (!hsotg->core_params->hibernation) {
|
||||
if (!hsotg->params.hibernation) {
|
||||
pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
|
||||
pcgctl &= ~PCGCTL_STOPPCLK;
|
||||
dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
|
||||
@ -3569,7 +3569,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
|
||||
port_status |= USB_PORT_STAT_TEST;
|
||||
/* USB_PORT_FEAT_INDICATOR unsupported always 0 */
|
||||
|
||||
if (hsotg->core_params->dma_desc_fs_enable) {
|
||||
if (hsotg->params.dma_desc_fs_enable) {
|
||||
/*
|
||||
* Enable descriptor DMA only if a full speed
|
||||
* device is connected.
|
||||
@ -3583,7 +3583,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
|
||||
u32 hcfg;
|
||||
|
||||
dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
|
||||
hsotg->core_params->dma_desc_enable = 1;
|
||||
hsotg->params.dma_desc_enable = 1;
|
||||
hcfg = dwc2_readl(hsotg->regs + HCFG);
|
||||
hcfg |= HCFG_DESCDMA;
|
||||
dwc2_writel(hcfg, hsotg->regs + HCFG);
|
||||
@ -3824,7 +3824,7 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
|
||||
u32 p_tx_status;
|
||||
int i;
|
||||
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
dev_dbg(hsotg->dev, "\n");
|
||||
dev_dbg(hsotg->dev,
|
||||
"************************************************************\n");
|
||||
@ -4365,7 +4365,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
|
||||
if (!HCD_HW_ACCESSIBLE(hcd))
|
||||
goto unlock;
|
||||
|
||||
if (!hsotg->core_params->hibernation)
|
||||
if (!hsotg->params.hibernation)
|
||||
goto skip_power_saving;
|
||||
|
||||
/*
|
||||
@ -4417,7 +4417,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
|
||||
if (hsotg->lx_state != DWC2_L2)
|
||||
goto unlock;
|
||||
|
||||
if (!hsotg->core_params->hibernation) {
|
||||
if (!hsotg->params.hibernation) {
|
||||
hsotg->lx_state = DWC2_L0;
|
||||
goto unlock;
|
||||
}
|
||||
@ -4919,7 +4919,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
|
||||
}
|
||||
}
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
if (hsotg->status_buf) {
|
||||
dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
|
||||
hsotg->status_buf,
|
||||
@ -4999,16 +4999,16 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
hsotg->last_frame_num = HFNUM_MAX_FRNUM;
|
||||
|
||||
/* Check if the bus driver or platform code has setup a dma_mask */
|
||||
if (hsotg->core_params->dma_enable > 0 &&
|
||||
if (hsotg->params.dma_enable > 0 &&
|
||||
hsotg->dev->dma_mask == NULL) {
|
||||
dev_warn(hsotg->dev,
|
||||
"dma_mask not set, disabling DMA\n");
|
||||
hsotg->core_params->dma_enable = 0;
|
||||
hsotg->core_params->dma_desc_enable = 0;
|
||||
hsotg->params.dma_enable = 0;
|
||||
hsotg->params.dma_desc_enable = 0;
|
||||
}
|
||||
|
||||
/* Set device flags indicating whether the HCD supports DMA */
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
|
||||
dev_warn(hsotg->dev, "can't set DMA mask\n");
|
||||
if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
|
||||
@ -5019,7 +5019,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
if (!hcd)
|
||||
goto error1;
|
||||
|
||||
if (hsotg->core_params->dma_enable <= 0)
|
||||
if (hsotg->params.dma_enable <= 0)
|
||||
hcd->self.uses_dma = 0;
|
||||
|
||||
hcd->has_tt = 1;
|
||||
@ -5067,7 +5067,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
* in the controller. Initialize the channel descriptor array.
|
||||
*/
|
||||
INIT_LIST_HEAD(&hsotg->free_hc_list);
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
|
||||
|
||||
for (i = 0; i < num_channels; i++) {
|
||||
@ -5091,7 +5091,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
* done after usb_add_hcd since that function allocates the DMA buffer
|
||||
* pool.
|
||||
*/
|
||||
if (hsotg->core_params->dma_enable > 0)
|
||||
if (hsotg->params.dma_enable > 0)
|
||||
hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
|
||||
DWC2_HCD_STATUS_BUF_SIZE,
|
||||
&hsotg->status_buf_dma, GFP_KERNEL);
|
||||
@ -5107,8 +5107,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
* DMA mode.
|
||||
* Alignment must be set to 512 bytes.
|
||||
*/
|
||||
if (hsotg->core_params->dma_desc_enable ||
|
||||
hsotg->core_params->dma_desc_fs_enable) {
|
||||
if (hsotg->params.dma_desc_enable ||
|
||||
hsotg->params.dma_desc_fs_enable) {
|
||||
hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
|
||||
sizeof(struct dwc2_hcd_dma_desc) *
|
||||
MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
|
||||
@ -5121,8 +5121,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
* Disable descriptor dma mode since it will not be
|
||||
* usable.
|
||||
*/
|
||||
hsotg->core_params->dma_desc_enable = 0;
|
||||
hsotg->core_params->dma_desc_fs_enable = 0;
|
||||
hsotg->params.dma_desc_enable = 0;
|
||||
hsotg->params.dma_desc_fs_enable = 0;
|
||||
}
|
||||
|
||||
hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
|
||||
@ -5138,8 +5138,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
|
||||
* Disable descriptor dma mode since it will not be
|
||||
* usable.
|
||||
*/
|
||||
hsotg->core_params->dma_desc_enable = 0;
|
||||
hsotg->core_params->dma_desc_fs_enable = 0;
|
||||
hsotg->params.dma_desc_enable = 0;
|
||||
hsotg->params.dma_desc_fs_enable = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -5249,7 +5249,7 @@ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
|
||||
hr = &hsotg->hr_backup;
|
||||
hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
|
||||
hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
|
||||
for (i = 0; i < hsotg->core_params->host_channels; ++i)
|
||||
for (i = 0; i < hsotg->params.host_channels; ++i)
|
||||
hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
|
||||
|
||||
hr->hprt0 = dwc2_read_hprt0(hsotg);
|
||||
@ -5285,7 +5285,7 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
|
||||
dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
|
||||
dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
|
||||
|
||||
for (i = 0; i < hsotg->core_params->host_channels; ++i)
|
||||
for (i = 0; i < hsotg->params.host_channels; ++i)
|
||||
dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
|
||||
|
||||
dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
|
||||
|
||||
@ -297,7 +297,7 @@ static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg,
|
||||
struct dwc2_host_chan *chan = qh->channel;
|
||||
|
||||
if (dwc2_qh_is_non_per(qh)) {
|
||||
if (hsotg->core_params->uframe_sched > 0)
|
||||
if (hsotg->params.uframe_sched > 0)
|
||||
hsotg->available_host_channels++;
|
||||
else
|
||||
hsotg->non_periodic_channels--;
|
||||
@ -404,7 +404,7 @@ void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
|
||||
if ((qh->ep_type == USB_ENDPOINT_XFER_ISOC ||
|
||||
qh->ep_type == USB_ENDPOINT_XFER_INT) &&
|
||||
(hsotg->core_params->uframe_sched > 0 ||
|
||||
(hsotg->params.uframe_sched > 0 ||
|
||||
!hsotg->periodic_channels) && hsotg->frame_list) {
|
||||
dwc2_per_sched_disable(hsotg);
|
||||
dwc2_frame_list_free(hsotg);
|
||||
|
||||
@ -256,7 +256,7 @@ static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
|
||||
static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
|
||||
u32 *hprt0_modify)
|
||||
{
|
||||
struct dwc2_core_params *params = hsotg->core_params;
|
||||
struct dwc2_core_params *params = &hsotg->params;
|
||||
int do_reset = 0;
|
||||
u32 usbcfg;
|
||||
u32 prtspd;
|
||||
@ -395,10 +395,10 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
|
||||
dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
|
||||
} else {
|
||||
hsotg->flags.b.port_enable_change = 1;
|
||||
if (hsotg->core_params->dma_desc_fs_enable) {
|
||||
if (hsotg->params.dma_desc_fs_enable) {
|
||||
u32 hcfg;
|
||||
|
||||
hsotg->core_params->dma_desc_enable = 0;
|
||||
hsotg->params.dma_desc_enable = 0;
|
||||
hsotg->new_connection = false;
|
||||
hcfg = dwc2_readl(hsotg->regs + HCFG);
|
||||
hcfg &= ~HCFG_DESCDMA;
|
||||
@ -604,7 +604,7 @@ static enum dwc2_halt_status dwc2_update_isoc_urb_state(
|
||||
/* Skip whole frame */
|
||||
if (chan->qh->do_split &&
|
||||
chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
|
||||
hsotg->core_params->dma_enable > 0) {
|
||||
hsotg->params.dma_enable > 0) {
|
||||
qtd->complete_split = 0;
|
||||
qtd->isoc_split_offset = 0;
|
||||
}
|
||||
@ -743,7 +743,7 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
|
||||
dwc2_hc_cleanup(hsotg, chan);
|
||||
list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
|
||||
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
hsotg->available_host_channels++;
|
||||
} else {
|
||||
switch (chan->ep_type) {
|
||||
@ -789,7 +789,7 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
|
||||
if (dbg_hc(chan))
|
||||
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
if (dbg_hc(chan))
|
||||
dev_vdbg(hsotg->dev, "DMA enabled\n");
|
||||
dwc2_release_channel(hsotg, chan, qtd, halt_status);
|
||||
@ -974,7 +974,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
|
||||
|
||||
pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
|
||||
if (pipe_type == USB_ENDPOINT_XFER_ISOC)
|
||||
/* Do not disable the interrupt, just clear it */
|
||||
@ -985,7 +985,7 @@ static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
|
||||
/* Handle xfer complete on CSPLIT */
|
||||
if (chan->qh->do_split) {
|
||||
if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
|
||||
hsotg->core_params->dma_enable > 0) {
|
||||
hsotg->params.dma_enable > 0) {
|
||||
if (qtd->complete_split &&
|
||||
dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
|
||||
qtd))
|
||||
@ -1097,7 +1097,7 @@ static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
|
||||
dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
|
||||
chnum);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
DWC2_HC_XFER_STALL);
|
||||
goto handle_stall_done;
|
||||
@ -1207,7 +1207,7 @@ static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
|
||||
switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
|
||||
case USB_ENDPOINT_XFER_CONTROL:
|
||||
case USB_ENDPOINT_XFER_BULK:
|
||||
if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
|
||||
if (hsotg->params.dma_enable > 0 && chan->ep_is_in) {
|
||||
/*
|
||||
* NAK interrupts are enabled on bulk/control IN
|
||||
* transfers in DMA mode for the sole purpose of
|
||||
@ -1353,7 +1353,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
|
||||
*/
|
||||
if (chan->do_split && chan->complete_split) {
|
||||
if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
|
||||
hsotg->core_params->dma_enable > 0) {
|
||||
hsotg->params.dma_enable > 0) {
|
||||
qtd->complete_split = 0;
|
||||
qtd->isoc_split_offset = 0;
|
||||
qtd->isoc_frame_index++;
|
||||
@ -1374,7 +1374,7 @@ static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
|
||||
struct dwc2_qh *qh = chan->qh;
|
||||
bool past_end;
|
||||
|
||||
if (hsotg->core_params->uframe_sched <= 0) {
|
||||
if (hsotg->params.uframe_sched <= 0) {
|
||||
int frnum = dwc2_hcd_get_frame_number(hsotg);
|
||||
|
||||
/* Don't have num_hs_transfers; simple logic */
|
||||
@ -1467,7 +1467,7 @@ static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
|
||||
|
||||
dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
DWC2_HC_XFER_BABBLE_ERR);
|
||||
goto disable_int;
|
||||
@ -1572,7 +1572,7 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
|
||||
dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
|
||||
|
||||
/* Core halts the channel for Descriptor DMA mode */
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
DWC2_HC_XFER_AHB_ERR);
|
||||
goto handle_ahberr_done;
|
||||
@ -1604,7 +1604,7 @@ static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
|
||||
|
||||
dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0) {
|
||||
if (hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
DWC2_HC_XFER_XACT_ERR);
|
||||
goto handle_xacterr_done;
|
||||
@ -1798,8 +1798,8 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
|
||||
|
||||
if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
|
||||
(chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
|
||||
hsotg->core_params->dma_desc_enable <= 0)) {
|
||||
if (hsotg->core_params->dma_desc_enable > 0)
|
||||
hsotg->params.dma_desc_enable <= 0)) {
|
||||
if (hsotg->params.dma_desc_enable > 0)
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
chan->halt_status);
|
||||
else
|
||||
@ -1830,7 +1830,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
|
||||
} else if (chan->hcint & HCINTMSK_STALL) {
|
||||
dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
|
||||
} else if ((chan->hcint & HCINTMSK_XACTERR) &&
|
||||
hsotg->core_params->dma_desc_enable <= 0) {
|
||||
hsotg->params.dma_desc_enable <= 0) {
|
||||
if (out_nak_enh) {
|
||||
if (chan->hcint &
|
||||
(HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
|
||||
@ -1850,10 +1850,10 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
|
||||
*/
|
||||
dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
|
||||
} else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
|
||||
hsotg->core_params->dma_desc_enable > 0) {
|
||||
hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
|
||||
} else if ((chan->hcint & HCINTMSK_AHBERR) &&
|
||||
hsotg->core_params->dma_desc_enable > 0) {
|
||||
hsotg->params.dma_desc_enable > 0) {
|
||||
dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
|
||||
} else if (chan->hcint & HCINTMSK_BBLERR) {
|
||||
dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
|
||||
@ -1946,7 +1946,7 @@ static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
|
||||
dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
|
||||
chnum);
|
||||
|
||||
if (hsotg->core_params->dma_enable > 0) {
|
||||
if (hsotg->params.dma_enable > 0) {
|
||||
dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
|
||||
} else {
|
||||
if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
|
||||
@ -2023,7 +2023,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
|
||||
* interrupt unmasked
|
||||
*/
|
||||
WARN_ON(hcint != HCINTMSK_CHHLTD);
|
||||
if (hsotg->core_params->dma_desc_enable > 0)
|
||||
if (hsotg->params.dma_desc_enable > 0)
|
||||
dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
|
||||
chan->halt_status);
|
||||
else
|
||||
@ -2051,7 +2051,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
|
||||
qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
|
||||
qtd_list_entry);
|
||||
|
||||
if (hsotg->core_params->dma_enable <= 0) {
|
||||
if (hsotg->params.dma_enable <= 0) {
|
||||
if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
|
||||
hcint &= ~HCINTMSK_CHHLTD;
|
||||
}
|
||||
@ -2156,7 +2156,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < hsotg->core_params->host_channels; i++) {
|
||||
for (i = 0; i < hsotg->params.host_channels; i++) {
|
||||
if (haint & (1 << i))
|
||||
dwc2_hc_n_intr(hsotg, i);
|
||||
}
|
||||
|
||||
@ -75,7 +75,7 @@ static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
|
||||
int status;
|
||||
int num_channels;
|
||||
|
||||
num_channels = hsotg->core_params->host_channels;
|
||||
num_channels = hsotg->params.host_channels;
|
||||
if (hsotg->periodic_channels + hsotg->non_periodic_channels <
|
||||
num_channels
|
||||
&& hsotg->periodic_channels < num_channels - 1) {
|
||||
@ -1104,7 +1104,7 @@ static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
next_active_frame = earliest_frame;
|
||||
|
||||
/* Get the "no microframe schduler" out of the way... */
|
||||
if (hsotg->core_params->uframe_sched <= 0) {
|
||||
if (hsotg->params.uframe_sched <= 0) {
|
||||
if (qh->do_split)
|
||||
/* Splits are active at microframe 0 minus 1 */
|
||||
next_active_frame |= 0x7;
|
||||
@ -1197,7 +1197,7 @@ static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
{
|
||||
int status;
|
||||
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
status = dwc2_uframe_schedule(hsotg, qh);
|
||||
} else {
|
||||
status = dwc2_periodic_channel_available(hsotg);
|
||||
@ -1218,7 +1218,7 @@ static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
return status;
|
||||
}
|
||||
|
||||
if (hsotg->core_params->uframe_sched <= 0)
|
||||
if (hsotg->params.uframe_sched <= 0)
|
||||
/* Reserve periodic channel */
|
||||
hsotg->periodic_channels++;
|
||||
|
||||
@ -1254,7 +1254,7 @@ static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
/* Update claimed usecs per (micro)frame */
|
||||
hsotg->periodic_usecs -= qh->host_us;
|
||||
|
||||
if (hsotg->core_params->uframe_sched > 0) {
|
||||
if (hsotg->params.uframe_sched > 0) {
|
||||
dwc2_uframe_unschedule(hsotg, qh);
|
||||
} else {
|
||||
/* Release periodic channel reservation */
|
||||
@ -1328,7 +1328,7 @@ static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
|
||||
int status = 0;
|
||||
|
||||
max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
|
||||
max_channel_xfer_size = hsotg->core_params->max_transfer_size;
|
||||
max_channel_xfer_size = hsotg->params.max_transfer_size;
|
||||
|
||||
if (max_xfer_size > max_channel_xfer_size) {
|
||||
dev_err(hsotg->dev,
|
||||
@ -1391,7 +1391,7 @@ static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
|
||||
qh->unreserve_pending = 0;
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0)
|
||||
if (hsotg->params.dma_desc_enable > 0)
|
||||
/* Don't rely on SOF and start in ready schedule */
|
||||
list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
|
||||
else
|
||||
@ -1599,7 +1599,7 @@ struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
|
||||
|
||||
dwc2_qh_init(hsotg, qh, urb, mem_flags);
|
||||
|
||||
if (hsotg->core_params->dma_desc_enable > 0 &&
|
||||
if (hsotg->params.dma_desc_enable > 0 &&
|
||||
dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
|
||||
dwc2_hcd_qh_free(hsotg, qh);
|
||||
return NULL;
|
||||
@ -1711,7 +1711,7 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
|
||||
dwc2_deschedule_periodic(hsotg, qh);
|
||||
hsotg->periodic_qh_count--;
|
||||
if (!hsotg->periodic_qh_count &&
|
||||
hsotg->core_params->dma_desc_enable <= 0) {
|
||||
hsotg->params.dma_desc_enable <= 0) {
|
||||
intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
|
||||
intr_mask &= ~GINTSTS_SOF;
|
||||
dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
|
||||
|
||||
@ -264,7 +264,7 @@ void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->otg_cap = val;
|
||||
hsotg->params.otg_cap = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -285,14 +285,14 @@ void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->dma_enable = val;
|
||||
hsotg->params.dma_enable = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
{
|
||||
int valid = 1;
|
||||
|
||||
if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
|
||||
if (val > 0 && (hsotg->params.dma_enable <= 0 ||
|
||||
!hsotg->hw_params.dma_desc_enable))
|
||||
valid = 0;
|
||||
if (val < 0)
|
||||
@ -303,19 +303,19 @@ void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_err(hsotg->dev,
|
||||
"%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
|
||||
val);
|
||||
val = (hsotg->core_params->dma_enable > 0 &&
|
||||
val = (hsotg->params.dma_enable > 0 &&
|
||||
hsotg->hw_params.dma_desc_enable);
|
||||
dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->dma_desc_enable = val;
|
||||
hsotg->params.dma_desc_enable = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
{
|
||||
int valid = 1;
|
||||
|
||||
if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
|
||||
if (val > 0 && (hsotg->params.dma_enable <= 0 ||
|
||||
!hsotg->hw_params.dma_desc_enable))
|
||||
valid = 0;
|
||||
if (val < 0)
|
||||
@ -326,11 +326,11 @@ void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_err(hsotg->dev,
|
||||
"%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
|
||||
val);
|
||||
val = (hsotg->core_params->dma_enable > 0 &&
|
||||
val = (hsotg->params.dma_enable > 0 &&
|
||||
hsotg->hw_params.dma_desc_enable);
|
||||
}
|
||||
|
||||
hsotg->core_params->dma_desc_fs_enable = val;
|
||||
hsotg->params.dma_desc_fs_enable = val;
|
||||
dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
|
||||
}
|
||||
|
||||
@ -349,7 +349,7 @@ void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
|
||||
"Setting host_support_fs_low_power to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_support_fs_ls_low_power = val;
|
||||
hsotg->params.host_support_fs_ls_low_power = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -370,7 +370,7 @@ void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->enable_dynamic_fifo = val;
|
||||
hsotg->params.enable_dynamic_fifo = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -389,7 +389,7 @@ void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_rx_fifo_size = val;
|
||||
hsotg->params.host_rx_fifo_size = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -409,7 +409,7 @@ void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_nperio_tx_fifo_size = val;
|
||||
hsotg->params.host_nperio_tx_fifo_size = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -429,7 +429,7 @@ void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
|
||||
val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_perio_tx_fifo_size = val;
|
||||
hsotg->params.host_perio_tx_fifo_size = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -448,7 +448,7 @@ void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->max_transfer_size = val;
|
||||
hsotg->params.max_transfer_size = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -467,7 +467,7 @@ void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->max_packet_count = val;
|
||||
hsotg->params.max_packet_count = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -486,7 +486,7 @@ void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_channels = val;
|
||||
hsotg->params.host_channels = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -534,12 +534,12 @@ void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->phy_type = val;
|
||||
hsotg->params.phy_type = val;
|
||||
}
|
||||
|
||||
static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
|
||||
{
|
||||
return hsotg->core_params->phy_type;
|
||||
return hsotg->params.phy_type;
|
||||
}
|
||||
|
||||
void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -568,7 +568,7 @@ void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->speed = val;
|
||||
hsotg->params.speed = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -602,7 +602,7 @@ void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
|
||||
val);
|
||||
}
|
||||
|
||||
hsotg->core_params->host_ls_low_power_phy_clk = val;
|
||||
hsotg->params.host_ls_low_power_phy_clk = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -616,7 +616,7 @@ void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->phy_ulpi_ddr = val;
|
||||
hsotg->params.phy_ulpi_ddr = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -632,7 +632,7 @@ void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->phy_ulpi_ext_vbus = val;
|
||||
hsotg->params.phy_ulpi_ext_vbus = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -662,7 +662,7 @@ void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->phy_utmi_width = val;
|
||||
hsotg->params.phy_utmi_width = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -676,7 +676,7 @@ void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->ulpi_fs_ls = val;
|
||||
hsotg->params.ulpi_fs_ls = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -690,7 +690,7 @@ void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->ts_dline = val;
|
||||
hsotg->params.ts_dline = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -718,7 +718,7 @@ void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->i2c_enable = val;
|
||||
hsotg->params.i2c_enable = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -747,7 +747,7 @@ void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->en_multiple_tx_fifo = val;
|
||||
hsotg->params.en_multiple_tx_fifo = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -775,15 +775,15 @@ void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->reload_ctl = val;
|
||||
hsotg->params.reload_ctl = val;
|
||||
}
|
||||
|
||||
void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
|
||||
{
|
||||
if (val != -1)
|
||||
hsotg->core_params->ahbcfg = val;
|
||||
hsotg->params.ahbcfg = val;
|
||||
else
|
||||
hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
|
||||
hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
|
||||
GAHBCFG_HBSTLEN_SHIFT;
|
||||
}
|
||||
|
||||
@ -800,7 +800,7 @@ void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->otg_ver = val;
|
||||
hsotg->params.otg_ver = val;
|
||||
}
|
||||
|
||||
static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
|
||||
@ -816,7 +816,7 @@ static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
|
||||
dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->uframe_sched = val;
|
||||
hsotg->params.uframe_sched = val;
|
||||
}
|
||||
|
||||
static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
|
||||
@ -833,7 +833,7 @@ static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
|
||||
dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->external_id_pin_ctl = val;
|
||||
hsotg->params.external_id_pin_ctl = val;
|
||||
}
|
||||
|
||||
static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
|
||||
@ -850,7 +850,7 @@ static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
|
||||
dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
|
||||
}
|
||||
|
||||
hsotg->core_params->hibernation = val;
|
||||
hsotg->params.hibernation = val;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -418,12 +418,7 @@ static int dwc2_driver_probe(struct platform_device *dev)
|
||||
|
||||
spin_lock_init(&hsotg->lock);
|
||||
|
||||
hsotg->core_params = devm_kzalloc(&dev->dev,
|
||||
sizeof(*hsotg->core_params), GFP_KERNEL);
|
||||
if (!hsotg->core_params)
|
||||
return -ENOMEM;
|
||||
|
||||
dwc2_set_all_params(hsotg->core_params, -1);
|
||||
dwc2_set_all_params(&hsotg->params, -1);
|
||||
|
||||
hsotg->irq = platform_get_irq(dev, 0);
|
||||
if (hsotg->irq < 0) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user