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mlxsw: pci: Fix size of trap_id field in CQE

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The "trap_id" is 9bits long. So far, this was not a problem since we
used only traps with ids that fit into 8bits. But the ACL traps that are
going to be introduced use the 9th bit.

Fixes: eda6500a98 ("mlxsw: Add PCI bus implementation")
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Yotam Gigi <yotamg@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko 2017-06-06 14:12:04 +02:00 committed by David S. Miller
parent 5a4d1fee2f
commit be8408e144
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
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@ -155,7 +155,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
/* pci_cqe_trap_id
* Trap ID that captured the packet.
*/
MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
/* pci_cqe_crc
* Length include CRC. Indicates the length field includes