mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define the values. Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI memory location control bits. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
c644a11aae
commit
be13e14e31
drivers/staging/comedi/drivers
@ -4004,13 +4004,13 @@ static int auto_attach(struct comedi_device *dev,
|
||||
|
||||
/* figure out what local addresses are */
|
||||
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
|
||||
LRNG_MEM_MASK;
|
||||
PLX_LASRR_MEM_MASK;
|
||||
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
|
||||
local_range & LMAP_MEM_MASK;
|
||||
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
|
||||
~local_range) | local_decode;
|
||||
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
|
||||
LRNG_MEM_MASK;
|
||||
PLX_LASRR_MEM_MASK;
|
||||
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
|
||||
local_range & LMAP_MEM_MASK;
|
||||
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
|
||||
|
@ -54,14 +54,16 @@ struct plx_dma_desc {
|
||||
/* Local Address Space 1 Range Register */
|
||||
#define PLX_REG_LAS1RR 0x00f0
|
||||
|
||||
#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
|
||||
#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
|
||||
#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
|
||||
#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
|
||||
/* bits that specify range for memory io */
|
||||
#define LRNG_MEM_MASK 0xfffffff0
|
||||
/* bits that specify range for normal io */
|
||||
#define LRNG_IO_MASK 0xfffffffc
|
||||
#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
|
||||
#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
|
||||
#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
|
||||
#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
|
||||
#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
|
||||
#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
|
||||
/* bits that specify range for memory space decode bits */
|
||||
#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
|
||||
/* bits that specify range for i/o space decode bits */
|
||||
#define PLX_LASRR_IO_MASK GENMASK(31, 2)
|
||||
|
||||
/* Local Address Space 0 Local Base Address (Remap) Register */
|
||||
#define PLX_REG_LAS0BA 0x0004
|
||||
|
Loading…
Reference in New Issue
Block a user