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iwlwifi: 3945 extract flow handler definitions into iwl-3945-fh.h
This patch moves 3945 definitions into iwl-3945-fh.h It renames FH_ to FH39 to help inclusion of 3945 into iwlcore framework Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Tomas Winkler
John W. Linville
parent
7cbf0ba519
commit
bddadf86fb
178
drivers/net/wireless/iwlwifi/iwl-3945-fh.h
Normal file
178
drivers/net/wireless/iwlwifi/iwl-3945-fh.h
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@ -0,0 +1,178 @@
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __iwl_3945_fh_h__
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#define __iwl_3945_fh_h__
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/************************************/
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/* iwl3945 Flow Handler Definitions */
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/************************************/
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/**
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* This I/O area is directly read/writable by driver (e.g. Linux uses writel())
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* Addresses are offsets from device's PCI hardware base address.
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*/
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#define FH39_MEM_LOWER_BOUND (0x0800)
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#define FH39_MEM_UPPER_BOUND (0x1000)
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#define FH39_CBCC_TABLE (FH39_MEM_LOWER_BOUND + 0x140)
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#define FH39_TFDB_TABLE (FH39_MEM_LOWER_BOUND + 0x180)
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#define FH39_RCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x400)
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#define FH39_RSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x4c0)
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#define FH39_TCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x500)
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#define FH39_TSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x680)
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/* TFDB (Transmit Frame Buffer Descriptor) */
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#define FH39_TFDB(_ch, buf) (FH39_TFDB_TABLE + \
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((_ch) * 2 + (buf)) * 0x28)
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#define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TABLE + 0x50 * (_ch))
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/* CBCC channel is [0,2] */
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#define FH39_CBCC(_ch) (FH39_CBCC_TABLE + (_ch) * 0x8)
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#define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00)
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#define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04)
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/* RCSR channel is [0,2] */
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#define FH39_RCSR(_ch) (FH39_RCSR_TABLE + (_ch) * 0x40)
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#define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00)
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#define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04)
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#define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20)
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#define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24)
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#define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0))
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/* RSSR */
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#define FH39_RSSR_CTRL (FH39_RSSR_TABLE + 0x000)
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#define FH39_RSSR_STATUS (FH39_RSSR_TABLE + 0x004)
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/* TCSR */
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#define FH39_TCSR(_ch) (FH39_TCSR_TABLE + (_ch) * 0x20)
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#define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00)
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#define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04)
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#define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08)
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/* TSSR */
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#define FH39_TSSR_CBB_BASE (FH39_TSSR_TABLE + 0x000)
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#define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TABLE + 0x008)
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#define FH39_TSSR_TX_STATUS (FH39_TSSR_TABLE + 0x010)
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/* DBM */
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#define FH39_SRVC_CHNL (6)
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#define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
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#define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
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#define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
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#define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
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#define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24)
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#define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16)
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#define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \
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(FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \
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FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch))
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#define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
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#define TFD_QUEUE_SIZE_MAX (256)
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#endif /* __iwl_3945_fh_h__ */
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@ -288,107 +288,6 @@ struct iwl3945_eeprom {
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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/*=== FH (data Flow Handler) ===*/
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#define FH_BASE (0x800)
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#define FH_CBCC_TABLE (FH_BASE+0x140)
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#define FH_TFDB_TABLE (FH_BASE+0x180)
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#define FH_RCSR_TABLE (FH_BASE+0x400)
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#define FH_RSSR_TABLE (FH_BASE+0x4c0)
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#define FH_TCSR_TABLE (FH_BASE+0x500)
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#define FH_TSSR_TABLE (FH_BASE+0x680)
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/* TFDB (Transmit Frame Buffer Descriptor) */
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#define FH_TFDB(_channel, buf) \
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(FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
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#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
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(FH_TFDB_TABLE + 0x50 * _channel)
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/* CBCC _channel is [0,2] */
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#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
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#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
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#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
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/* RCSR _channel is [0,2] */
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#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
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#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
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#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
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#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
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#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
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#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
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/* RSSR */
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#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
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#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
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#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
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/* TCSR */
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#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
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#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
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#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
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#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
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/* TSSR */
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#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
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#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
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#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
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/* DBM */
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#define ALM_FH_SRVC_CHNL (6)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
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#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
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((1LU << _channel) << 24)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
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((1LU << _channel) << 16)
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#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
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(ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
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ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
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#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
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#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
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@ -39,6 +39,7 @@
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#include <net/mac80211.h>
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#include "iwl-3945-core.h"
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#include "iwl-3945-fh.h"
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#include "iwl-3945.h"
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#include "iwl-helpers.h"
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#include "iwl-3945-rs.h"
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@ -984,23 +985,23 @@ static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *r
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return rc;
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}
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iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
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iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
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iwl3945_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
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iwl3945_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
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priv->hw_setting.shared_phys +
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offsetof(struct iwl3945_shared, rx_read_ptr[0]));
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iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
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iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
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ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
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ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
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ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
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ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
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(RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
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ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
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(1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
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ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
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iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
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iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0),
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FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
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FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
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FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
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FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
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(RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
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FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
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(1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
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FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
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/* fake read to flush all prev I/O */
|
||||
iwl3945_read_direct32(priv, FH_RSSR_CTRL);
|
||||
iwl3945_read_direct32(priv, FH39_RSSR_CTRL);
|
||||
|
||||
iwl3945_release_nic_access(priv);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
@ -1034,17 +1035,17 @@ static int iwl3945_tx_reset(struct iwl3945_priv *priv)
|
||||
iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
|
||||
iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
|
||||
|
||||
iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
|
||||
iwl3945_write_direct32(priv, FH39_TSSR_CBB_BASE,
|
||||
priv->hw_setting.shared_phys);
|
||||
|
||||
iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
|
||||
ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
|
||||
iwl3945_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
|
||||
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
|
||||
|
||||
iwl3945_release_nic_access(priv);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
@ -1210,7 +1211,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
return rc;
|
||||
}
|
||||
iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
|
||||
iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
|
||||
iwl3945_release_nic_access(priv);
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
@ -1240,7 +1241,7 @@ void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
|
||||
|
||||
void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
|
||||
{
|
||||
int queue;
|
||||
int txq_id;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&priv->lock, flags);
|
||||
@ -1254,10 +1255,10 @@ void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
|
||||
iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
|
||||
|
||||
/* reset TFD queues */
|
||||
for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
|
||||
iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
|
||||
iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
|
||||
ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
|
||||
for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
|
||||
iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
|
||||
iwl3945_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
|
||||
FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
|
||||
1000);
|
||||
}
|
||||
|
||||
@ -2307,9 +2308,9 @@ int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
|
||||
return rc;
|
||||
}
|
||||
|
||||
iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
|
||||
rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS,
|
||||
FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
|
||||
iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
|
||||
rc = iwl3945_poll_direct_bit(priv, FH39_RSSR_STATUS,
|
||||
FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
|
||||
if (rc < 0)
|
||||
IWL_ERROR("Can't stop Rx DMA.\n");
|
||||
|
||||
@ -2335,19 +2336,19 @@ int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
return rc;
|
||||
}
|
||||
iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
|
||||
iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
|
||||
iwl3945_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
|
||||
iwl3945_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
|
||||
|
||||
iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
|
||||
ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
|
||||
ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
|
||||
ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
|
||||
ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
|
||||
ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
|
||||
iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
|
||||
FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
|
||||
FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
|
||||
FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
|
||||
FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
|
||||
FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
|
||||
iwl3945_release_nic_access(priv);
|
||||
|
||||
/* fake read to flush all prev. writes */
|
||||
iwl3945_read32(priv, FH_TSSR_CBB_BASE);
|
||||
iwl3945_read32(priv, FH39_TSSR_CBB_BASE);
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -691,7 +691,6 @@ static inline void iwl3945_rfkill_unregister(struct iwl3945_priv *priv) {}
|
||||
static inline int iwl3945_rfkill_init(struct iwl3945_priv *priv) { return 0; }
|
||||
#endif
|
||||
|
||||
#define IWL_MAX_NUM_QUEUES IWL39_MAX_NUM_QUEUES
|
||||
|
||||
struct iwl3945_priv {
|
||||
|
||||
@ -815,7 +814,7 @@ struct iwl3945_priv {
|
||||
|
||||
/* Rx and Tx DMA processing queues */
|
||||
struct iwl3945_rx_queue rxq;
|
||||
struct iwl3945_tx_queue txq[IWL_MAX_NUM_QUEUES];
|
||||
struct iwl3945_tx_queue txq[IWL39_MAX_NUM_QUEUES];
|
||||
|
||||
unsigned long status;
|
||||
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
|
||||
#include "iwl-3945-core.h"
|
||||
#include "iwl-3945.h"
|
||||
#include "iwl-3945-fh.h"
|
||||
#include "iwl-helpers.h"
|
||||
|
||||
#ifdef CONFIG_IWL3945_DEBUG
|
||||
@ -3479,14 +3480,14 @@ int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_
|
||||
goto exit_unlock;
|
||||
|
||||
/* Device expects a multiple of 8 */
|
||||
iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
|
||||
iwl3945_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
|
||||
q->write & ~0x7);
|
||||
iwl3945_release_nic_access(priv);
|
||||
|
||||
/* Else device is assumed to be awake */
|
||||
} else
|
||||
/* Device expects a multiple of 8 */
|
||||
iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
|
||||
iwl3945_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
|
||||
|
||||
|
||||
q->need_update = 0;
|
||||
@ -4339,9 +4340,8 @@ static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
|
||||
|
||||
iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
|
||||
if (!iwl3945_grab_nic_access(priv)) {
|
||||
iwl3945_write_direct32(priv,
|
||||
FH_TCSR_CREDIT
|
||||
(ALM_FH_SRVC_CHNL), 0x0);
|
||||
iwl3945_write_direct32(priv, FH39_TCSR_CREDIT
|
||||
(FH39_SRVC_CHNL), 0x0);
|
||||
iwl3945_release_nic_access(priv);
|
||||
}
|
||||
handled |= CSR_INT_BIT_FH_TX;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user