mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 11:36:41 +07:00
rt2x00: Convert rt2400pci interrupt handling to use tasklets
Fix interrupt processing on slow machines by using individual tasklets for each different device interrupt. This ensures that while a RX or TX status tasklet is scheduled only the according device interrupt is masked and other interrupts such as TBTT can still be processed. Also, this allows us to use tasklet_hi_schedule for TBTT processing which is required to not send out beacons with a wrong DTIM count (due to delayed periodic beacon updates). Furthermore, this improves the latency between the TBTT and sending out buffered multi- and broadcast traffic. As a nice bonus, the interrupt handling overhead should be much lower. Compile-tested only. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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16222a0d06
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@ -645,6 +645,11 @@ static void rt2400pci_start_queue(struct data_queue *queue)
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rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
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break;
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case QID_BEACON:
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/*
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* Allow the tbtt tasklet to be scheduled.
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*/
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tasklet_enable(&rt2x00dev->tbtt_tasklet);
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rt2x00pci_register_read(rt2x00dev, CSR14, ®);
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rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
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rt2x00_set_field32(®, CSR14_TBCN, 1);
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@ -706,6 +711,11 @@ static void rt2400pci_stop_queue(struct data_queue *queue)
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rt2x00_set_field32(®, CSR14_TBCN, 0);
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rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
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rt2x00pci_register_write(rt2x00dev, CSR14, reg);
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/*
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* Wait for possibly running tbtt tasklets.
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*/
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tasklet_disable(&rt2x00dev->tbtt_tasklet);
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break;
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default:
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break;
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@ -964,6 +974,7 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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int mask = (state == STATE_RADIO_IRQ_OFF) ||
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(state == STATE_RADIO_IRQ_OFF_ISR);
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u32 reg;
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unsigned long flags;
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/*
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* When interrupts are being enabled, the interrupt registers
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@ -972,12 +983,20 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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if (state == STATE_RADIO_IRQ_ON) {
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rt2x00pci_register_read(rt2x00dev, CSR7, ®);
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rt2x00pci_register_write(rt2x00dev, CSR7, reg);
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/*
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* Enable tasklets.
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*/
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tasklet_enable(&rt2x00dev->txstatus_tasklet);
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tasklet_enable(&rt2x00dev->rxdone_tasklet);
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}
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/*
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* Only toggle the interrupts bits we are going to use.
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* Non-checked interrupt bits are disabled by default.
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*/
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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rt2x00pci_register_read(rt2x00dev, CSR8, ®);
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rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
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rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
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@ -985,6 +1004,17 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
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rt2x00_set_field32(®, CSR8_RXDONE, mask);
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rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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if (state == STATE_RADIO_IRQ_OFF) {
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/*
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* Ensure that all tasklets are finished before
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* disabling the interrupts.
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*/
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tasklet_disable(&rt2x00dev->txstatus_tasklet);
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tasklet_disable(&rt2x00dev->rxdone_tasklet);
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}
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}
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static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
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@ -1285,57 +1315,71 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
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}
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}
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static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
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static void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
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struct rt2x00_field32 irq_field)
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{
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struct rt2x00_dev *rt2x00dev = dev_instance;
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u32 reg = rt2x00dev->irqvalue[0];
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unsigned long flags;
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u32 reg;
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/*
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* Handle interrupts, walk through all bits
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* and run the tasks, the bits are checked in order of
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* priority.
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* Enable a single interrupt. The interrupt mask register
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* access needs locking.
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*/
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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rt2x00pci_register_read(rt2x00dev, CSR8, ®);
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rt2x00_set_field32(®, irq_field, 0);
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rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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}
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static void rt2400pci_txstatus_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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u32 reg;
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unsigned long flags;
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/*
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* 1 - Beacon timer expired interrupt.
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* Handle all tx queues.
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*/
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if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
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rt2x00lib_beacondone(rt2x00dev);
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rt2400pci_txdone(rt2x00dev, QID_ATIM);
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rt2400pci_txdone(rt2x00dev, QID_AC_VO);
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rt2400pci_txdone(rt2x00dev, QID_AC_VI);
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/*
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* 2 - Rx ring done interrupt.
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* Enable all TXDONE interrupts again.
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*/
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if (rt2x00_get_field32(reg, CSR7_RXDONE))
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rt2x00pci_rxdone(rt2x00dev);
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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/*
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* 3 - Atim ring transmit done interrupt.
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*/
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if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
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rt2400pci_txdone(rt2x00dev, QID_ATIM);
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rt2x00pci_register_read(rt2x00dev, CSR8, ®);
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rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
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rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
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rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
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rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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/*
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* 4 - Priority ring transmit done interrupt.
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*/
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if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
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rt2400pci_txdone(rt2x00dev, QID_AC_VO);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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}
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/*
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* 5 - Tx ring transmit done interrupt.
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*/
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if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
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rt2400pci_txdone(rt2x00dev, QID_AC_VI);
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static void rt2400pci_tbtt_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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rt2x00lib_beacondone(rt2x00dev);
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rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
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}
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/* Enable interrupts again. */
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rt2x00dev->ops->lib->set_device_state(rt2x00dev,
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STATE_RADIO_IRQ_ON_ISR);
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return IRQ_HANDLED;
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static void rt2400pci_rxdone_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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rt2x00pci_rxdone(rt2x00dev);
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rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
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}
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static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
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{
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struct rt2x00_dev *rt2x00dev = dev_instance;
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u32 reg;
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u32 reg, mask;
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unsigned long flags;
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/*
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* Get the interrupt sources & saved to local variable.
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@ -1350,14 +1394,44 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
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if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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return IRQ_HANDLED;
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/* Store irqvalues for use in the interrupt thread. */
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rt2x00dev->irqvalue[0] = reg;
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mask = reg;
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/* Disable interrupts, will be enabled again in the interrupt thread. */
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rt2x00dev->ops->lib->set_device_state(rt2x00dev,
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STATE_RADIO_IRQ_OFF_ISR);
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/*
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* Schedule tasklets for interrupt handling.
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*/
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if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
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tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
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return IRQ_WAKE_THREAD;
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if (rt2x00_get_field32(reg, CSR7_RXDONE))
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tasklet_schedule(&rt2x00dev->rxdone_tasklet);
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if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
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rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
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rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
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tasklet_schedule(&rt2x00dev->txstatus_tasklet);
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/*
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* Mask out all txdone interrupts.
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*/
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rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
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rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
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rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
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}
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/*
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* Disable all interrupts for which a tasklet was scheduled right now,
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* the tasklet will reenable the appropriate interrupts.
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*/
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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rt2x00pci_register_read(rt2x00dev, CSR8, ®);
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reg |= mask;
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rt2x00pci_register_write(rt2x00dev, CSR8, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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return IRQ_HANDLED;
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}
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/*
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@ -1651,7 +1725,9 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
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static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
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.irq_handler = rt2400pci_interrupt,
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.irq_handler_thread = rt2400pci_interrupt_thread,
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.txstatus_tasklet = rt2400pci_txstatus_tasklet,
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.tbtt_tasklet = rt2400pci_tbtt_tasklet,
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.rxdone_tasklet = rt2400pci_rxdone_tasklet,
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.probe_hw = rt2400pci_probe_hw,
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.initialize = rt2x00pci_initialize,
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.uninitialize = rt2x00pci_uninitialize,
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