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firmware: xilinx: Remove eemi ops for aes engine

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Use direct function call for aes engine instead of using eemi ops.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Link: https://lore.kernel.org/r/1587761887-4279-20-git-send-email-jolly.shah@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Rajan Vaja 2020-04-24 13:58:01 -07:00 committed by Greg Kroah-Hartman
parent cbbbda71fe
commit bc86f9c546
3 changed files with 8 additions and 14 deletions
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12
drivers/crypto/xilinx/zynqmp-aes-gcm.c
View File

@ -46,7 +46,6 @@ struct zynqmp_aead_drv_ctx {
} alg;
struct device *dev;
struct crypto_engine *engine;
const struct zynqmp_eemi_ops *eemi_ops;
};
struct zynqmp_aead_hw_req {
@ -92,9 +91,6 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req)
drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead);
if (!drv_ctx->eemi_ops->aes)
return -ENOTSUPP;
if (tfm_ctx->keysrc == ZYNQMP_AES_KUP_KEY)
dma_size = req->cryptlen + ZYNQMP_AES_KEY_SIZE
+ GCM_AES_IV_SIZE;
@ -136,7 +132,7 @@ static int zynqmp_aes_aead_cipher(struct aead_request *req)
hwreq->key = 0;
}
drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status);
zynqmp_pm_aes_engine(dma_addr_hw_req, &status);
if (status) {
switch (status) {
@ -388,12 +384,6 @@ static int zynqmp_aes_aead_probe(struct platform_device *pdev)
else
return -ENODEV;
aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops();
if (IS_ERR(aes_drv_ctx.eemi_ops)) {
dev_err(dev, "Failed to get ZynqMP EEMI interface\n");
return PTR_ERR(aes_drv_ctx.eemi_ops);
}
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
if (err < 0) {
dev_err(dev, "No usable DMA configuration\n");

4
drivers/firmware/xilinx/zynqmp.c
View File

@ -795,7 +795,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
*
* Return: Returns status, either success or error code.
*/
static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
int zynqmp_pm_aes_engine(const u64 address, u32 *out)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
@ -810,11 +810,11 @@ static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
static const struct zynqmp_eemi_ops eemi_ops = {
.fpga_load = zynqmp_pm_fpga_load,
.fpga_get_status = zynqmp_pm_fpga_get_status,
.aes = zynqmp_pm_aes_engine,
};
/**

6
include/linux/firmware/xlnx-zynqmp.h
View File

@ -296,7 +296,6 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
int (*fpga_get_status)(u32 *value);
int (*aes)(const u64 address, u32 *out);
};
int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
@ -333,6 +332,7 @@ int zynqmp_pm_release_node(const u32 node);
int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@ -446,6 +446,10 @@ static inline int zynqmp_pm_set_requirement(const u32 node,
{
return -ENODEV;
}
static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
{
return -ENODEV;
}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */