mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 00:00:52 +07:00
ioat: cleanup some long deref chains and 80 column collisions
* reduce device->common. to dma-> in ioat_dma_{probe,remove,selftest}
* ioat_lookup_chan_by_index to ioat_chan_by_index
* multi-line function definitions
* ioat_desc_sw.async_tx to ioat_desc_sw.txd
* desc->txd. to tx-> in cleanup routine
Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
e6c0b69a43
commit
bc3c702585
@ -55,9 +55,8 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
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static struct ioat_desc_sw *
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ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
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static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
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struct ioatdma_device *device,
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int index)
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static inline struct ioat_dma_chan *
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ioat_chan_by_index(struct ioatdma_device *device, int index)
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{
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return device->idx[index];
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}
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@ -87,7 +86,7 @@ static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
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attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
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for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
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ioat_chan = ioat_lookup_chan_by_index(instance, bit);
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ioat_chan = ioat_chan_by_index(instance, bit);
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tasklet_schedule(&ioat_chan->cleanup_task);
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}
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@ -205,8 +204,8 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
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* descriptors to hw
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* @chan: DMA channel handle
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*/
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static inline void __ioat1_dma_memcpy_issue_pending(
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struct ioat_dma_chan *ioat_chan)
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static inline void
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__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan)
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{
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ioat_chan->pending = 0;
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writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
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@ -223,8 +222,8 @@ static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
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}
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}
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static inline void __ioat2_dma_memcpy_issue_pending(
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struct ioat_dma_chan *ioat_chan)
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static inline void
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__ioat2_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat_chan)
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{
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ioat_chan->pending = 0;
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writew(ioat_chan->dmacount,
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@ -279,18 +278,18 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work)
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desc = to_ioat_desc(ioat_chan->used_desc.prev);
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switch (ioat_chan->device->version) {
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case IOAT_VER_1_2:
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writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
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writel(((u64) desc->async_tx.phys) >> 32,
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writel(((u64) desc->txd.phys) >> 32,
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ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
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writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
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+ IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
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break;
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case IOAT_VER_2_0:
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writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(((u64) desc->async_tx.phys) >> 32,
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writel(((u64) desc->txd.phys) >> 32,
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ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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/* tell the engine to go with what's left to be done */
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@ -299,7 +298,7 @@ static void ioat_dma_chan_reset_part2(struct work_struct *work)
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break;
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}
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dev_err(&ioat_chan->device->pdev->dev,
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dev_err(to_dev(ioat_chan),
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"chan%d reset - %d descs waiting, %d total desc\n",
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chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
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@ -322,7 +321,7 @@ static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
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chansts = (ioat_chan->completion_virt->low
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& IOAT_CHANSTS_DMA_TRANSFER_STATUS);
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if (chanerr) {
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dev_err(&ioat_chan->device->pdev->dev,
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dev_err(to_dev(ioat_chan),
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"chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
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chan_num(ioat_chan), chansts, chanerr);
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writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
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@ -367,7 +366,7 @@ static void ioat_dma_chan_watchdog(struct work_struct *work)
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unsigned long compl_desc_addr_hw;
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for (i = 0; i < device->common.chancnt; i++) {
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ioat_chan = ioat_lookup_chan_by_index(device, i);
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ioat_chan = ioat_chan_by_index(device, i);
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if (ioat_chan->device->version == IOAT_VER_1_2
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/* have we started processing anything yet */
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@ -475,7 +474,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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len = first->len;
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src = first->src;
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dst = first->dst;
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orig_flags = first->async_tx.flags;
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orig_flags = first->txd.flags;
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new = first;
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spin_lock_bh(&ioat_chan->desc_lock);
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@ -484,7 +483,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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do {
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copy = min_t(size_t, len, ioat_chan->xfercap);
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async_tx_ack(&new->async_tx);
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async_tx_ack(&new->txd);
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hw = new->hw;
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hw->size = copy;
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@ -495,7 +494,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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/* chain together the physical address list for the HW */
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wmb();
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prev->hw->next = (u64) new->async_tx.phys;
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prev->hw->next = (u64) new->txd.phys;
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len -= copy;
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dst += copy;
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@ -507,27 +506,26 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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} while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
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if (!new) {
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dev_err(&ioat_chan->device->pdev->dev,
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"tx submit failed\n");
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dev_err(to_dev(ioat_chan), "tx submit failed\n");
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spin_unlock_bh(&ioat_chan->desc_lock);
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return -ENOMEM;
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}
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hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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if (first->async_tx.callback) {
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if (first->txd.callback) {
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
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if (first != new) {
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/* move callback into to last desc */
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new->async_tx.callback = first->async_tx.callback;
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new->async_tx.callback_param
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= first->async_tx.callback_param;
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first->async_tx.callback = NULL;
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first->async_tx.callback_param = NULL;
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new->txd.callback = first->txd.callback;
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new->txd.callback_param
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= first->txd.callback_param;
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first->txd.callback = NULL;
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first->txd.callback_param = NULL;
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}
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}
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new->tx_cnt = desc_count;
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new->async_tx.flags = orig_flags; /* client is in control of this ack */
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new->txd.flags = orig_flags; /* client is in control of this ack */
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/* store the original values for use in later cleanup */
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if (new != first) {
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@ -541,11 +539,11 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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cookie++;
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if (cookie < 0)
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cookie = 1;
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ioat_chan->common.cookie = new->async_tx.cookie = cookie;
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ioat_chan->common.cookie = new->txd.cookie = cookie;
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/* write address into NextDescriptor field of last desc in chain */
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to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
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first->async_tx.phys;
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first->txd.phys;
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list_splice_tail(&new_chain, &ioat_chan->used_desc);
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ioat_chan->dmacount += desc_count;
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@ -574,7 +572,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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len = first->len;
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src = first->src;
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dst = first->dst;
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orig_flags = first->async_tx.flags;
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orig_flags = first->txd.flags;
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new = first;
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/*
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@ -584,7 +582,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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do {
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copy = min_t(size_t, len, ioat_chan->xfercap);
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async_tx_ack(&new->async_tx);
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async_tx_ack(&new->txd);
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hw = new->hw;
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hw->size = copy;
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@ -599,27 +597,26 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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} while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
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if (!new) {
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dev_err(&ioat_chan->device->pdev->dev,
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"tx submit failed\n");
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dev_err(to_dev(ioat_chan), "tx submit failed\n");
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spin_unlock_bh(&ioat_chan->desc_lock);
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return -ENOMEM;
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}
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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if (first->async_tx.callback) {
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if (first->txd.callback) {
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
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if (first != new) {
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/* move callback into to last desc */
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new->async_tx.callback = first->async_tx.callback;
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new->async_tx.callback_param
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= first->async_tx.callback_param;
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first->async_tx.callback = NULL;
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first->async_tx.callback_param = NULL;
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new->txd.callback = first->txd.callback;
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new->txd.callback_param
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= first->txd.callback_param;
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first->txd.callback = NULL;
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first->txd.callback_param = NULL;
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}
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}
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new->tx_cnt = desc_count;
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new->async_tx.flags = orig_flags; /* client is in control of this ack */
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new->txd.flags = orig_flags; /* client is in control of this ack */
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/* store the original values for use in later cleanup */
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if (new != first) {
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@ -633,7 +630,7 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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cookie++;
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if (cookie < 0)
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cookie = 1;
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ioat_chan->common.cookie = new->async_tx.cookie = cookie;
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ioat_chan->common.cookie = new->txd.cookie = cookie;
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ioat_chan->dmacount += desc_count;
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ioat_chan->pending += desc_count;
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@ -649,9 +646,8 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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* @ioat_chan: the channel supplying the memory pool for the descriptors
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* @flags: allocation flags
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*/
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static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
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struct ioat_dma_chan *ioat_chan,
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gfp_t flags)
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static struct ioat_desc_sw *
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ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat_chan, gfp_t flags)
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{
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struct ioat_dma_descriptor *desc;
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struct ioat_desc_sw *desc_sw;
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@ -670,19 +666,19 @@ static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
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}
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memset(desc, 0, sizeof(*desc));
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dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
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dma_async_tx_descriptor_init(&desc_sw->txd, &ioat_chan->common);
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switch (ioat_chan->device->version) {
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case IOAT_VER_1_2:
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desc_sw->async_tx.tx_submit = ioat1_tx_submit;
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desc_sw->txd.tx_submit = ioat1_tx_submit;
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break;
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case IOAT_VER_2_0:
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case IOAT_VER_3_0:
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desc_sw->async_tx.tx_submit = ioat2_tx_submit;
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desc_sw->txd.tx_submit = ioat2_tx_submit;
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break;
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}
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desc_sw->hw = desc;
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desc_sw->async_tx.phys = phys;
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desc_sw->txd.phys = phys;
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return desc_sw;
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}
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@ -712,9 +708,9 @@ static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
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/* circle link the hw descriptors */
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desc = to_ioat_desc(ioat_chan->free_desc.next);
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desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
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desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys;
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list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
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desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
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desc->hw->next = to_ioat_desc(desc->node.next)->txd.phys;
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}
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}
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@ -743,8 +739,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
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chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
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if (chanerr) {
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dev_err(&ioat_chan->device->pdev->dev,
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"CHANERR = %x, clearing\n", chanerr);
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dev_err(to_dev(ioat_chan), "CHANERR = %x, clearing\n", chanerr);
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writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
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}
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@ -752,7 +747,7 @@ static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
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for (i = 0; i < ioat_initial_desc_count; i++) {
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desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
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if (!desc) {
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dev_err(&ioat_chan->device->pdev->dev,
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dev_err(to_dev(ioat_chan),
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"Only %d initial descriptors\n", i);
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break;
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}
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@ -819,14 +814,14 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
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in_use_descs++;
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list_del(&desc->node);
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pci_pool_free(ioatdma_device->dma_pool, desc->hw,
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desc->async_tx.phys);
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desc->txd.phys);
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kfree(desc);
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}
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list_for_each_entry_safe(desc, _desc,
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&ioat_chan->free_desc, node) {
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list_del(&desc->node);
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pci_pool_free(ioatdma_device->dma_pool, desc->hw,
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desc->async_tx.phys);
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desc->txd.phys);
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kfree(desc);
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}
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break;
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@ -836,12 +831,12 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
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ioat_chan->free_desc.next, node) {
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list_del(&desc->node);
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pci_pool_free(ioatdma_device->dma_pool, desc->hw,
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desc->async_tx.phys);
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desc->txd.phys);
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kfree(desc);
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}
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desc = to_ioat_desc(ioat_chan->free_desc.next);
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pci_pool_free(ioatdma_device->dma_pool, desc->hw,
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desc->async_tx.phys);
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desc->txd.phys);
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kfree(desc);
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INIT_LIST_HEAD(&ioat_chan->free_desc);
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INIT_LIST_HEAD(&ioat_chan->used_desc);
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@ -855,8 +850,7 @@ static void ioat_dma_free_chan_resources(struct dma_chan *chan)
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/* one is ok since we left it on there on purpose */
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if (in_use_descs > 1)
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dev_err(&ioat_chan->device->pdev->dev,
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"Freeing %d in use descriptors!\n",
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dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
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in_use_descs - 1);
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ioat_chan->last_completion = ioat_chan->completion_addr = 0;
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@ -889,8 +883,7 @@ ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
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/* try to get another desc */
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new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
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if (!new) {
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dev_err(&ioat_chan->device->pdev->dev,
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"alloc failed\n");
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dev_err(to_dev(ioat_chan), "alloc failed\n");
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return NULL;
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}
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}
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@ -936,16 +929,15 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
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for (i = 16; i; i--) {
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desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
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if (!desc) {
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dev_err(&ioat_chan->device->pdev->dev,
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"alloc failed\n");
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dev_err(to_dev(ioat_chan), "alloc failed\n");
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break;
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}
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list_add_tail(&desc->node, ioat_chan->used_desc.next);
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desc->hw->next
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= to_ioat_desc(desc->node.next)->async_tx.phys;
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= to_ioat_desc(desc->node.next)->txd.phys;
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to_ioat_desc(desc->node.prev)->hw->next
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= desc->async_tx.phys;
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= desc->txd.phys;
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ioat_chan->desccount++;
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}
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@ -962,8 +954,8 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
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return new;
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}
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static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
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struct ioat_dma_chan *ioat_chan)
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static struct ioat_desc_sw *
|
||||
ioat_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
|
||||
{
|
||||
if (!ioat_chan)
|
||||
return NULL;
|
||||
@ -978,12 +970,9 @@ static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
|
||||
struct dma_chan *chan,
|
||||
dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src,
|
||||
size_t len,
|
||||
unsigned long flags)
|
||||
static struct dma_async_tx_descriptor *
|
||||
ioat1_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src, size_t len, unsigned long flags)
|
||||
{
|
||||
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
||||
struct ioat_desc_sw *new;
|
||||
@ -996,22 +985,19 @@ static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
|
||||
new->len = len;
|
||||
new->dst = dma_dest;
|
||||
new->src = dma_src;
|
||||
new->async_tx.flags = flags;
|
||||
return &new->async_tx;
|
||||
new->txd.flags = flags;
|
||||
return &new->txd;
|
||||
} else {
|
||||
dev_err(&ioat_chan->device->pdev->dev,
|
||||
dev_err(to_dev(ioat_chan),
|
||||
"chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
|
||||
chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
|
||||
struct dma_chan *chan,
|
||||
dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src,
|
||||
size_t len,
|
||||
unsigned long flags)
|
||||
static struct dma_async_tx_descriptor *
|
||||
ioat2_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
|
||||
dma_addr_t dma_src, size_t len, unsigned long flags)
|
||||
{
|
||||
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
||||
struct ioat_desc_sw *new;
|
||||
@ -1028,11 +1014,11 @@ static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
|
||||
new->len = len;
|
||||
new->dst = dma_dest;
|
||||
new->src = dma_src;
|
||||
new->async_tx.flags = flags;
|
||||
return &new->async_tx;
|
||||
new->txd.flags = flags;
|
||||
return &new->txd;
|
||||
} else {
|
||||
spin_unlock_bh(&ioat_chan->desc_lock);
|
||||
dev_err(&ioat_chan->device->pdev->dev,
|
||||
dev_err(to_dev(ioat_chan),
|
||||
"chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
|
||||
chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
|
||||
return NULL;
|
||||
@ -1050,8 +1036,8 @@ static void ioat_dma_cleanup_tasklet(unsigned long data)
|
||||
static void
|
||||
ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
|
||||
{
|
||||
if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
|
||||
if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
|
||||
if (!(desc->txd.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
|
||||
if (desc->txd.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
|
||||
pci_unmap_single(ioat_chan->device->pdev,
|
||||
pci_unmap_addr(desc, dst),
|
||||
pci_unmap_len(desc, len),
|
||||
@ -1063,8 +1049,8 @@ ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
|
||||
PCI_DMA_FROMDEVICE);
|
||||
}
|
||||
|
||||
if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
|
||||
if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
|
||||
if (!(desc->txd.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
|
||||
if (desc->txd.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
|
||||
pci_unmap_single(ioat_chan->device->pdev,
|
||||
pci_unmap_addr(desc, src),
|
||||
pci_unmap_len(desc, len),
|
||||
@ -1088,6 +1074,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
dma_cookie_t cookie = 0;
|
||||
unsigned long desc_phys;
|
||||
struct ioat_desc_sw *latest_desc;
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
|
||||
prefetch(ioat_chan->completion_virt);
|
||||
|
||||
@ -1111,8 +1098,7 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
if ((ioat_chan->completion_virt->full
|
||||
& IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
|
||||
IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
|
||||
dev_err(&ioat_chan->device->pdev->dev,
|
||||
"Channel halted, chanerr = %x\n",
|
||||
dev_err(to_dev(ioat_chan), "Channel halted, chanerr = %x\n",
|
||||
readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
|
||||
|
||||
/* TODO do something to salvage the situation */
|
||||
@ -1145,38 +1131,38 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
case IOAT_VER_1_2:
|
||||
list_for_each_entry_safe(desc, _desc,
|
||||
&ioat_chan->used_desc, node) {
|
||||
|
||||
tx = &desc->txd;
|
||||
/*
|
||||
* Incoming DMA requests may use multiple descriptors,
|
||||
* due to exceeding xfercap, perhaps. If so, only the
|
||||
* last one will have a cookie, and require unmapping.
|
||||
*/
|
||||
if (desc->async_tx.cookie) {
|
||||
cookie = desc->async_tx.cookie;
|
||||
if (tx->cookie) {
|
||||
cookie = tx->cookie;
|
||||
ioat_dma_unmap(ioat_chan, desc);
|
||||
if (desc->async_tx.callback) {
|
||||
desc->async_tx.callback(desc->async_tx.callback_param);
|
||||
desc->async_tx.callback = NULL;
|
||||
if (tx->callback) {
|
||||
tx->callback(tx->callback_param);
|
||||
tx->callback = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
if (desc->async_tx.phys != phys_complete) {
|
||||
if (tx->phys != phys_complete) {
|
||||
/*
|
||||
* a completed entry, but not the last, so clean
|
||||
* up if the client is done with the descriptor
|
||||
*/
|
||||
if (async_tx_test_ack(&desc->async_tx)) {
|
||||
if (async_tx_test_ack(tx)) {
|
||||
list_move_tail(&desc->node,
|
||||
&ioat_chan->free_desc);
|
||||
} else
|
||||
desc->async_tx.cookie = 0;
|
||||
tx->cookie = 0;
|
||||
} else {
|
||||
/*
|
||||
* last used desc. Do not remove, so we can
|
||||
* append from it, but don't look at it next
|
||||
* time, either
|
||||
*/
|
||||
desc->async_tx.cookie = 0;
|
||||
tx->cookie = 0;
|
||||
|
||||
/* TODO check status bits? */
|
||||
break;
|
||||
@ -1191,10 +1177,11 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
|
||||
/* work backwards to find latest finished desc */
|
||||
desc = to_ioat_desc(ioat_chan->used_desc.next);
|
||||
tx = &desc->txd;
|
||||
latest_desc = NULL;
|
||||
do {
|
||||
desc = to_ioat_desc(desc->node.prev);
|
||||
desc_phys = (unsigned long)desc->async_tx.phys
|
||||
desc_phys = (unsigned long)tx->phys
|
||||
& IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
|
||||
if (desc_phys == phys_complete) {
|
||||
latest_desc = desc;
|
||||
@ -1203,19 +1190,18 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
} while (&desc->node != ioat_chan->used_desc.prev);
|
||||
|
||||
if (latest_desc != NULL) {
|
||||
|
||||
/* work forwards to clear finished descriptors */
|
||||
for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
|
||||
&desc->node != latest_desc->node.next &&
|
||||
&desc->node != ioat_chan->used_desc.next;
|
||||
desc = to_ioat_desc(desc->node.next)) {
|
||||
if (desc->async_tx.cookie) {
|
||||
cookie = desc->async_tx.cookie;
|
||||
desc->async_tx.cookie = 0;
|
||||
if (tx->cookie) {
|
||||
cookie = tx->cookie;
|
||||
tx->cookie = 0;
|
||||
ioat_dma_unmap(ioat_chan, desc);
|
||||
if (desc->async_tx.callback) {
|
||||
desc->async_tx.callback(desc->async_tx.callback_param);
|
||||
desc->async_tx.callback = NULL;
|
||||
if (tx->callback) {
|
||||
tx->callback(tx->callback_param);
|
||||
tx->callback = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1245,10 +1231,9 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
|
||||
* @done: if not %NULL, updated with last completed transaction
|
||||
* @used: if not %NULL, updated with last used transaction
|
||||
*/
|
||||
static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
|
||||
dma_cookie_t cookie,
|
||||
dma_cookie_t *done,
|
||||
dma_cookie_t *used)
|
||||
static enum dma_status
|
||||
ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie,
|
||||
dma_cookie_t *done, dma_cookie_t *used)
|
||||
{
|
||||
struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
|
||||
dma_cookie_t last_used;
|
||||
@ -1290,7 +1275,7 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
|
||||
desc = ioat_dma_get_next_descriptor(ioat_chan);
|
||||
|
||||
if (!desc) {
|
||||
dev_err(&ioat_chan->device->pdev->dev,
|
||||
dev_err(to_dev(ioat_chan),
|
||||
"Unable to start null desc - get next desc failed\n");
|
||||
spin_unlock_bh(&ioat_chan->desc_lock);
|
||||
return;
|
||||
@ -1303,15 +1288,15 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
|
||||
desc->hw->size = NULL_DESC_BUFFER_SIZE;
|
||||
desc->hw->src_addr = 0;
|
||||
desc->hw->dst_addr = 0;
|
||||
async_tx_ack(&desc->async_tx);
|
||||
async_tx_ack(&desc->txd);
|
||||
switch (ioat_chan->device->version) {
|
||||
case IOAT_VER_1_2:
|
||||
desc->hw->next = 0;
|
||||
list_add_tail(&desc->node, &ioat_chan->used_desc);
|
||||
|
||||
writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
|
||||
writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
|
||||
ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
|
||||
writel(((u64) desc->async_tx.phys) >> 32,
|
||||
writel(((u64) desc->txd.phys) >> 32,
|
||||
ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
|
||||
|
||||
writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
|
||||
@ -1319,9 +1304,9 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
|
||||
break;
|
||||
case IOAT_VER_2_0:
|
||||
case IOAT_VER_3_0:
|
||||
writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
|
||||
writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
|
||||
ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
|
||||
writel(((u64) desc->async_tx.phys) >> 32,
|
||||
writel(((u64) desc->txd.phys) >> 32,
|
||||
ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
|
||||
|
||||
ioat_chan->dmacount++;
|
||||
@ -1352,6 +1337,8 @@ static int ioat_dma_self_test(struct ioatdma_device *device)
|
||||
int i;
|
||||
u8 *src;
|
||||
u8 *dest;
|
||||
struct dma_device *dma = &device->common;
|
||||
struct device *dev = &device->pdev->dev;
|
||||
struct dma_chan *dma_chan;
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
dma_addr_t dma_dest, dma_src;
|
||||
@ -1375,26 +1362,21 @@ static int ioat_dma_self_test(struct ioatdma_device *device)
|
||||
src[i] = (u8)i;
|
||||
|
||||
/* Start copy, using first DMA channel */
|
||||
dma_chan = container_of(device->common.channels.next,
|
||||
struct dma_chan,
|
||||
dma_chan = container_of(dma->channels.next, struct dma_chan,
|
||||
device_node);
|
||||
if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
|
||||
dev_err(&device->pdev->dev,
|
||||
"selftest cannot allocate chan resource\n");
|
||||
if (dma->device_alloc_chan_resources(dma_chan) < 1) {
|
||||
dev_err(dev, "selftest cannot allocate chan resource\n");
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
|
||||
DMA_TO_DEVICE);
|
||||
dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
|
||||
DMA_FROM_DEVICE);
|
||||
dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
|
||||
dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
|
||||
flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE;
|
||||
tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
|
||||
IOAT_TEST_SIZE, flags);
|
||||
if (!tx) {
|
||||
dev_err(&device->pdev->dev,
|
||||
"Self-test prep failed, disabling\n");
|
||||
dev_err(dev, "Self-test prep failed, disabling\n");
|
||||
err = -ENODEV;
|
||||
goto free_resources;
|
||||
}
|
||||
@ -1405,32 +1387,29 @@ static int ioat_dma_self_test(struct ioatdma_device *device)
|
||||
tx->callback_param = &cmp;
|
||||
cookie = tx->tx_submit(tx);
|
||||
if (cookie < 0) {
|
||||
dev_err(&device->pdev->dev,
|
||||
"Self-test setup failed, disabling\n");
|
||||
dev_err(dev, "Self-test setup failed, disabling\n");
|
||||
err = -ENODEV;
|
||||
goto free_resources;
|
||||
}
|
||||
device->common.device_issue_pending(dma_chan);
|
||||
dma->device_issue_pending(dma_chan);
|
||||
|
||||
tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
|
||||
|
||||
if (tmo == 0 ||
|
||||
device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
|
||||
dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
|
||||
!= DMA_SUCCESS) {
|
||||
dev_err(&device->pdev->dev,
|
||||
"Self-test copy timed out, disabling\n");
|
||||
dev_err(dev, "Self-test copy timed out, disabling\n");
|
||||
err = -ENODEV;
|
||||
goto free_resources;
|
||||
}
|
||||
if (memcmp(src, dest, IOAT_TEST_SIZE)) {
|
||||
dev_err(&device->pdev->dev,
|
||||
"Self-test copy failed compare, disabling\n");
|
||||
dev_err(dev, "Self-test copy failed compare, disabling\n");
|
||||
err = -ENODEV;
|
||||
goto free_resources;
|
||||
}
|
||||
|
||||
free_resources:
|
||||
device->common.device_free_chan_resources(dma_chan);
|
||||
dma->device_free_chan_resources(dma_chan);
|
||||
out:
|
||||
kfree(src);
|
||||
kfree(dest);
|
||||
@ -1483,15 +1462,14 @@ static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
|
||||
|
||||
for (i = 0; i < msixcnt; i++) {
|
||||
msix = &device->msix_entries[i];
|
||||
ioat_chan = ioat_lookup_chan_by_index(device, i);
|
||||
ioat_chan = ioat_chan_by_index(device, i);
|
||||
err = devm_request_irq(dev, msix->vector,
|
||||
ioat_dma_do_interrupt_msix, 0,
|
||||
"ioat-msix", ioat_chan);
|
||||
if (err) {
|
||||
for (j = 0; j < i; j++) {
|
||||
msix = &device->msix_entries[j];
|
||||
ioat_chan =
|
||||
ioat_lookup_chan_by_index(device, j);
|
||||
ioat_chan = ioat_chan_by_index(device, j);
|
||||
devm_free_irq(dev, msix->vector, ioat_chan);
|
||||
}
|
||||
goto msix_single_vector;
|
||||
@ -1561,12 +1539,13 @@ static void ioat_disable_interrupts(struct ioatdma_device *device)
|
||||
writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
|
||||
}
|
||||
|
||||
struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
|
||||
void __iomem *iobase)
|
||||
struct ioatdma_device *
|
||||
ioat_dma_probe(struct pci_dev *pdev, void __iomem *iobase)
|
||||
{
|
||||
int err;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct ioatdma_device *device;
|
||||
struct dma_device *dma;
|
||||
|
||||
device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL);
|
||||
if (!device)
|
||||
@ -1574,6 +1553,7 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
|
||||
device->pdev = pdev;
|
||||
device->reg_base = iobase;
|
||||
device->version = readb(device->reg_base + IOAT_VER_OFFSET);
|
||||
dma = &device->common;
|
||||
|
||||
/* DMA coherent memory pool for DMA descriptor allocations */
|
||||
device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
|
||||
@ -1592,36 +1572,32 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
|
||||
goto err_completion_pool;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&device->common.channels);
|
||||
INIT_LIST_HEAD(&dma->channels);
|
||||
ioat_dma_enumerate_channels(device);
|
||||
|
||||
device->common.device_alloc_chan_resources =
|
||||
ioat_dma_alloc_chan_resources;
|
||||
device->common.device_free_chan_resources =
|
||||
ioat_dma_free_chan_resources;
|
||||
device->common.dev = &pdev->dev;
|
||||
dma->device_alloc_chan_resources = ioat_dma_alloc_chan_resources;
|
||||
dma->device_free_chan_resources = ioat_dma_free_chan_resources;
|
||||
dma->dev = &pdev->dev;
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
|
||||
device->common.device_is_tx_complete = ioat_dma_is_complete;
|
||||
dma_cap_set(DMA_MEMCPY, dma->cap_mask);
|
||||
dma->device_is_tx_complete = ioat_dma_is_complete;
|
||||
switch (device->version) {
|
||||
case IOAT_VER_1_2:
|
||||
device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
|
||||
device->common.device_issue_pending =
|
||||
ioat1_dma_memcpy_issue_pending;
|
||||
dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
|
||||
dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
|
||||
break;
|
||||
case IOAT_VER_2_0:
|
||||
case IOAT_VER_3_0:
|
||||
device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
|
||||
device->common.device_issue_pending =
|
||||
ioat2_dma_memcpy_issue_pending;
|
||||
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
|
||||
dma->device_issue_pending = ioat2_dma_memcpy_issue_pending;
|
||||
break;
|
||||
}
|
||||
|
||||
dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
|
||||
" %d channels, device version 0x%02x, driver version %s\n",
|
||||
device->common.chancnt, device->version, IOAT_DMA_VERSION);
|
||||
dma->chancnt, device->version, IOAT_DMA_VERSION);
|
||||
|
||||
if (!device->common.chancnt) {
|
||||
if (!dma->chancnt) {
|
||||
dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
|
||||
"zero channels detected\n");
|
||||
goto err_setup_interrupts;
|
||||
@ -1635,7 +1611,7 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
|
||||
if (err)
|
||||
goto err_self_test;
|
||||
|
||||
err = dma_async_device_register(&device->common);
|
||||
err = dma_async_device_register(dma);
|
||||
if (err)
|
||||
goto err_self_test;
|
||||
|
||||
@ -1663,19 +1639,19 @@ void ioat_dma_remove(struct ioatdma_device *device)
|
||||
{
|
||||
struct dma_chan *chan, *_chan;
|
||||
struct ioat_dma_chan *ioat_chan;
|
||||
struct dma_device *dma = &device->common;
|
||||
|
||||
if (device->version != IOAT_VER_3_0)
|
||||
cancel_delayed_work(&device->work);
|
||||
|
||||
ioat_disable_interrupts(device);
|
||||
|
||||
dma_async_device_unregister(&device->common);
|
||||
dma_async_device_unregister(dma);
|
||||
|
||||
pci_pool_destroy(device->dma_pool);
|
||||
pci_pool_destroy(device->completion_pool);
|
||||
|
||||
list_for_each_entry_safe(chan, _chan,
|
||||
&device->common.channels, device_node) {
|
||||
list_for_each_entry_safe(chan, _chan, &dma->channels, device_node) {
|
||||
ioat_chan = to_ioat_chan(chan);
|
||||
list_del(&chan->device_node);
|
||||
}
|
||||
|
||||
@ -38,7 +38,8 @@
|
||||
#define to_ioat_chan(chan) container_of(chan, struct ioat_dma_chan, common)
|
||||
#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
|
||||
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
|
||||
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
|
||||
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
|
||||
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
|
||||
|
||||
#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
|
||||
|
||||
@ -123,7 +124,7 @@ struct ioat_dma_chan {
|
||||
* @node: this descriptor will either be on the free list,
|
||||
* or attached to a transaction list (async_tx.tx_list)
|
||||
* @tx_cnt: number of descriptors required to complete the transaction
|
||||
* @async_tx: the generic software descriptor for all engines
|
||||
* @txd: the generic software descriptor for all engines
|
||||
*/
|
||||
struct ioat_desc_sw {
|
||||
struct ioat_dma_descriptor *hw;
|
||||
@ -132,7 +133,7 @@ struct ioat_desc_sw {
|
||||
size_t len;
|
||||
dma_addr_t src;
|
||||
dma_addr_t dst;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
struct dma_async_tx_descriptor txd;
|
||||
};
|
||||
|
||||
static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user