mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 14:15:35 +07:00
drm/msm/mdp5: subclass msm_mdss for mdp5
SoCs having mdp5 or dpu have identical tree like device hierarchy where MDSS top level wrapper manages common power resources for all child devices. Subclass msm_mdss so that msm_mdss includes common defines and mdp5/dpu mdss derivations to include any extensions. Add mdss helper interface (msm_mdss_funcs) to msm_mdss base for mdp5/dpu mdss specific implementation calls. This change subclasses msm_mdss for mdp5, dpu specific changes will be done separately. Changes in v3: - Added Archit's R-b Reviewed-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> [seanpaul rebased on msm-next and resolved conflicts] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rajesh Yadav
Sean Paul
parent
a5c6b59904
commit
bc3220be22
@ -20,12 +20,10 @@
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#include "msm_drv.h"
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#include "mdp5_kms.h"
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/*
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* If needed, this can become more specific: something like struct mdp5_mdss,
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* which contains a 'struct msm_mdss base' member.
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*/
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struct msm_mdss {
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struct drm_device *dev;
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#define to_mdp5_mdss(x) container_of(x, struct mdp5_mdss, base)
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struct mdp5_mdss {
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struct msm_mdss base;
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void __iomem *mmio, *vbif;
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@ -41,22 +39,22 @@ struct msm_mdss {
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} irqcontroller;
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};
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static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data)
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static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data)
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{
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msm_writel(data, mdss->mmio + reg);
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msm_writel(data, mdp5_mdss->mmio + reg);
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}
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static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg)
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static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg)
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{
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return msm_readl(mdss->mmio + reg);
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return msm_readl(mdp5_mdss->mmio + reg);
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}
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static irqreturn_t mdss_irq(int irq, void *arg)
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{
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struct msm_mdss *mdss = arg;
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struct mdp5_mdss *mdp5_mdss = arg;
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u32 intr;
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intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS);
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intr = mdss_read(mdp5_mdss, REG_MDSS_HW_INTR_STATUS);
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VERB("intr=%08x", intr);
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@ -64,7 +62,7 @@ static irqreturn_t mdss_irq(int irq, void *arg)
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irq_hw_number_t hwirq = fls(intr) - 1;
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generic_handle_irq(irq_find_mapping(
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mdss->irqcontroller.domain, hwirq));
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mdp5_mdss->irqcontroller.domain, hwirq));
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intr &= ~(1 << hwirq);
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}
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@ -84,19 +82,19 @@ static irqreturn_t mdss_irq(int irq, void *arg)
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static void mdss_hw_mask_irq(struct irq_data *irqd)
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{
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struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
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struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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clear_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
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clear_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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static void mdss_hw_unmask_irq(struct irq_data *irqd)
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{
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struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd);
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struct mdp5_mdss *mdp5_mdss = irq_data_get_irq_chip_data(irqd);
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smp_mb__before_atomic();
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set_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask);
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set_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
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smp_mb__after_atomic();
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}
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@ -109,13 +107,13 @@ static struct irq_chip mdss_hw_irq_chip = {
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static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct msm_mdss *mdss = d->host_data;
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struct mdp5_mdss *mdp5_mdss = d->host_data;
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if (!(VALID_IRQS & (1 << hwirq)))
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return -EPERM;
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irq_set_chip_and_handler(irq, &mdss_hw_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, mdss);
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irq_set_chip_data(irq, mdp5_mdss);
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return 0;
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}
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@ -126,90 +124,99 @@ static const struct irq_domain_ops mdss_hw_irqdomain_ops = {
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};
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static int mdss_irq_domain_init(struct msm_mdss *mdss)
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static int mdss_irq_domain_init(struct mdp5_mdss *mdp5_mdss)
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{
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struct device *dev = mdss->dev->dev;
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struct device *dev = mdp5_mdss->base.dev->dev;
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struct irq_domain *d;
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d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops,
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mdss);
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mdp5_mdss);
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if (!d) {
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dev_err(dev, "mdss irq domain add failed\n");
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return -ENXIO;
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}
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mdss->irqcontroller.enabled_mask = 0;
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mdss->irqcontroller.domain = d;
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mdp5_mdss->irqcontroller.enabled_mask = 0;
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mdp5_mdss->irqcontroller.domain = d;
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return 0;
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}
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int msm_mdss_enable(struct msm_mdss *mdss)
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static int mdp5_mdss_enable(struct msm_mdss *mdss)
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{
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struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(mdss);
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DBG("");
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clk_prepare_enable(mdss->ahb_clk);
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if (mdss->axi_clk)
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clk_prepare_enable(mdss->axi_clk);
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if (mdss->vsync_clk)
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clk_prepare_enable(mdss->vsync_clk);
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clk_prepare_enable(mdp5_mdss->ahb_clk);
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if (mdp5_mdss->axi_clk)
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clk_prepare_enable(mdp5_mdss->axi_clk);
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if (mdp5_mdss->vsync_clk)
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clk_prepare_enable(mdp5_mdss->vsync_clk);
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return 0;
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}
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int msm_mdss_disable(struct msm_mdss *mdss)
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static int mdp5_mdss_disable(struct msm_mdss *mdss)
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{
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struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(mdss);
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DBG("");
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if (mdss->vsync_clk)
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clk_disable_unprepare(mdss->vsync_clk);
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if (mdss->axi_clk)
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clk_disable_unprepare(mdss->axi_clk);
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clk_disable_unprepare(mdss->ahb_clk);
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if (mdp5_mdss->vsync_clk)
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clk_disable_unprepare(mdp5_mdss->vsync_clk);
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if (mdp5_mdss->axi_clk)
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clk_disable_unprepare(mdp5_mdss->axi_clk);
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clk_disable_unprepare(mdp5_mdss->ahb_clk);
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return 0;
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}
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static int msm_mdss_get_clocks(struct msm_mdss *mdss)
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static int msm_mdss_get_clocks(struct mdp5_mdss *mdp5_mdss)
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{
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struct platform_device *pdev = to_platform_device(mdss->dev->dev);
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struct platform_device *pdev =
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to_platform_device(mdp5_mdss->base.dev->dev);
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mdss->ahb_clk = msm_clk_get(pdev, "iface");
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if (IS_ERR(mdss->ahb_clk))
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mdss->ahb_clk = NULL;
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mdp5_mdss->ahb_clk = msm_clk_get(pdev, "iface");
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if (IS_ERR(mdp5_mdss->ahb_clk))
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mdp5_mdss->ahb_clk = NULL;
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mdss->axi_clk = msm_clk_get(pdev, "bus");
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if (IS_ERR(mdss->axi_clk))
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mdss->axi_clk = NULL;
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mdp5_mdss->axi_clk = msm_clk_get(pdev, "bus");
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if (IS_ERR(mdp5_mdss->axi_clk))
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mdp5_mdss->axi_clk = NULL;
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mdss->vsync_clk = msm_clk_get(pdev, "vsync");
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if (IS_ERR(mdss->vsync_clk))
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mdss->vsync_clk = NULL;
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mdp5_mdss->vsync_clk = msm_clk_get(pdev, "vsync");
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if (IS_ERR(mdp5_mdss->vsync_clk))
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mdp5_mdss->vsync_clk = NULL;
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return 0;
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}
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void msm_mdss_destroy(struct drm_device *dev)
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static void mdp5_mdss_destroy(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_mdss *mdss = priv->mdss;
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struct mdp5_mdss *mdp5_mdss = to_mdp5_mdss(priv->mdss);
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if (!mdss)
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if (!mdp5_mdss)
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return;
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irq_domain_remove(mdss->irqcontroller.domain);
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mdss->irqcontroller.domain = NULL;
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irq_domain_remove(mdp5_mdss->irqcontroller.domain);
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mdp5_mdss->irqcontroller.domain = NULL;
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regulator_disable(mdss->vdd);
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regulator_disable(mdp5_mdss->vdd);
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pm_runtime_disable(dev->dev);
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}
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int msm_mdss_init(struct drm_device *dev)
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static const struct msm_mdss_funcs mdss_funcs = {
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.enable = mdp5_mdss_enable,
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.disable = mdp5_mdss_disable,
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.destroy = mdp5_mdss_destroy,
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};
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int mdp5_mdss_init(struct drm_device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev->dev);
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_mdss *mdss;
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struct mdp5_mdss *mdp5_mdss;
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int ret;
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DBG("");
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@ -217,40 +224,40 @@ int msm_mdss_init(struct drm_device *dev)
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if (!of_device_is_compatible(dev->dev->of_node, "qcom,mdss"))
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return 0;
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mdss = devm_kzalloc(dev->dev, sizeof(*mdss), GFP_KERNEL);
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if (!mdss) {
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mdp5_mdss = devm_kzalloc(dev->dev, sizeof(*mdp5_mdss), GFP_KERNEL);
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if (!mdp5_mdss) {
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ret = -ENOMEM;
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goto fail;
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}
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mdss->dev = dev;
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mdp5_mdss->base.dev = dev;
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mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");
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if (IS_ERR(mdss->mmio)) {
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ret = PTR_ERR(mdss->mmio);
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mdp5_mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS");
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if (IS_ERR(mdp5_mdss->mmio)) {
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ret = PTR_ERR(mdp5_mdss->mmio);
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goto fail;
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}
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mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
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if (IS_ERR(mdss->vbif)) {
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ret = PTR_ERR(mdss->vbif);
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mdp5_mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
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if (IS_ERR(mdp5_mdss->vbif)) {
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ret = PTR_ERR(mdp5_mdss->vbif);
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goto fail;
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}
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ret = msm_mdss_get_clocks(mdss);
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ret = msm_mdss_get_clocks(mdp5_mdss);
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if (ret) {
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dev_err(dev->dev, "failed to get clocks: %d\n", ret);
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goto fail;
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}
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/* Regulator to enable GDSCs in downstream kernels */
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mdss->vdd = devm_regulator_get(dev->dev, "vdd");
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if (IS_ERR(mdss->vdd)) {
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ret = PTR_ERR(mdss->vdd);
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mdp5_mdss->vdd = devm_regulator_get(dev->dev, "vdd");
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if (IS_ERR(mdp5_mdss->vdd)) {
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ret = PTR_ERR(mdp5_mdss->vdd);
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goto fail;
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}
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ret = regulator_enable(mdss->vdd);
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ret = regulator_enable(mdp5_mdss->vdd);
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if (ret) {
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dev_err(dev->dev, "failed to enable regulator vdd: %d\n",
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ret);
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@ -258,25 +265,26 @@ int msm_mdss_init(struct drm_device *dev)
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}
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ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0),
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mdss_irq, 0, "mdss_isr", mdss);
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mdss_irq, 0, "mdss_isr", mdp5_mdss);
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if (ret) {
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dev_err(dev->dev, "failed to init irq: %d\n", ret);
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goto fail_irq;
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}
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ret = mdss_irq_domain_init(mdss);
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ret = mdss_irq_domain_init(mdp5_mdss);
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if (ret) {
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dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret);
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goto fail_irq;
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}
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priv->mdss = mdss;
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mdp5_mdss->base.funcs = &mdss_funcs;
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priv->mdss = &mdp5_mdss->base;
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pm_runtime_enable(dev->dev);
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return 0;
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fail_irq:
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regulator_disable(mdss->vdd);
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regulator_disable(mdp5_mdss->vdd);
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fail:
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return ret;
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}
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@ -208,6 +208,7 @@ static int msm_drm_uninit(struct device *dev)
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struct drm_device *ddev = platform_get_drvdata(pdev);
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struct msm_drm_private *priv = ddev->dev_private;
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struct msm_kms *kms = priv->kms;
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struct msm_mdss *mdss = priv->mdss;
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struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
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struct vblank_event *vbl_ev, *tmp;
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@ -258,7 +259,8 @@ static int msm_drm_uninit(struct device *dev)
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component_unbind_all(dev, ddev);
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msm_mdss_destroy(ddev);
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if (mdss && mdss->funcs)
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mdss->funcs->destroy(ddev);
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ddev->dev_private = NULL;
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drm_dev_unref(ddev);
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@ -357,6 +359,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
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struct drm_device *ddev;
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struct msm_drm_private *priv;
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struct msm_kms *kms;
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struct msm_mdss *mdss;
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int ret;
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ddev = drm_dev_alloc(drv, dev);
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@ -376,13 +379,15 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
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ddev->dev_private = priv;
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priv->dev = ddev;
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ret = msm_mdss_init(ddev);
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ret = mdp5_mdss_init(ddev);
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if (ret) {
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kfree(priv);
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drm_dev_unref(ddev);
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return ret;
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}
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mdss = priv->mdss;
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priv->wq = alloc_ordered_workqueue("msm", 0);
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priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
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@ -396,7 +401,8 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv)
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/* Bind all our sub-components: */
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ret = component_bind_all(dev, ddev);
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if (ret) {
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msm_mdss_destroy(ddev);
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if (mdss && mdss->funcs)
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mdss->funcs->destroy(ddev);
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kfree(priv);
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drm_dev_unref(ddev);
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return ret;
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@ -924,11 +930,12 @@ static int msm_runtime_suspend(struct device *dev)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct msm_drm_private *priv = ddev->dev_private;
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struct msm_mdss *mdss = priv->mdss;
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DBG("");
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if (priv->mdss)
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return msm_mdss_disable(priv->mdss);
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if (mdss && mdss->funcs)
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return mdss->funcs->disable(mdss);
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return 0;
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}
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@ -937,11 +944,12 @@ static int msm_runtime_resume(struct device *dev)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct msm_drm_private *priv = ddev->dev_private;
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struct msm_mdss *mdss = priv->mdss;
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DBG("");
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if (priv->mdss)
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return msm_mdss_enable(priv->mdss);
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if (mdss && mdss->funcs)
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return mdss->funcs->enable(mdss);
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return 0;
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}
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@ -86,9 +86,18 @@ static inline void msm_kms_init(struct msm_kms *kms,
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struct msm_kms *mdp4_kms_init(struct drm_device *dev);
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struct msm_kms *mdp5_kms_init(struct drm_device *dev);
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int msm_mdss_init(struct drm_device *dev);
|
||||
void msm_mdss_destroy(struct drm_device *dev);
|
||||
int msm_mdss_enable(struct msm_mdss *mdss);
|
||||
int msm_mdss_disable(struct msm_mdss *mdss);
|
||||
|
||||
struct msm_mdss_funcs {
|
||||
int (*enable)(struct msm_mdss *mdss);
|
||||
int (*disable)(struct msm_mdss *mdss);
|
||||
void (*destroy)(struct drm_device *dev);
|
||||
};
|
||||
|
||||
struct msm_mdss {
|
||||
struct drm_device *dev;
|
||||
const struct msm_mdss_funcs *funcs;
|
||||
};
|
||||
|
||||
int mdp5_mdss_init(struct drm_device *dev);
|
||||
|
||||
#endif /* __MSM_KMS_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user