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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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usb: add APIs to access host registers from Tegra PHY
As Tegra PHY driver needs to access one of the host registers, added few APIs. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> [swarren: moved assignment of phy->is_ulpi_phy to previous patch.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Venu Byravarasu
Stephen Warren
parent
3f9db1a19a
commit
bbdabdb62d
@ -2,7 +2,7 @@
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* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2009 NVIDIA Corporation
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* Copyright (C) 2009 - 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -26,13 +26,18 @@
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/ehci_def.h>
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#include <linux/usb/tegra_usb_phy.h>
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#define TEGRA_USB_BASE 0xC5000000
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#define TEGRA_USB2_BASE 0xC5004000
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#define TEGRA_USB3_BASE 0xC5008000
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/* PORTSC registers */
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#define TEGRA_USB_PORTSC1 0x184
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#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
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#define TEGRA_USB_PORTSC1_PHCD (1 << 23)
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#define TEGRA_USB_DMA_ALIGN 32
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struct tegra_ehci_hcd {
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@ -605,6 +610,37 @@ static const struct dev_pm_ops tegra_ehci_pm_ops = {
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#endif
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/* Bits of PORTSC1, which will get cleared by writing 1 into them */
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#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
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void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val)
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{
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unsigned long val;
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struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
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void __iomem *base = hcd->regs;
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val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
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val &= ~TEGRA_USB_PORTSC1_PTS(3);
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val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3);
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writel(val, base + TEGRA_USB_PORTSC1);
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}
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EXPORT_SYMBOL_GPL(tegra_ehci_set_pts);
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void tegra_ehci_set_phcd(struct usb_phy *x, bool enable)
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{
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unsigned long val;
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struct usb_hcd *hcd = bus_to_hcd(x->otg->host);
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void __iomem *base = hcd->regs;
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val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
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if (enable)
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val |= TEGRA_USB_PORTSC1_PHCD;
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else
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val &= ~TEGRA_USB_PORTSC1_PHCD;
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writel(val, base + TEGRA_USB_PORTSC1);
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}
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EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd);
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static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
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static int tegra_ehci_probe(struct platform_device *pdev)
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@ -616,6 +652,7 @@ static int tegra_ehci_probe(struct platform_device *pdev)
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int err = 0;
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int irq;
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int instance = pdev->id;
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struct usb_phy *u_phy;
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pdata = pdev->dev.platform_data;
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if (!pdata) {
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@ -718,6 +755,16 @@ static int tegra_ehci_probe(struct platform_device *pdev)
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usb_phy_init(&tegra->phy->u_phy);
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hcd->phy = u_phy = &tegra->phy->u_phy;
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u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
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GFP_KERNEL);
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if (!u_phy->otg) {
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dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
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err = -ENOMEM;
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goto fail_io;
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}
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u_phy->otg->host = hcd_to_bus(hcd);
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err = usb_phy_set_suspend(&tegra->phy->u_phy, 0);
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if (err) {
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dev_err(&pdev->dev, "Failed to power on the phy\n");
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@ -36,19 +36,6 @@
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#define ULPI_VIEWPORT 0x170
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#define USB_PORTSC1 0x184
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#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
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#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
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#define USB_PORTSC1_PHCD (1 << 23)
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#define USB_PORTSC1_WKOC (1 << 22)
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#define USB_PORTSC1_WKDS (1 << 21)
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#define USB_PORTSC1_WKCN (1 << 20)
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#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
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#define USB_PORTSC1_PP (1 << 12)
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#define USB_PORTSC1_SUSP (1 << 7)
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#define USB_PORTSC1_PE (1 << 2)
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#define USB_PORTSC1_CCS (1 << 0)
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#define USB_SUSP_CTRL 0x400
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#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
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#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
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@ -311,11 +298,8 @@ static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
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val = readl(base + USB_SUSP_CTRL);
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val &= ~USB_SUSP_SET;
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writel(val, base + USB_SUSP_CTRL);
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} else {
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val = readl(base + USB_PORTSC1);
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val |= USB_PORTSC1_PHCD;
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writel(val, base + USB_PORTSC1);
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}
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} else
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tegra_ehci_set_phcd(&phy->u_phy, true);
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if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
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pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
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@ -336,11 +320,8 @@ static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
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val = readl(base + USB_SUSP_CTRL);
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val &= ~USB_SUSP_CLR;
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writel(val, base + USB_SUSP_CTRL);
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} else {
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val = readl(base + USB_PORTSC1);
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val &= ~USB_PORTSC1_PHCD;
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writel(val, base + USB_PORTSC1);
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}
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} else
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tegra_ehci_set_phcd(&phy->u_phy, false);
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if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
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USB_PHY_CLK_VALID))
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@ -462,11 +443,8 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
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utmi_phy_clk_enable(phy);
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if (!phy->is_legacy_phy) {
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val = readl(base + USB_PORTSC1);
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val &= ~USB_PORTSC1_PTS(~0);
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writel(val, base + USB_PORTSC1);
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}
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if (!phy->is_legacy_phy)
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tegra_ehci_set_pts(&phy->u_phy, 0);
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return 0;
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}
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@ -611,10 +589,6 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
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return ret;
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}
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val = readl(base + USB_PORTSC1);
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val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
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writel(val, base + USB_PORTSC1);
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val = readl(base + USB_SUSP_CTRL);
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val |= USB_SUSP_CLR;
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writel(val, base + USB_SUSP_CTRL);
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@ -629,17 +603,8 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
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static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
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{
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unsigned long val;
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void __iomem *base = phy->regs;
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struct tegra_ulpi_config *config = phy->config;
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/* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
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* Controller to immediately bring the ULPI PHY out of low power
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*/
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val = readl(base + USB_PORTSC1);
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val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
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writel(val, base + USB_PORTSC1);
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clk_disable(phy->clk);
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return gpio_direction_output(config->reset_gpio, 0);
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}
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@ -75,4 +75,8 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
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void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
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void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val);
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void tegra_ehci_set_phcd(struct usb_phy *x, bool enable);
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#endif /* __TEGRA_USB_PHY_H */
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