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mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC
Added MMC_DDR52 as eMMC's DDR mode is distinguished from SD-UHS. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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@ -1510,6 +1510,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
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/* In case of UHS-I modes, set High Speed Enable */
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if ((ios->timing == MMC_TIMING_MMC_HS200) ||
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(ios->timing == MMC_TIMING_MMC_DDR52) ||
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(ios->timing == MMC_TIMING_UHS_SDR50) ||
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(ios->timing == MMC_TIMING_UHS_SDR104) ||
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(ios->timing == MMC_TIMING_UHS_DDR50) ||
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@ -1570,7 +1571,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (ios->timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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else if (ios->timing == MMC_TIMING_UHS_DDR50)
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else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
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(ios->timing == MMC_TIMING_MMC_DDR52))
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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