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drm/i915: Use a loop for the "three times for luck" DPLL procedure
The magic "enable the DPLL three times" sequence feels like it deserves a loop. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170601143619.27840-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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@ -1550,6 +1550,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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i915_reg_t reg = DPLL(crtc->pipe);
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i915_reg_t reg = DPLL(crtc->pipe);
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u32 dpll = crtc->config->dpll_hw_state.dpll;
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u32 dpll = crtc->config->dpll_hw_state.dpll;
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int i;
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assert_pipe_disabled(dev_priv, crtc->pipe);
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assert_pipe_disabled(dev_priv, crtc->pipe);
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@ -1596,15 +1597,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
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}
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}
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/* We do this three times for luck */
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/* We do this three times for luck */
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I915_WRITE(reg, dpll);
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for (i = 0; i < 3; i++) {
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POSTING_READ(reg);
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I915_WRITE(reg, dpll);
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udelay(150); /* wait for warmup */
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POSTING_READ(reg);
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I915_WRITE(reg, dpll);
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udelay(150); /* wait for warmup */
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POSTING_READ(reg);
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}
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udelay(150); /* wait for warmup */
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I915_WRITE(reg, dpll);
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POSTING_READ(reg);
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udelay(150); /* wait for warmup */
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}
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}
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/**
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/**
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