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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'Add-new-PCI_DEV_FLAGS_NO_RELAXED_ORDERING-flag'
Ding Tianhong says:
====================
Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Some devices have problems with Transaction Layer Packets with the Relaxed
Ordering Attribute set. This patch set adds a new PCIe Device Flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
devices with Relaxed Ordering issues, and a use of this new flag by the
cxgb4 driver to avoid using Relaxed Ordering with problematic Root Complex
Ports.
It's been years since I've submitted kernel.org patches, I appolgise for the
almost certain submission errors.
v2: Alexander point out that the v1 was only a part of the whole solution,
some platform which has some issues could use the new flag to indicate
that it is not safe to enable relaxed ordering attribute, then we need
to clear the relaxed ordering enable bits in the PCI configuration when
initializing the device. So add a new second patch to modify the PCI
initialization code to clear the relaxed ordering enable bit in the
event that the root complex doesn't want relaxed ordering enabled.
The third patch was base on the v1's second patch and only be changed
to query the relaxed ordering enable bit in the PCI configuration space
to allow the Chelsio NIC to send TLPs with the relaxed ordering attributes
set.
This version didn't plan to drop the defines for Intel Drivers to use the
new checking way to enable relaxed ordering because it is not the hardest
part of the moment, we could fix it in next patchset when this patches
reach the goal.
v3: Redesigned the logic for pci_configure_relaxed_ordering when configuration,
If a PCIe device didn't enable the relaxed ordering attribute default,
we should not do anything in the PCIe configuration, otherwise we
should check if any of the devices above us do not support relaxed
ordering by the PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag, then base on
the result if we get a return that indicate that the relaxed ordering
is not supported we should update our device to disable relaxed ordering
in configuration space. If the device above us doesn't exist or isn't
the PCIe device, we shouldn't do anything and skip updating relaxed ordering
because we are probably running in a guest.
v4: Rename the functions pcie_get_relaxed_ordering and pcie_disable_relaxed_ordering
according John's suggestion, and modify the description, use the true/false
as the return value.
We shouldn't enable relaxed ordering attribute by the setting in the root
complex configuration space for PCIe device, so fix it for cxgb4.
Fix some format issues.
v5: Removed the unnecessary code for some function which only return the bool
value, and add the check for VF device.
Make this patch set base on 4.12-rc5.
v6: Fix the logic error in the need to enable the relaxed ordering attribute for cxgb4.
v7: The cxgb4 drivers will enable the PCIe Capability Device Control[Relaxed
Ordering Enable] in PCI Probe() routine, this will break our current
solution for some platform which has problematic when enable the relaxed
ordering attribute. According to the latest recommendations, remove the
enable_pcie_relaxed_ordering(), although it could not cover the Peer-to-Peer
scene, but we agree to leave this problem until we really trigger it.
Make this patch set base on 4.12 release version.
v8: Change the second patch title and description to make it more reasonable,
add the acked-by from Alex and Ashok.
Add a new patch to enable the Relaxed Ordering Attribute for cxgb4vf driver.
Make this patch set base on 4.13-rc2.
v9: The document (https://software.intel.com/sites/default/files/managed/9e/
bc/64-ia-32-architectures-optimization-manual.pdf) indicate that the Xeon
processors based on Broadwell/Haswell microarchitecture has the problem
with Relaxed Ordering Attribute enabled, so add the whole list Device ID
from Intel to the patch.
v10: Significant rework based on Bjorn's feedback, reorganize the first 2 patches,
now the Intel and AMD erratum soc has been divided to the different patches,
rename the pcie_relaxed_ordering_supported() to pcie_relaxed_ordering_enabled(),
and no need to check every intervening switch except the root ports, update
some commits.
v11: We shouldn't let the Intel engineer to acked the AMD's erratum patch, fix the
funny mistake.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
bae514a688
@ -529,6 +529,7 @@ enum { /* adapter flags */
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USING_SOFT_PARAMS = (1 << 6),
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MASTER_PF = (1 << 7),
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FW_OFLD_CONN = (1 << 9),
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ROOT_NO_RELAXED_ORDERING = (1 << 10),
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};
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enum {
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@ -4654,11 +4654,6 @@ static void print_port_info(const struct net_device *dev)
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dev->name, adap->params.vpd.id, adap->name, buf);
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}
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static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
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{
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
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}
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/*
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* Free the following resources:
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* - memory used for tables
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@ -4908,7 +4903,6 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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pci_enable_pcie_error_reporting(pdev);
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enable_pcie_relaxed_ordering(pdev);
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pci_set_master(pdev);
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pci_save_state(pdev);
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@ -4947,6 +4941,23 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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adapter->msg_enable = DFLT_MSG_ENABLE;
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memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
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/* If possible, we use PCIe Relaxed Ordering Attribute to deliver
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* Ingress Packet Data to Free List Buffers in order to allow for
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* chipset performance optimizations between the Root Complex and
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* Memory Controllers. (Messages to the associated Ingress Queue
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* notifying new Packet Placement in the Free Lists Buffers will be
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* send without the Relaxed Ordering Attribute thus guaranteeing that
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* all preceding PCIe Transaction Layer Packets will be processed
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* first.) But some Root Complexes have various issues with Upstream
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* Transaction Layer Packets with the Relaxed Ordering Attribute set.
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* The PCIe devices which under the Root Complexes will be cleared the
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* Relaxed Ordering bit in the configuration space, So we check our
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* PCIe configuration space to see if it's flagged with advice against
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* using Relaxed Ordering.
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*/
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if (!pcie_relaxed_ordering_enabled(pdev))
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adapter->flags |= ROOT_NO_RELAXED_ORDERING;
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spin_lock_init(&adapter->stats_lock);
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spin_lock_init(&adapter->tid_release_lock);
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spin_lock_init(&adapter->win0_lock);
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@ -2719,6 +2719,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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struct fw_iq_cmd c;
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struct sge *s = &adap->sge;
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struct port_info *pi = netdev_priv(dev);
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int relaxed = !(adap->flags & ROOT_NO_RELAXED_ORDERING);
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/* Size needs to be multiple of 16, including status entry. */
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iq->size = roundup(iq->size, 16);
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@ -2772,8 +2773,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
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flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
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c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
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FW_IQ_CMD_FL0FETCHRO_F |
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FW_IQ_CMD_FL0DATARO_F |
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FW_IQ_CMD_FL0FETCHRO_V(relaxed) |
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FW_IQ_CMD_FL0DATARO_V(relaxed) |
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FW_IQ_CMD_FL0PADEN_F);
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if (cong >= 0)
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c.iqns_to_fl0congen |=
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@ -408,6 +408,7 @@ enum { /* adapter flags */
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USING_MSI = (1UL << 1),
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USING_MSIX = (1UL << 2),
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QUEUES_BOUND = (1UL << 3),
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ROOT_NO_RELAXED_ORDERING = (1UL << 4),
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};
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/*
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@ -2888,6 +2888,24 @@ static int cxgb4vf_pci_probe(struct pci_dev *pdev,
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*/
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adapter->name = pci_name(pdev);
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adapter->msg_enable = DFLT_MSG_ENABLE;
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/* If possible, we use PCIe Relaxed Ordering Attribute to deliver
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* Ingress Packet Data to Free List Buffers in order to allow for
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* chipset performance optimizations between the Root Complex and
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* Memory Controllers. (Messages to the associated Ingress Queue
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* notifying new Packet Placement in the Free Lists Buffers will be
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* send without the Relaxed Ordering Attribute thus guaranteeing that
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* all preceding PCIe Transaction Layer Packets will be processed
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* first.) But some Root Complexes have various issues with Upstream
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* Transaction Layer Packets with the Relaxed Ordering Attribute set.
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* The PCIe devices which under the Root Complexes will be cleared the
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* Relaxed Ordering bit in the configuration space, So we check our
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* PCIe configuration space to see if it's flagged with advice against
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* using Relaxed Ordering.
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*/
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if (!pcie_relaxed_ordering_enabled(pdev))
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adapter->flags |= ROOT_NO_RELAXED_ORDERING;
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err = adap_init0(adapter);
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if (err)
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goto err_unmap_bar;
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@ -2205,6 +2205,7 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
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struct port_info *pi = netdev_priv(dev);
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struct fw_iq_cmd cmd, rpl;
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int ret, iqandst, flsz = 0;
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int relaxed = !(adapter->flags & ROOT_NO_RELAXED_ORDERING);
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/*
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* If we're using MSI interrupts and we're not initializing the
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@ -2300,6 +2301,8 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
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cpu_to_be32(
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FW_IQ_CMD_FL0HOSTFCMODE_V(SGE_HOSTFCMODE_NONE) |
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FW_IQ_CMD_FL0PACKEN_F |
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FW_IQ_CMD_FL0FETCHRO_V(relaxed) |
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FW_IQ_CMD_FL0DATARO_V(relaxed) |
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FW_IQ_CMD_FL0PADEN_F);
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/* In T6, for egress queue type FL there is internal overhead
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@ -1762,6 +1762,48 @@ static void pci_configure_extended_tags(struct pci_dev *dev)
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PCI_EXP_DEVCTL_EXT_TAG);
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}
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/**
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* pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
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* @dev: PCI device to query
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*
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* Returns true if the device has enabled relaxed ordering attribute.
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*/
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bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
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{
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u16 v;
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pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
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return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
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}
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EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
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static void pci_configure_relaxed_ordering(struct pci_dev *dev)
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{
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struct pci_dev *root;
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/* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
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if (dev->is_virtfn)
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return;
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if (!pcie_relaxed_ordering_enabled(dev))
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return;
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/*
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* For now, we only deal with Relaxed Ordering issues with Root
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* Ports. Peer-to-Peer DMA is another can of worms.
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*/
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root = pci_find_pcie_root_port(dev);
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if (!root)
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return;
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if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_RELAX_EN);
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dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
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}
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}
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static void pci_configure_device(struct pci_dev *dev)
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{
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struct hotplug_params hpp;
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@ -1769,6 +1811,7 @@ static void pci_configure_device(struct pci_dev *dev)
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pci_configure_mps(dev);
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pci_configure_extended_tags(dev);
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pci_configure_relaxed_ordering(dev);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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@ -4015,6 +4015,95 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
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DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
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quirk_tw686x_class);
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/*
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* Some devices have problems with Transaction Layer Packets with the Relaxed
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* Ordering Attribute set. Such devices should mark themselves and other
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* Device Drivers should check before sending TLPs with RO set.
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*/
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static void quirk_relaxedordering_disable(struct pci_dev *dev)
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{
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dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
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dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
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}
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/*
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* Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
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* Complex has a Flow Control Credit issue which can cause performance
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* problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
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*/
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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/*
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* The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
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* where Upstream Transaction Layer Packets with the Relaxed Ordering
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* Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
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* set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
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* outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
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* November 10, 2010). As a result, on this platform we can't use Relaxed
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* Ordering for Upstream TLPs.
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*/
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
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quirk_relaxedordering_disable);
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/*
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* Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
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* values for the Attribute as were supplied in the header of the
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@ -188,6 +188,8 @@ enum pci_dev_flags {
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* the direct_complete optimization.
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*/
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PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
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/* Don't use Relaxed Ordering for TLPs directed at this device */
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PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
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};
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enum pci_irq_reroute_variant {
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@ -1125,6 +1127,7 @@ bool pci_check_pme_status(struct pci_dev *dev);
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void pci_pme_wakeup_bus(struct pci_bus *bus);
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void pci_d3cold_enable(struct pci_dev *dev);
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void pci_d3cold_disable(struct pci_dev *dev);
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bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
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/* PCI Virtual Channel */
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int pci_save_vc_state(struct pci_dev *dev);
|
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|
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