mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-02-08 04:05:17 +07:00
Merge remote branch 'korg/drm-radeon-cayman' into drm-core-next
* korg/drm-radeon-cayman: drm/radeon/kms: add cayman pci ids drm/radeon/kms: cayman/evergreen cs checker updates drm/radeon/kms/cayman: always set certain VGT regs at CP init drm/radeon/kms: additional default context regs for cayman drm/radeon/kms: add cayman CS check support drm/radeon/kms: add radeon_asic entry for cayman drm/radeon/kms: add cayman safe regs drm/radeon/kms/cayman: add asic init/startup/fini/suspend/resume functions drm/radeon/kms: add cayman asic reset support drm/radeon/kms: add support for cayman irqs drm/radeon/kms: add support for CP setup on cayman asics drm/radeon/kms: add support for cayman gart setup drm/radeon/kms: add gpu_init function for cayman drm/radeon/kms: add ucode loader for cayman drm/radeon/kms: add cayman chip family
This commit is contained in:
Dave Airlie
commit
ba77a26cb5
@ -36,6 +36,9 @@ $(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable
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$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable
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$(call if_changed,mkregtable)
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$(obj)/cayman_reg_safe.h: $(src)/reg_srcs/cayman $(obj)/mkregtable
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$(call if_changed,mkregtable)
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$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h
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$(obj)/r200.o: $(obj)/r200_reg_safe.h
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@ -50,7 +53,7 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
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$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
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$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h
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$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
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radeon_irq.o r300_cmdbuf.o r600_cp.o
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@ -66,7 +69,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
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r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
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radeon_trace_points.o ni.o
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radeon_trace_points.o ni.o cayman_blit_shaders.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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55
drivers/gpu/drm/radeon/cayman_blit_shaders.c
Normal file
55
drivers/gpu/drm/radeon/cayman_blit_shaders.c
Normal file
@ -0,0 +1,55 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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/*
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* evergreen cards need to use the 3D engine to blit data which requires
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* quite a bit of hw state setup. Rather than pull the whole 3D driver
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* (which normally generates the 3D state) into the DRM, we opt to use
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* statically generated state tables. The regsiter state and shaders
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* were hand generated to support blitting functionality. See the 3D
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* driver or documentation for descriptions of the registers and
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* shader instructions.
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*/
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const u32 cayman_default_state[] =
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{
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/* XXX fill in additional blit state */
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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0xc0026900,
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0x000000d9,
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0x00000000, /* CP_RINGID */
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0x00000000, /* CP_VMID */
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};
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const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
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32
drivers/gpu/drm/radeon/cayman_blit_shaders.h
Normal file
32
drivers/gpu/drm/radeon/cayman_blit_shaders.h
Normal file
@ -0,0 +1,32 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef CAYMAN_BLIT_SHADERS_H
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#define CAYMAN_BLIT_SHADERS_H
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extern const u32 cayman_default_state[];
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extern const u32 cayman_default_size;
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#endif
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@ -804,7 +804,7 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
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}
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}
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static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
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int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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u32 tmp;
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@ -957,7 +957,7 @@ void evergreen_agp_enable(struct radeon_device *rdev)
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WREG32(VM_CONTEXT1_CNTL, 0);
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}
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static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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save->vga_control[0] = RREG32(D1VGA_CONTROL);
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save->vga_control[1] = RREG32(D2VGA_CONTROL);
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@ -1011,7 +1011,7 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
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WREG32(EVERGREEN_D6VGA_CONTROL, 0);
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}
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static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
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{
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WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
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upper_32_bits(rdev->mc.vram_start));
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@ -1108,7 +1108,7 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
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WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
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}
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static void evergreen_mc_program(struct radeon_device *rdev)
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void evergreen_mc_program(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 tmp;
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@ -2565,7 +2565,7 @@ void evergreen_irq_disable(struct radeon_device *rdev)
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evergreen_disable_interrupt_state(rdev);
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}
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static void evergreen_irq_suspend(struct radeon_device *rdev)
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void evergreen_irq_suspend(struct radeon_device *rdev)
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{
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evergreen_irq_disable(rdev);
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r600_rlc_stop(rdev);
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@ -2888,7 +2888,7 @@ static int evergreen_startup(struct radeon_device *rdev)
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return r;
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}
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}
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r = btc_mc_load_microcode(rdev);
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r = ni_mc_load_microcode(rdev);
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if (r) {
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DRM_ERROR("Failed to load MC firmware!\n");
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return r;
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@ -2970,7 +2970,7 @@ int evergreen_resume(struct radeon_device *rdev)
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r = evergreen_startup(rdev);
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if (r) {
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DRM_ERROR("r600 startup failed on resume\n");
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DRM_ERROR("evergreen startup failed on resume\n");
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return r;
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}
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@ -3050,7 +3050,7 @@ int evergreen_init(struct radeon_device *rdev)
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}
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/* Must be an ATOMBIOS */
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if (!rdev->is_atom_bios) {
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dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
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dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
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return -EINVAL;
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}
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r = radeon_atombios_init(rdev);
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@ -29,6 +29,7 @@
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#include "radeon.h"
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#include "evergreend.h"
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#include "evergreen_reg_safe.h"
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#include "cayman_reg_safe.h"
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static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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@ -425,18 +426,28 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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{
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struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
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struct radeon_cs_reloc *reloc;
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u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
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u32 last_reg;
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u32 m, i, tmp, *ib;
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int r;
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if (p->rdev->family >= CHIP_CAYMAN)
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last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
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else
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last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
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i = (reg >> 7);
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if (i > last_reg) {
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dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
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return -EINVAL;
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}
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m = 1 << ((reg >> 2) & 31);
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if (!(evergreen_reg_safe_bm[i] & m))
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return 0;
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if (p->rdev->family >= CHIP_CAYMAN) {
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if (!(cayman_reg_safe_bm[i] & m))
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return 0;
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} else {
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if (!(evergreen_reg_safe_bm[i] & m))
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return 0;
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}
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ib = p->ib->ptr;
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switch (reg) {
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/* force following reg to 0 in an attemp to disable out buffer
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@ -468,12 +479,42 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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case SQ_VSTMP_RING_ITEMSIZE:
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case VGT_TF_RING_SIZE:
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/* get value to populate the IB don't remove */
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tmp =radeon_get_ib_value(p, idx);
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ib[idx] = 0;
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/*tmp =radeon_get_ib_value(p, idx);
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ib[idx] = 0;*/
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break;
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case SQ_ESGS_RING_BASE:
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case SQ_GSVS_RING_BASE:
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case SQ_ESTMP_RING_BASE:
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case SQ_GSTMP_RING_BASE:
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case SQ_HSTMP_RING_BASE:
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case SQ_LSTMP_RING_BASE:
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case SQ_PSTMP_RING_BASE:
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case SQ_VSTMP_RING_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
|
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if (r) {
|
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
|
||||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
|
||||
break;
|
||||
case DB_DEPTH_CONTROL:
|
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track->db_depth_control = radeon_get_ib_value(p, idx);
|
||||
break;
|
||||
case CAYMAN_DB_EQAA:
|
||||
if (p->rdev->family < CHIP_CAYMAN) {
|
||||
dev_warn(p->dev, "bad SET_CONTEXT_REG "
|
||||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case CAYMAN_DB_DEPTH_INFO:
|
||||
if (p->rdev->family < CHIP_CAYMAN) {
|
||||
dev_warn(p->dev, "bad SET_CONTEXT_REG "
|
||||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case DB_Z_INFO:
|
||||
r = evergreen_cs_packet_next_reloc(p, &reloc);
|
||||
if (r) {
|
||||
@ -559,9 +600,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
|
||||
track->cb_shader_mask = radeon_get_ib_value(p, idx);
|
||||
break;
|
||||
case PA_SC_AA_CONFIG:
|
||||
if (p->rdev->family >= CHIP_CAYMAN) {
|
||||
dev_warn(p->dev, "bad SET_CONTEXT_REG "
|
||||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
|
||||
track->nsamples = 1 << tmp;
|
||||
break;
|
||||
case CAYMAN_PA_SC_AA_CONFIG:
|
||||
if (p->rdev->family < CHIP_CAYMAN) {
|
||||
dev_warn(p->dev, "bad SET_CONTEXT_REG "
|
||||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
|
||||
track->nsamples = 1 << tmp;
|
||||
break;
|
||||
case CB_COLOR0_VIEW:
|
||||
case CB_COLOR1_VIEW:
|
||||
case CB_COLOR2_VIEW:
|
||||
@ -987,6 +1042,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case CAYMAN_PACKET3_DEALLOC_STATE:
|
||||
if (p->rdev->family < CHIP_CAYMAN) {
|
||||
DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (pkt->count) {
|
||||
DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case PACKET3_INDEX_BASE:
|
||||
if (pkt->count != 1) {
|
||||
DRM_ERROR("bad INDEX_BASE\n");
|
||||
|
||||
@ -754,13 +754,21 @@
|
||||
|
||||
#define SQ_CONST_MEM_BASE 0x8df8
|
||||
|
||||
#define SQ_ESGS_RING_BASE 0x8c40
|
||||
#define SQ_ESGS_RING_SIZE 0x8c44
|
||||
#define SQ_GSVS_RING_BASE 0x8c48
|
||||
#define SQ_GSVS_RING_SIZE 0x8c4c
|
||||
#define SQ_ESTMP_RING_BASE 0x8c50
|
||||
#define SQ_ESTMP_RING_SIZE 0x8c54
|
||||
#define SQ_GSTMP_RING_BASE 0x8c58
|
||||
#define SQ_GSTMP_RING_SIZE 0x8c5c
|
||||
#define SQ_VSTMP_RING_BASE 0x8c60
|
||||
#define SQ_VSTMP_RING_SIZE 0x8c64
|
||||
#define SQ_PSTMP_RING_BASE 0x8c68
|
||||
#define SQ_PSTMP_RING_SIZE 0x8c6c
|
||||
#define SQ_LSTMP_RING_BASE 0x8e10
|
||||
#define SQ_LSTMP_RING_SIZE 0x8e14
|
||||
#define SQ_HSTMP_RING_BASE 0x8e18
|
||||
#define SQ_HSTMP_RING_SIZE 0x8e1c
|
||||
#define VGT_TF_RING_SIZE 0x8988
|
||||
|
||||
@ -1092,5 +1100,14 @@
|
||||
#define SQ_TEX_RESOURCE_WORD6_0 0x30018
|
||||
#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
|
||||
|
||||
/* cayman 3D regs */
|
||||
#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
|
||||
#define CAYMAN_DB_EQAA 0x28804
|
||||
#define CAYMAN_DB_DEPTH_INFO 0x2803C
|
||||
#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
|
||||
#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
|
||||
#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
|
||||
/* cayman packet3 addition */
|
||||
#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -24,7 +24,101 @@
|
||||
#ifndef NI_H
|
||||
#define NI_H
|
||||
|
||||
#define CAYMAN_MAX_SH_GPRS 256
|
||||
#define CAYMAN_MAX_TEMP_GPRS 16
|
||||
#define CAYMAN_MAX_SH_THREADS 256
|
||||
#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
|
||||
#define CAYMAN_MAX_FRC_EOV_CNT 16384
|
||||
#define CAYMAN_MAX_BACKENDS 8
|
||||
#define CAYMAN_MAX_BACKENDS_MASK 0xFF
|
||||
#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
|
||||
#define CAYMAN_MAX_SIMDS 16
|
||||
#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
|
||||
#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
|
||||
#define CAYMAN_MAX_PIPES 8
|
||||
#define CAYMAN_MAX_PIPES_MASK 0xFF
|
||||
#define CAYMAN_MAX_LDS_NUM 0xFFFF
|
||||
#define CAYMAN_MAX_TCC 16
|
||||
#define CAYMAN_MAX_TCC_MASK 0xFF
|
||||
|
||||
#define DMIF_ADDR_CONFIG 0xBD4
|
||||
#define SRBM_STATUS 0x0E50
|
||||
|
||||
#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
|
||||
#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
|
||||
#define RESPONSE_TYPE_MASK 0x000000F0
|
||||
#define RESPONSE_TYPE_SHIFT 4
|
||||
#define VM_L2_CNTL 0x1400
|
||||
#define ENABLE_L2_CACHE (1 << 0)
|
||||
#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
|
||||
#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
|
||||
#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
|
||||
#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
|
||||
#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
|
||||
/* CONTEXT1_IDENTITY_ACCESS_MODE
|
||||
* 0 physical = logical
|
||||
* 1 logical via context1 page table
|
||||
* 2 inside identity aperture use translation, outside physical = logical
|
||||
* 3 inside identity aperture physical = logical, outside use translation
|
||||
*/
|
||||
#define VM_L2_CNTL2 0x1404
|
||||
#define INVALIDATE_ALL_L1_TLBS (1 << 0)
|
||||
#define INVALIDATE_L2_CACHE (1 << 1)
|
||||
#define VM_L2_CNTL3 0x1408
|
||||
#define BANK_SELECT(x) ((x) << 0)
|
||||
#define CACHE_UPDATE_MODE(x) ((x) << 6)
|
||||
#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
|
||||
#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
|
||||
#define VM_L2_STATUS 0x140C
|
||||
#define L2_BUSY (1 << 0)
|
||||
#define VM_CONTEXT0_CNTL 0x1410
|
||||
#define ENABLE_CONTEXT (1 << 0)
|
||||
#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
|
||||
#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
|
||||
#define VM_CONTEXT1_CNTL 0x1414
|
||||
#define VM_CONTEXT0_CNTL2 0x1430
|
||||
#define VM_CONTEXT1_CNTL2 0x1434
|
||||
#define VM_INVALIDATE_REQUEST 0x1478
|
||||
#define VM_INVALIDATE_RESPONSE 0x147c
|
||||
#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
|
||||
#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
|
||||
#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
|
||||
#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
|
||||
|
||||
#define MC_SHARED_CHMAP 0x2004
|
||||
#define NOOFCHAN_SHIFT 12
|
||||
#define NOOFCHAN_MASK 0x00003000
|
||||
#define MC_SHARED_CHREMAP 0x2008
|
||||
|
||||
#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
|
||||
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
|
||||
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
|
||||
#define MC_VM_MX_L1_TLB_CNTL 0x2064
|
||||
#define ENABLE_L1_TLB (1 << 0)
|
||||
#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
|
||||
#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
|
||||
#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
|
||||
#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
|
||||
#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
|
||||
|
||||
#define MC_SHARED_BLACKOUT_CNTL 0x20ac
|
||||
#define MC_ARB_RAMCFG 0x2760
|
||||
#define NOOFBANK_SHIFT 0
|
||||
#define NOOFBANK_MASK 0x00000003
|
||||
#define NOOFRANK_SHIFT 2
|
||||
#define NOOFRANK_MASK 0x00000004
|
||||
#define NOOFROWS_SHIFT 3
|
||||
#define NOOFROWS_MASK 0x00000038
|
||||
#define NOOFCOLS_SHIFT 6
|
||||
#define NOOFCOLS_MASK 0x000000C0
|
||||
#define CHANSIZE_SHIFT 8
|
||||
#define CHANSIZE_MASK 0x00000100
|
||||
#define BURSTLENGTH_SHIFT 9
|
||||
#define BURSTLENGTH_MASK 0x00000200
|
||||
#define CHANSIZE_OVERRIDE (1 << 11)
|
||||
#define MC_SEQ_SUP_CNTL 0x28c8
|
||||
#define RUN_MASK (1 << 0)
|
||||
#define MC_SEQ_SUP_PGM 0x28cc
|
||||
@ -37,5 +131,406 @@
|
||||
#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
|
||||
#define MC_SEQ_IO_DEBUG_DATA 0x2a48
|
||||
|
||||
#define HDP_HOST_PATH_CNTL 0x2C00
|
||||
#define HDP_NONSURFACE_BASE 0x2C04
|
||||
#define HDP_NONSURFACE_INFO 0x2C08
|
||||
#define HDP_NONSURFACE_SIZE 0x2C0C
|
||||
#define HDP_ADDR_CONFIG 0x2F48
|
||||
|
||||
#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
|
||||
#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
|
||||
#define CGTS_SYS_TCC_DISABLE 0x3F90
|
||||
#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
|
||||
|
||||
#define CONFIG_MEMSIZE 0x5428
|
||||
|
||||
#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
|
||||
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
|
||||
|
||||
#define GRBM_CNTL 0x8000
|
||||
#define GRBM_READ_TIMEOUT(x) ((x) << 0)
|
||||
#define GRBM_STATUS 0x8010
|
||||
#define CMDFIFO_AVAIL_MASK 0x0000000F
|
||||
#define RING2_RQ_PENDING (1 << 4)
|
||||
#define SRBM_RQ_PENDING (1 << 5)
|
||||
#define RING1_RQ_PENDING (1 << 6)
|
||||
#define CF_RQ_PENDING (1 << 7)
|
||||
#define PF_RQ_PENDING (1 << 8)
|
||||
#define GDS_DMA_RQ_PENDING (1 << 9)
|
||||
#define GRBM_EE_BUSY (1 << 10)
|
||||
#define SX_CLEAN (1 << 11)
|
||||
#define DB_CLEAN (1 << 12)
|
||||
#define CB_CLEAN (1 << 13)
|
||||
#define TA_BUSY (1 << 14)
|
||||
#define GDS_BUSY (1 << 15)
|
||||
#define VGT_BUSY_NO_DMA (1 << 16)
|
||||
#define VGT_BUSY (1 << 17)
|
||||
#define IA_BUSY_NO_DMA (1 << 18)
|
||||
#define IA_BUSY (1 << 19)
|
||||
#define SX_BUSY (1 << 20)
|
||||
#define SH_BUSY (1 << 21)
|
||||
#define SPI_BUSY (1 << 22)
|
||||
#define SC_BUSY (1 << 24)
|
||||
#define PA_BUSY (1 << 25)
|
||||
#define DB_BUSY (1 << 26)
|
||||
#define CP_COHERENCY_BUSY (1 << 28)
|
||||
#define CP_BUSY (1 << 29)
|
||||
#define CB_BUSY (1 << 30)
|
||||
#define GUI_ACTIVE (1 << 31)
|
||||
#define GRBM_STATUS_SE0 0x8014
|
||||
#define GRBM_STATUS_SE1 0x8018
|
||||
#define SE_SX_CLEAN (1 << 0)
|
||||
#define SE_DB_CLEAN (1 << 1)
|
||||
#define SE_CB_CLEAN (1 << 2)
|
||||
#define SE_VGT_BUSY (1 << 23)
|
||||
#define SE_PA_BUSY (1 << 24)
|
||||
#define SE_TA_BUSY (1 << 25)
|
||||
#define SE_SX_BUSY (1 << 26)
|
||||
#define SE_SPI_BUSY (1 << 27)
|
||||
#define SE_SH_BUSY (1 << 28)
|
||||
#define SE_SC_BUSY (1 << 29)
|
||||
#define SE_DB_BUSY (1 << 30)
|
||||
#define SE_CB_BUSY (1 << 31)
|
||||
#define GRBM_SOFT_RESET 0x8020
|
||||
#define SOFT_RESET_CP (1 << 0)
|
||||
#define SOFT_RESET_CB (1 << 1)
|
||||
#define SOFT_RESET_DB (1 << 3)
|
||||
#define SOFT_RESET_GDS (1 << 4)
|
||||
#define SOFT_RESET_PA (1 << 5)
|
||||
#define SOFT_RESET_SC (1 << 6)
|
||||
#define SOFT_RESET_SPI (1 << 8)
|
||||
#define SOFT_RESET_SH (1 << 9)
|
||||
#define SOFT_RESET_SX (1 << 10)
|
||||
#define SOFT_RESET_TC (1 << 11)
|
||||
#define SOFT_RESET_TA (1 << 12)
|
||||
#define SOFT_RESET_VGT (1 << 14)
|
||||
#define SOFT_RESET_IA (1 << 15)
|
||||
|
||||
#define SCRATCH_REG0 0x8500
|
||||
#define SCRATCH_REG1 0x8504
|
||||
#define SCRATCH_REG2 0x8508
|
||||
#define SCRATCH_REG3 0x850C
|
||||
#define SCRATCH_REG4 0x8510
|
||||
#define SCRATCH_REG5 0x8514
|
||||
#define SCRATCH_REG6 0x8518
|
||||
#define SCRATCH_REG7 0x851C
|
||||
#define SCRATCH_UMSK 0x8540
|
||||
#define SCRATCH_ADDR 0x8544
|
||||
#define CP_SEM_WAIT_TIMER 0x85BC
|
||||
#define CP_ME_CNTL 0x86D8
|
||||
#define CP_ME_HALT (1 << 28)
|
||||
#define CP_PFP_HALT (1 << 26)
|
||||
#define CP_RB2_RPTR 0x86f8
|
||||
#define CP_RB1_RPTR 0x86fc
|
||||
#define CP_RB0_RPTR 0x8700
|
||||
#define CP_RB_WPTR_DELAY 0x8704
|
||||
#define CP_MEQ_THRESHOLDS 0x8764
|
||||
#define MEQ1_START(x) ((x) << 0)
|
||||
#define MEQ2_START(x) ((x) << 8)
|
||||
#define CP_PERFMON_CNTL 0x87FC
|
||||
|
||||
#define VGT_CACHE_INVALIDATION 0x88C4
|
||||
#define CACHE_INVALIDATION(x) ((x) << 0)
|
||||
#define VC_ONLY 0
|
||||
#define TC_ONLY 1
|
||||
#define VC_AND_TC 2
|
||||
#define AUTO_INVLD_EN(x) ((x) << 6)
|
||||
#define NO_AUTO 0
|
||||
#define ES_AUTO 1
|
||||
#define GS_AUTO 2
|
||||
#define ES_AND_GS_AUTO 3
|
||||
#define VGT_GS_VERTEX_REUSE 0x88D4
|
||||
|
||||
#define CC_GC_SHADER_PIPE_CONFIG 0x8950
|
||||
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
|
||||
#define INACTIVE_QD_PIPES(x) ((x) << 8)
|
||||
#define INACTIVE_QD_PIPES_MASK 0x0000FF00
|
||||
#define INACTIVE_QD_PIPES_SHIFT 8
|
||||
#define INACTIVE_SIMDS(x) ((x) << 16)
|
||||
#define INACTIVE_SIMDS_MASK 0xFFFF0000
|
||||
#define INACTIVE_SIMDS_SHIFT 16
|
||||
|
||||
#define VGT_PRIMITIVE_TYPE 0x8958
|
||||
#define VGT_NUM_INSTANCES 0x8974
|
||||
#define VGT_TF_RING_SIZE 0x8988
|
||||
#define VGT_OFFCHIP_LDS_BASE 0x89b4
|
||||
|
||||
#define PA_SC_LINE_STIPPLE_STATE 0x8B10
|
||||
#define PA_CL_ENHANCE 0x8A14
|
||||
#define CLIP_VTX_REORDER_ENA (1 << 0)
|
||||
#define NUM_CLIP_SEQ(x) ((x) << 1)
|
||||
#define PA_SC_FIFO_SIZE 0x8BCC
|
||||
#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
|
||||
#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
|
||||
#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
|
||||
#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
|
||||
#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
|
||||
#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
|
||||
|
||||
#define SQ_CONFIG 0x8C00
|
||||
#define VC_ENABLE (1 << 0)
|
||||
#define EXPORT_SRC_C (1 << 1)
|
||||
#define GFX_PRIO(x) ((x) << 2)
|
||||
#define CS1_PRIO(x) ((x) << 4)
|
||||
#define CS2_PRIO(x) ((x) << 6)
|
||||
#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
|
||||
#define NUM_PS_GPRS(x) ((x) << 0)
|
||||
#define NUM_VS_GPRS(x) ((x) << 16)
|
||||
#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
|
||||
#define SQ_ESGS_RING_SIZE 0x8c44
|
||||
#define SQ_GSVS_RING_SIZE 0x8c4c
|
||||
#define SQ_ESTMP_RING_BASE 0x8c50
|
||||
#define SQ_ESTMP_RING_SIZE 0x8c54
|
||||
#define SQ_GSTMP_RING_BASE 0x8c58
|
||||
#define SQ_GSTMP_RING_SIZE 0x8c5c
|
||||
#define SQ_VSTMP_RING_BASE 0x8c60
|
||||
#define SQ_VSTMP_RING_SIZE 0x8c64
|
||||
#define SQ_PSTMP_RING_BASE 0x8c68
|
||||
#define SQ_PSTMP_RING_SIZE 0x8c6c
|
||||
#define SQ_MS_FIFO_SIZES 0x8CF0
|
||||
#define CACHE_FIFO_SIZE(x) ((x) << 0)
|
||||
#define FETCH_FIFO_HIWATER(x) ((x) << 8)
|
||||
#define DONE_FIFO_HIWATER(x) ((x) << 16)
|
||||
#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
|
||||
#define SQ_LSTMP_RING_BASE 0x8e10
|
||||
#define SQ_LSTMP_RING_SIZE 0x8e14
|
||||
#define SQ_HSTMP_RING_BASE 0x8e18
|
||||
#define SQ_HSTMP_RING_SIZE 0x8e1c
|
||||
#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
|
||||
#define DYN_GPR_ENABLE (1 << 8)
|
||||
#define SQ_CONST_MEM_BASE 0x8df8
|
||||
|
||||
#define SX_EXPORT_BUFFER_SIZES 0x900C
|
||||
#define COLOR_BUFFER_SIZE(x) ((x) << 0)
|
||||
#define POSITION_BUFFER_SIZE(x) ((x) << 8)
|
||||
#define SMX_BUFFER_SIZE(x) ((x) << 16)
|
||||
#define SX_DEBUG_1 0x9058
|
||||
#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
|
||||
|
||||
#define SPI_CONFIG_CNTL 0x9100
|
||||
#define GPR_WRITE_PRIORITY(x) ((x) << 0)
|
||||
#define SPI_CONFIG_CNTL_1 0x913C
|
||||
#define VTX_DONE_DELAY(x) ((x) << 0)
|
||||
#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
|
||||
#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
|
||||
|
||||
#define CGTS_TCC_DISABLE 0x9148
|
||||
#define CGTS_USER_TCC_DISABLE 0x914C
|
||||
#define TCC_DISABLE_MASK 0xFFFF0000
|
||||
#define TCC_DISABLE_SHIFT 16
|
||||
#define CGTS_SM_CTRL_REG 0x915C
|
||||
#define OVERRIDE (1 << 21)
|
||||
|
||||
#define TA_CNTL_AUX 0x9508
|
||||
#define DISABLE_CUBE_WRAP (1 << 0)
|
||||
#define DISABLE_CUBE_ANISO (1 << 1)
|
||||
|
||||
#define TCP_CHAN_STEER_LO 0x960c
|
||||
#define TCP_CHAN_STEER_HI 0x9610
|
||||
|
||||
#define CC_RB_BACKEND_DISABLE 0x98F4
|
||||
#define BACKEND_DISABLE(x) ((x) << 16)
|
||||
#define GB_ADDR_CONFIG 0x98F8
|
||||
#define NUM_PIPES(x) ((x) << 0)
|
||||
#define NUM_PIPES_MASK 0x00000007
|
||||
#define NUM_PIPES_SHIFT 0
|
||||
#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
|
||||
#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
|
||||
#define PIPE_INTERLEAVE_SIZE_SHIFT 4
|
||||
#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
|
||||
#define NUM_SHADER_ENGINES(x) ((x) << 12)
|
||||
#define NUM_SHADER_ENGINES_MASK 0x00003000
|
||||
#define NUM_SHADER_ENGINES_SHIFT 12
|
||||
#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
|
||||
#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
|
||||
#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
|
||||
#define NUM_GPUS(x) ((x) << 20)
|
||||
#define NUM_GPUS_MASK 0x00700000
|
||||
#define NUM_GPUS_SHIFT 20
|
||||
#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
|
||||
#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
|
||||
#define MULTI_GPU_TILE_SIZE_SHIFT 24
|
||||
#define ROW_SIZE(x) ((x) << 28)
|
||||
#define ROW_SIZE_MASK 0x30000007
|
||||
#define ROW_SIZE_SHIFT 28
|
||||
#define NUM_LOWER_PIPES(x) ((x) << 30)
|
||||
#define NUM_LOWER_PIPES_MASK 0x40000000
|
||||
#define NUM_LOWER_PIPES_SHIFT 30
|
||||
#define GB_BACKEND_MAP 0x98FC
|
||||
|
||||
#define CB_PERF_CTR0_SEL_0 0x9A20
|
||||
#define CB_PERF_CTR0_SEL_1 0x9A24
|
||||
#define CB_PERF_CTR1_SEL_0 0x9A28
|
||||
#define CB_PERF_CTR1_SEL_1 0x9A2C
|
||||
#define CB_PERF_CTR2_SEL_0 0x9A30
|
||||
#define CB_PERF_CTR2_SEL_1 0x9A34
|
||||
#define CB_PERF_CTR3_SEL_0 0x9A38
|
||||
#define CB_PERF_CTR3_SEL_1 0x9A3C
|
||||
|
||||
#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
|
||||
#define BACKEND_DISABLE_MASK 0x00FF0000
|
||||
#define BACKEND_DISABLE_SHIFT 16
|
||||
|
||||
#define SMX_DC_CTL0 0xA020
|
||||
#define USE_HASH_FUNCTION (1 << 0)
|
||||
#define NUMBER_OF_SETS(x) ((x) << 1)
|
||||
#define FLUSH_ALL_ON_EVENT (1 << 10)
|
||||
#define STALL_ON_EVENT (1 << 11)
|
||||
#define SMX_EVENT_CTL 0xA02C
|
||||
#define ES_FLUSH_CTL(x) ((x) << 0)
|
||||
#define GS_FLUSH_CTL(x) ((x) << 3)
|
||||
#define ACK_FLUSH_CTL(x) ((x) << 6)
|
||||
#define SYNC_FLUSH_CTL (1 << 8)
|
||||
|
||||
#define CP_RB0_BASE 0xC100
|
||||
#define CP_RB0_CNTL 0xC104
|
||||
#define RB_BUFSZ(x) ((x) << 0)
|
||||
#define RB_BLKSZ(x) ((x) << 8)
|
||||
#define RB_NO_UPDATE (1 << 27)
|
||||
#define RB_RPTR_WR_ENA (1 << 31)
|
||||
#define BUF_SWAP_32BIT (2 << 16)
|
||||
#define CP_RB0_RPTR_ADDR 0xC10C
|
||||
#define CP_RB0_RPTR_ADDR_HI 0xC110
|
||||
#define CP_RB0_WPTR 0xC114
|
||||
#define CP_RB1_BASE 0xC180
|
||||
#define CP_RB1_CNTL 0xC184
|
||||
#define CP_RB1_RPTR_ADDR 0xC188
|
||||
#define CP_RB1_RPTR_ADDR_HI 0xC18C
|
||||
#define CP_RB1_WPTR 0xC190
|
||||
#define CP_RB2_BASE 0xC194
|
||||
#define CP_RB2_CNTL 0xC198
|
||||
#define CP_RB2_RPTR_ADDR 0xC19C
|
||||
#define CP_RB2_RPTR_ADDR_HI 0xC1A0
|
||||
#define CP_RB2_WPTR 0xC1A4
|
||||
#define CP_PFP_UCODE_ADDR 0xC150
|
||||
#define CP_PFP_UCODE_DATA 0xC154
|
||||
#define CP_ME_RAM_RADDR 0xC158
|
||||
#define CP_ME_RAM_WADDR 0xC15C
|
||||
#define CP_ME_RAM_DATA 0xC160
|
||||
#define CP_DEBUG 0xC1FC
|
||||
|
||||
/*
|
||||
* PM4
|
||||
*/
|
||||
#define PACKET_TYPE0 0
|
||||
#define PACKET_TYPE1 1
|
||||
#define PACKET_TYPE2 2
|
||||
#define PACKET_TYPE3 3
|
||||
|
||||
#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
|
||||
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
|
||||
#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
|
||||
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
|
||||
#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
||||
(((reg) >> 2) & 0xFFFF) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
#define CP_PACKET2 0x80000000
|
||||
#define PACKET2_PAD_SHIFT 0
|
||||
#define PACKET2_PAD_MASK (0x3fffffff << 0)
|
||||
|
||||
#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
|
||||
|
||||
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
|
||||
(((op) & 0xFF) << 8) | \
|
||||
((n) & 0x3FFF) << 16)
|
||||
|
||||
/* Packet 3 types */
|
||||
#define PACKET3_NOP 0x10
|
||||
#define PACKET3_SET_BASE 0x11
|
||||
#define PACKET3_CLEAR_STATE 0x12
|
||||
#define PACKET3_INDEX_BUFFER_SIZE 0x13
|
||||
#define PACKET3_DEALLOC_STATE 0x14
|
||||
#define PACKET3_DISPATCH_DIRECT 0x15
|
||||
#define PACKET3_DISPATCH_INDIRECT 0x16
|
||||
#define PACKET3_INDIRECT_BUFFER_END 0x17
|
||||
#define PACKET3_SET_PREDICATION 0x20
|
||||
#define PACKET3_REG_RMW 0x21
|
||||
#define PACKET3_COND_EXEC 0x22
|
||||
#define PACKET3_PRED_EXEC 0x23
|
||||
#define PACKET3_DRAW_INDIRECT 0x24
|
||||
#define PACKET3_DRAW_INDEX_INDIRECT 0x25
|
||||
#define PACKET3_INDEX_BASE 0x26
|
||||
#define PACKET3_DRAW_INDEX_2 0x27
|
||||
#define PACKET3_CONTEXT_CONTROL 0x28
|
||||
#define PACKET3_DRAW_INDEX_OFFSET 0x29
|
||||
#define PACKET3_INDEX_TYPE 0x2A
|
||||
#define PACKET3_DRAW_INDEX 0x2B
|
||||
#define PACKET3_DRAW_INDEX_AUTO 0x2D
|
||||
#define PACKET3_DRAW_INDEX_IMMD 0x2E
|
||||
#define PACKET3_NUM_INSTANCES 0x2F
|
||||
#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
|
||||
#define PACKET3_INDIRECT_BUFFER 0x32
|
||||
#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
|
||||
#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
|
||||
#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
|
||||
#define PACKET3_WRITE_DATA 0x37
|
||||
#define PACKET3_MEM_SEMAPHORE 0x39
|
||||
#define PACKET3_MPEG_INDEX 0x3A
|
||||
#define PACKET3_WAIT_REG_MEM 0x3C
|
||||
#define PACKET3_MEM_WRITE 0x3D
|
||||
#define PACKET3_SURFACE_SYNC 0x43
|
||||
# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
|
||||
# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
|
||||
# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
|
||||
# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
|
||||
# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
|
||||
# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
|
||||
# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
|
||||
# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
|
||||
# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
|
||||
# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
|
||||
# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
|
||||
# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
|
||||
# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
|
||||
# define PACKET3_FULL_CACHE_ENA (1 << 20)
|
||||
# define PACKET3_TC_ACTION_ENA (1 << 23)
|
||||
# define PACKET3_CB_ACTION_ENA (1 << 25)
|
||||
# define PACKET3_DB_ACTION_ENA (1 << 26)
|
||||
# define PACKET3_SH_ACTION_ENA (1 << 27)
|
||||
# define PACKET3_SX_ACTION_ENA (1 << 28)
|
||||
#define PACKET3_ME_INITIALIZE 0x44
|
||||
#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
|
||||
#define PACKET3_COND_WRITE 0x45
|
||||
#define PACKET3_EVENT_WRITE 0x46
|
||||
#define PACKET3_EVENT_WRITE_EOP 0x47
|
||||
#define PACKET3_EVENT_WRITE_EOS 0x48
|
||||
#define PACKET3_PREAMBLE_CNTL 0x4A
|
||||
# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
|
||||
# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
|
||||
#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
|
||||
#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
|
||||
#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
|
||||
#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
|
||||
#define PACKET3_ONE_REG_WRITE 0x57
|
||||
#define PACKET3_SET_CONFIG_REG 0x68
|
||||
#define PACKET3_SET_CONFIG_REG_START 0x00008000
|
||||
#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
|
||||
#define PACKET3_SET_CONTEXT_REG 0x69
|
||||
#define PACKET3_SET_CONTEXT_REG_START 0x00028000
|
||||
#define PACKET3_SET_CONTEXT_REG_END 0x00029000
|
||||
#define PACKET3_SET_ALU_CONST 0x6A
|
||||
/* alu const buffers only; no reg file */
|
||||
#define PACKET3_SET_BOOL_CONST 0x6B
|
||||
#define PACKET3_SET_BOOL_CONST_START 0x0003a500
|
||||
#define PACKET3_SET_BOOL_CONST_END 0x0003a518
|
||||
#define PACKET3_SET_LOOP_CONST 0x6C
|
||||
#define PACKET3_SET_LOOP_CONST_START 0x0003a200
|
||||
#define PACKET3_SET_LOOP_CONST_END 0x0003a500
|
||||
#define PACKET3_SET_RESOURCE 0x6D
|
||||
#define PACKET3_SET_RESOURCE_START 0x00030000
|
||||
#define PACKET3_SET_RESOURCE_END 0x00038000
|
||||
#define PACKET3_SET_SAMPLER 0x6E
|
||||
#define PACKET3_SET_SAMPLER_START 0x0003c000
|
||||
#define PACKET3_SET_SAMPLER_END 0x0003c600
|
||||
#define PACKET3_SET_CTL_CONST 0x6F
|
||||
#define PACKET3_SET_CTL_CONST_START 0x0003cff0
|
||||
#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
|
||||
#define PACKET3_SET_RESOURCE_OFFSET 0x70
|
||||
#define PACKET3_SET_ALU_CONST_VS 0x71
|
||||
#define PACKET3_SET_ALU_CONST_DI 0x72
|
||||
#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
|
||||
#define PACKET3_SET_RESOURCE_INDIRECT 0x74
|
||||
#define PACKET3_SET_APPEND_CNT 0x75
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -47,6 +47,7 @@
|
||||
#define EVERGREEN_PFP_UCODE_SIZE 1120
|
||||
#define EVERGREEN_PM4_UCODE_SIZE 1376
|
||||
#define EVERGREEN_RLC_UCODE_SIZE 768
|
||||
#define CAYMAN_RLC_UCODE_SIZE 1024
|
||||
|
||||
/* Firmware Names */
|
||||
MODULE_FIRMWARE("radeon/R600_pfp.bin");
|
||||
@ -2809,13 +2810,20 @@ static int r600_rlc_init(struct radeon_device *rdev)
|
||||
WREG32(RLC_HB_CNTL, 0);
|
||||
WREG32(RLC_HB_RPTR, 0);
|
||||
WREG32(RLC_HB_WPTR, 0);
|
||||
WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
|
||||
WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
|
||||
if (rdev->family <= CHIP_CAICOS) {
|
||||
WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
|
||||
WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
|
||||
}
|
||||
WREG32(RLC_MC_CNTL, 0);
|
||||
WREG32(RLC_UCODE_CNTL, 0);
|
||||
|
||||
fw_data = (const __be32 *)rdev->rlc_fw->data;
|
||||
if (rdev->family >= CHIP_CEDAR) {
|
||||
if (rdev->family >= CHIP_CAYMAN) {
|
||||
for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
|
||||
WREG32(RLC_UCODE_ADDR, i);
|
||||
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
|
||||
}
|
||||
} else if (rdev->family >= CHIP_CEDAR) {
|
||||
for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
|
||||
WREG32(RLC_UCODE_ADDR, i);
|
||||
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
|
||||
|
||||
@ -664,6 +664,8 @@ struct radeon_wb {
|
||||
|
||||
#define RADEON_WB_SCRATCH_OFFSET 0
|
||||
#define RADEON_WB_CP_RPTR_OFFSET 1024
|
||||
#define RADEON_WB_CP1_RPTR_OFFSET 1280
|
||||
#define RADEON_WB_CP2_RPTR_OFFSET 1536
|
||||
#define R600_WB_IH_WPTR_OFFSET 2048
|
||||
#define R600_WB_EVENT_OFFSET 3072
|
||||
|
||||
@ -1050,12 +1052,52 @@ struct evergreen_asic {
|
||||
struct r100_gpu_lockup lockup;
|
||||
};
|
||||
|
||||
struct cayman_asic {
|
||||
unsigned max_shader_engines;
|
||||
unsigned max_pipes_per_simd;
|
||||
unsigned max_tile_pipes;
|
||||
unsigned max_simds_per_se;
|
||||
unsigned max_backends_per_se;
|
||||
unsigned max_texture_channel_caches;
|
||||
unsigned max_gprs;
|
||||
unsigned max_threads;
|
||||
unsigned max_gs_threads;
|
||||
unsigned max_stack_entries;
|
||||
unsigned sx_num_of_sets;
|
||||
unsigned sx_max_export_size;
|
||||
unsigned sx_max_export_pos_size;
|
||||
unsigned sx_max_export_smx_size;
|
||||
unsigned max_hw_contexts;
|
||||
unsigned sq_num_cf_insts;
|
||||
unsigned sc_prim_fifo_size;
|
||||
unsigned sc_hiz_tile_fifo_size;
|
||||
unsigned sc_earlyz_tile_fifo_size;
|
||||
|
||||
unsigned num_shader_engines;
|
||||
unsigned num_shader_pipes_per_simd;
|
||||
unsigned num_tile_pipes;
|
||||
unsigned num_simds_per_se;
|
||||
unsigned num_backends_per_se;
|
||||
unsigned backend_disable_mask_per_asic;
|
||||
unsigned backend_map;
|
||||
unsigned num_texture_channel_caches;
|
||||
unsigned mem_max_burst_length_bytes;
|
||||
unsigned mem_row_size_in_kb;
|
||||
unsigned shader_engine_tile_size;
|
||||
unsigned num_gpus;
|
||||
unsigned multi_gpu_tile_size;
|
||||
|
||||
unsigned tile_config;
|
||||
struct r100_gpu_lockup lockup;
|
||||
};
|
||||
|
||||
union radeon_asic_config {
|
||||
struct r300_asic r300;
|
||||
struct r100_asic r100;
|
||||
struct r600_asic r600;
|
||||
struct rv770_asic rv770;
|
||||
struct evergreen_asic evergreen;
|
||||
struct cayman_asic cayman;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1146,6 +1188,9 @@ struct radeon_device {
|
||||
struct radeon_mman mman;
|
||||
struct radeon_fence_driver fence_drv;
|
||||
struct radeon_cp cp;
|
||||
/* cayman compute rings */
|
||||
struct radeon_cp cp1;
|
||||
struct radeon_cp cp2;
|
||||
struct radeon_ib_pool ib_pool;
|
||||
struct radeon_irq irq;
|
||||
struct radeon_asic *asic;
|
||||
@ -1456,7 +1501,7 @@ extern void r600_hdmi_disable(struct drm_encoder *encoder);
|
||||
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
|
||||
|
||||
extern int ni_init_microcode(struct radeon_device *rdev);
|
||||
extern int btc_mc_load_microcode(struct radeon_device *rdev);
|
||||
extern int ni_mc_load_microcode(struct radeon_device *rdev);
|
||||
|
||||
/* radeon_acpi.c */
|
||||
#if defined(CONFIG_ACPI)
|
||||
|
||||
@ -882,6 +882,52 @@ static struct radeon_asic btc_asic = {
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
};
|
||||
|
||||
static struct radeon_asic cayman_asic = {
|
||||
.init = &cayman_init,
|
||||
.fini = &cayman_fini,
|
||||
.suspend = &cayman_suspend,
|
||||
.resume = &cayman_resume,
|
||||
.cp_commit = &r600_cp_commit,
|
||||
.gpu_is_lockup = &cayman_gpu_is_lockup,
|
||||
.asic_reset = &cayman_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
|
||||
.gart_set_page = &rs600_gart_set_page,
|
||||
.ring_test = &r600_ring_test,
|
||||
.ring_ib_execute = &evergreen_ring_ib_execute,
|
||||
.irq_set = &evergreen_irq_set,
|
||||
.irq_process = &evergreen_irq_process,
|
||||
.get_vblank_counter = &evergreen_get_vblank_counter,
|
||||
.fence_ring_emit = &r600_fence_ring_emit,
|
||||
.cs_parse = &evergreen_cs_parse,
|
||||
.copy_blit = NULL,
|
||||
.copy_dma = NULL,
|
||||
.copy = NULL,
|
||||
.get_engine_clock = &radeon_atom_get_engine_clock,
|
||||
.set_engine_clock = &radeon_atom_set_engine_clock,
|
||||
.get_memory_clock = &radeon_atom_get_memory_clock,
|
||||
.set_memory_clock = &radeon_atom_set_memory_clock,
|
||||
.get_pcie_lanes = NULL,
|
||||
.set_pcie_lanes = NULL,
|
||||
.set_clock_gating = NULL,
|
||||
.set_surface_reg = r600_set_surface_reg,
|
||||
.clear_surface_reg = r600_clear_surface_reg,
|
||||
.bandwidth_update = &evergreen_bandwidth_update,
|
||||
.hpd_init = &evergreen_hpd_init,
|
||||
.hpd_fini = &evergreen_hpd_fini,
|
||||
.hpd_sense = &evergreen_hpd_sense,
|
||||
.hpd_set_polarity = &evergreen_hpd_set_polarity,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm_misc = &evergreen_pm_misc,
|
||||
.pm_prepare = &evergreen_pm_prepare,
|
||||
.pm_finish = &evergreen_pm_finish,
|
||||
.pm_init_profile = &r600_pm_init_profile,
|
||||
.pm_get_dynpm_state = &r600_pm_get_dynpm_state,
|
||||
.pre_page_flip = &evergreen_pre_page_flip,
|
||||
.page_flip = &evergreen_page_flip,
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
};
|
||||
|
||||
int radeon_asic_init(struct radeon_device *rdev)
|
||||
{
|
||||
radeon_register_accessor_init(rdev);
|
||||
@ -974,6 +1020,9 @@ int radeon_asic_init(struct radeon_device *rdev)
|
||||
case CHIP_CAICOS:
|
||||
rdev->asic = &btc_asic;
|
||||
break;
|
||||
case CHIP_CAYMAN:
|
||||
rdev->asic = &cayman_asic;
|
||||
break;
|
||||
default:
|
||||
/* FIXME: not supported yet */
|
||||
return -EINVAL;
|
||||
|
||||
@ -429,5 +429,15 @@ void evergreen_kms_blit_copy(struct radeon_device *rdev,
|
||||
u64 src_gpu_addr, u64 dst_gpu_addr,
|
||||
int size_bytes);
|
||||
|
||||
/*
|
||||
* cayman
|
||||
*/
|
||||
void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
||||
int cayman_init(struct radeon_device *rdev);
|
||||
void cayman_fini(struct radeon_device *rdev);
|
||||
int cayman_suspend(struct radeon_device *rdev);
|
||||
int cayman_resume(struct radeon_device *rdev);
|
||||
bool cayman_gpu_is_lockup(struct radeon_device *rdev);
|
||||
int cayman_asic_reset(struct radeon_device *rdev);
|
||||
|
||||
#endif
|
||||
|
||||
@ -85,6 +85,7 @@ static const char radeon_family_name[][16] = {
|
||||
"BARTS",
|
||||
"TURKS",
|
||||
"CAICOS",
|
||||
"CAYMAN",
|
||||
"LAST",
|
||||
};
|
||||
|
||||
|
||||
@ -84,6 +84,7 @@ enum radeon_family {
|
||||
CHIP_BARTS,
|
||||
CHIP_TURKS,
|
||||
CHIP_CAICOS,
|
||||
CHIP_CAYMAN,
|
||||
CHIP_LAST,
|
||||
};
|
||||
|
||||
|
||||
@ -169,7 +169,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
||||
value = rdev->accel_working;
|
||||
break;
|
||||
case RADEON_INFO_TILING_CONFIG:
|
||||
if (rdev->family >= CHIP_CEDAR)
|
||||
if (rdev->family >= CHIP_CAYMAN)
|
||||
value = rdev->config.cayman.tile_config;
|
||||
else if (rdev->family >= CHIP_CEDAR)
|
||||
value = rdev->config.evergreen.tile_config;
|
||||
else if (rdev->family >= CHIP_RV770)
|
||||
value = rdev->config.rv770.tile_config;
|
||||
@ -206,7 +208,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
||||
value = rdev->clock.spll.reference_freq * 10;
|
||||
break;
|
||||
case RADEON_INFO_NUM_BACKENDS:
|
||||
if (rdev->family >= CHIP_CEDAR)
|
||||
if (rdev->family >= CHIP_CAYMAN)
|
||||
value = rdev->config.cayman.max_backends_per_se *
|
||||
rdev->config.cayman.max_shader_engines;
|
||||
else if (rdev->family >= CHIP_CEDAR)
|
||||
value = rdev->config.evergreen.max_backends;
|
||||
else if (rdev->family >= CHIP_RV770)
|
||||
value = rdev->config.rv770.max_backends;
|
||||
|
||||
619
drivers/gpu/drm/radeon/reg_srcs/cayman
Normal file
619
drivers/gpu/drm/radeon/reg_srcs/cayman
Normal file
@ -0,0 +1,619 @@
|
||||
cayman 0x9400
|
||||
0x0000802C GRBM_GFX_INDEX
|
||||
0x000088B0 VGT_VTX_VECT_EJECT_REG
|
||||
0x000088C4 VGT_CACHE_INVALIDATION
|
||||
0x000088D4 VGT_GS_VERTEX_REUSE
|
||||
0x00008958 VGT_PRIMITIVE_TYPE
|
||||
0x0000895C VGT_INDEX_TYPE
|
||||
0x00008970 VGT_NUM_INDICES
|
||||
0x00008974 VGT_NUM_INSTANCES
|
||||
0x00008990 VGT_COMPUTE_DIM_X
|
||||
0x00008994 VGT_COMPUTE_DIM_Y
|
||||
0x00008998 VGT_COMPUTE_DIM_Z
|
||||
0x0000899C VGT_COMPUTE_START_X
|
||||
0x000089A0 VGT_COMPUTE_START_Y
|
||||
0x000089A4 VGT_COMPUTE_START_Z
|
||||
0x000089A8 VGT_COMPUTE_INDEX
|
||||
0x000089AC VGT_COMPUTE_THREAD_GOURP_SIZE
|
||||
0x000089B0 VGT_HS_OFFCHIP_PARAM
|
||||
0x00008A14 PA_CL_ENHANCE
|
||||
0x00008A60 PA_SC_LINE_STIPPLE_VALUE
|
||||
0x00008B10 PA_SC_LINE_STIPPLE_STATE
|
||||
0x00008BF0 PA_SC_ENHANCE
|
||||
0x00008D8C SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
|
||||
0x00008D94 SQ_DYN_GPR_SIMD_LOCK_EN
|
||||
0x00008C00 SQ_CONFIG
|
||||
0x00008C04 SQ_GPR_RESOURCE_MGMT_1
|
||||
0x00008C10 SQ_GLOBAL_GPR_RESOURCE_MGMT_1
|
||||
0x00008C14 SQ_GLOBAL_GPR_RESOURCE_MGMT_2
|
||||
0x00008DF8 SQ_CONST_MEM_BASE
|
||||
0x00008E20 SQ_STATIC_THREAD_MGMT_1
|
||||
0x00008E24 SQ_STATIC_THREAD_MGMT_2
|
||||
0x00008E28 SQ_STATIC_THREAD_MGMT_3
|
||||
0x00008E48 SQ_EX_ALLOC_TABLE_SLOTS
|
||||
0x00009100 SPI_CONFIG_CNTL
|
||||
0x0000913C SPI_CONFIG_CNTL_1
|
||||
0x00009830 DB_DEBUG
|
||||
0x00009834 DB_DEBUG2
|
||||
0x00009838 DB_DEBUG3
|
||||
0x0000983C DB_DEBUG4
|
||||
0x00009854 DB_WATERMARKS
|
||||
0x0000A400 TD_PS_BORDER_COLOR_INDEX
|
||||
0x0000A404 TD_PS_BORDER_COLOR_RED
|
||||
0x0000A408 TD_PS_BORDER_COLOR_GREEN
|
||||
0x0000A40C TD_PS_BORDER_COLOR_BLUE
|
||||
0x0000A410 TD_PS_BORDER_COLOR_ALPHA
|
||||
0x0000A414 TD_VS_BORDER_COLOR_INDEX
|
||||
0x0000A418 TD_VS_BORDER_COLOR_RED
|
||||
0x0000A41C TD_VS_BORDER_COLOR_GREEN
|
||||
0x0000A420 TD_VS_BORDER_COLOR_BLUE
|
||||
0x0000A424 TD_VS_BORDER_COLOR_ALPHA
|
||||
0x0000A428 TD_GS_BORDER_COLOR_INDEX
|
||||
0x0000A42C TD_GS_BORDER_COLOR_RED
|
||||
0x0000A430 TD_GS_BORDER_COLOR_GREEN
|
||||
0x0000A434 TD_GS_BORDER_COLOR_BLUE
|
||||
0x0000A438 TD_GS_BORDER_COLOR_ALPHA
|
||||
0x0000A43C TD_HS_BORDER_COLOR_INDEX
|
||||
0x0000A440 TD_HS_BORDER_COLOR_RED
|
||||
0x0000A444 TD_HS_BORDER_COLOR_GREEN
|
||||
0x0000A448 TD_HS_BORDER_COLOR_BLUE
|
||||
0x0000A44C TD_HS_BORDER_COLOR_ALPHA
|
||||
0x0000A450 TD_LS_BORDER_COLOR_INDEX
|
||||
0x0000A454 TD_LS_BORDER_COLOR_RED
|
||||
0x0000A458 TD_LS_BORDER_COLOR_GREEN
|
||||
0x0000A45C TD_LS_BORDER_COLOR_BLUE
|
||||
0x0000A460 TD_LS_BORDER_COLOR_ALPHA
|
||||
0x0000A464 TD_CS_BORDER_COLOR_INDEX
|
||||
0x0000A468 TD_CS_BORDER_COLOR_RED
|
||||
0x0000A46C TD_CS_BORDER_COLOR_GREEN
|
||||
0x0000A470 TD_CS_BORDER_COLOR_BLUE
|
||||
0x0000A474 TD_CS_BORDER_COLOR_ALPHA
|
||||
0x00028000 DB_RENDER_CONTROL
|
||||
0x00028004 DB_COUNT_CONTROL
|
||||
0x0002800C DB_RENDER_OVERRIDE
|
||||
0x00028010 DB_RENDER_OVERRIDE2
|
||||
0x00028028 DB_STENCIL_CLEAR
|
||||
0x0002802C DB_DEPTH_CLEAR
|
||||
0x00028030 PA_SC_SCREEN_SCISSOR_TL
|
||||
0x00028034 PA_SC_SCREEN_SCISSOR_BR
|
||||
0x0002805C DB_DEPTH_SLICE
|
||||
0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
|
||||
0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
|
||||
0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
|
||||
0x0002814C SQ_ALU_CONST_BUFFER_SIZE_PS_3
|
||||
0x00028150 SQ_ALU_CONST_BUFFER_SIZE_PS_4
|
||||
0x00028154 SQ_ALU_CONST_BUFFER_SIZE_PS_5
|
||||
0x00028158 SQ_ALU_CONST_BUFFER_SIZE_PS_6
|
||||
0x0002815C SQ_ALU_CONST_BUFFER_SIZE_PS_7
|
||||
0x00028160 SQ_ALU_CONST_BUFFER_SIZE_PS_8
|
||||
0x00028164 SQ_ALU_CONST_BUFFER_SIZE_PS_9
|
||||
0x00028168 SQ_ALU_CONST_BUFFER_SIZE_PS_10
|
||||
0x0002816C SQ_ALU_CONST_BUFFER_SIZE_PS_11
|
||||
0x00028170 SQ_ALU_CONST_BUFFER_SIZE_PS_12
|
||||
0x00028174 SQ_ALU_CONST_BUFFER_SIZE_PS_13
|
||||
0x00028178 SQ_ALU_CONST_BUFFER_SIZE_PS_14
|
||||
0x0002817C SQ_ALU_CONST_BUFFER_SIZE_PS_15
|
||||
0x00028180 SQ_ALU_CONST_BUFFER_SIZE_VS_0
|
||||
0x00028184 SQ_ALU_CONST_BUFFER_SIZE_VS_1
|
||||
0x00028188 SQ_ALU_CONST_BUFFER_SIZE_VS_2
|
||||
0x0002818C SQ_ALU_CONST_BUFFER_SIZE_VS_3
|
||||
0x00028190 SQ_ALU_CONST_BUFFER_SIZE_VS_4
|
||||
0x00028194 SQ_ALU_CONST_BUFFER_SIZE_VS_5
|
||||
0x00028198 SQ_ALU_CONST_BUFFER_SIZE_VS_6
|
||||
0x0002819C SQ_ALU_CONST_BUFFER_SIZE_VS_7
|
||||
0x000281A0 SQ_ALU_CONST_BUFFER_SIZE_VS_8
|
||||
0x000281A4 SQ_ALU_CONST_BUFFER_SIZE_VS_9
|
||||
0x000281A8 SQ_ALU_CONST_BUFFER_SIZE_VS_10
|
||||
0x000281AC SQ_ALU_CONST_BUFFER_SIZE_VS_11
|
||||
0x000281B0 SQ_ALU_CONST_BUFFER_SIZE_VS_12
|
||||
0x000281B4 SQ_ALU_CONST_BUFFER_SIZE_VS_13
|
||||
0x000281B8 SQ_ALU_CONST_BUFFER_SIZE_VS_14
|
||||
0x000281BC SQ_ALU_CONST_BUFFER_SIZE_VS_15
|
||||
0x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
|
||||
0x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
|
||||
0x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
|
||||
0x000281CC SQ_ALU_CONST_BUFFER_SIZE_GS_3
|
||||
0x000281D0 SQ_ALU_CONST_BUFFER_SIZE_GS_4
|
||||
0x000281D4 SQ_ALU_CONST_BUFFER_SIZE_GS_5
|
||||
0x000281D8 SQ_ALU_CONST_BUFFER_SIZE_GS_6
|
||||
0x000281DC SQ_ALU_CONST_BUFFER_SIZE_GS_7
|
||||
0x000281E0 SQ_ALU_CONST_BUFFER_SIZE_GS_8
|
||||
0x000281E4 SQ_ALU_CONST_BUFFER_SIZE_GS_9
|
||||
0x000281E8 SQ_ALU_CONST_BUFFER_SIZE_GS_10
|
||||
0x000281EC SQ_ALU_CONST_BUFFER_SIZE_GS_11
|
||||
0x000281F0 SQ_ALU_CONST_BUFFER_SIZE_GS_12
|
||||
0x000281F4 SQ_ALU_CONST_BUFFER_SIZE_GS_13
|
||||
0x000281F8 SQ_ALU_CONST_BUFFER_SIZE_GS_14
|
||||
0x000281FC SQ_ALU_CONST_BUFFER_SIZE_GS_15
|
||||
0x00028200 PA_SC_WINDOW_OFFSET
|
||||
0x00028204 PA_SC_WINDOW_SCISSOR_TL
|
||||
0x00028208 PA_SC_WINDOW_SCISSOR_BR
|
||||
0x0002820C PA_SC_CLIPRECT_RULE
|
||||
0x00028210 PA_SC_CLIPRECT_0_TL
|
||||
0x00028214 PA_SC_CLIPRECT_0_BR
|
||||
0x00028218 PA_SC_CLIPRECT_1_TL
|
||||
0x0002821C PA_SC_CLIPRECT_1_BR
|
||||
0x00028220 PA_SC_CLIPRECT_2_TL
|
||||
0x00028224 PA_SC_CLIPRECT_2_BR
|
||||
0x00028228 PA_SC_CLIPRECT_3_TL
|
||||
0x0002822C PA_SC_CLIPRECT_3_BR
|
||||
0x00028230 PA_SC_EDGERULE
|
||||
0x00028234 PA_SU_HARDWARE_SCREEN_OFFSET
|
||||
0x00028240 PA_SC_GENERIC_SCISSOR_TL
|
||||
0x00028244 PA_SC_GENERIC_SCISSOR_BR
|
||||
0x00028250 PA_SC_VPORT_SCISSOR_0_TL
|
||||
0x00028254 PA_SC_VPORT_SCISSOR_0_BR
|
||||
0x00028258 PA_SC_VPORT_SCISSOR_1_TL
|
||||
0x0002825C PA_SC_VPORT_SCISSOR_1_BR
|
||||
0x00028260 PA_SC_VPORT_SCISSOR_2_TL
|
||||
0x00028264 PA_SC_VPORT_SCISSOR_2_BR
|
||||
0x00028268 PA_SC_VPORT_SCISSOR_3_TL
|
||||
0x0002826C PA_SC_VPORT_SCISSOR_3_BR
|
||||
0x00028270 PA_SC_VPORT_SCISSOR_4_TL
|
||||
0x00028274 PA_SC_VPORT_SCISSOR_4_BR
|
||||
0x00028278 PA_SC_VPORT_SCISSOR_5_TL
|
||||
0x0002827C PA_SC_VPORT_SCISSOR_5_BR
|
||||
0x00028280 PA_SC_VPORT_SCISSOR_6_TL
|
||||
0x00028284 PA_SC_VPORT_SCISSOR_6_BR
|
||||
0x00028288 PA_SC_VPORT_SCISSOR_7_TL
|
||||
0x0002828C PA_SC_VPORT_SCISSOR_7_BR
|
||||
0x00028290 PA_SC_VPORT_SCISSOR_8_TL
|
||||
0x00028294 PA_SC_VPORT_SCISSOR_8_BR
|
||||
0x00028298 PA_SC_VPORT_SCISSOR_9_TL
|
||||
0x0002829C PA_SC_VPORT_SCISSOR_9_BR
|
||||
0x000282A0 PA_SC_VPORT_SCISSOR_10_TL
|
||||
0x000282A4 PA_SC_VPORT_SCISSOR_10_BR
|
||||
0x000282A8 PA_SC_VPORT_SCISSOR_11_TL
|
||||
0x000282AC PA_SC_VPORT_SCISSOR_11_BR
|
||||
0x000282B0 PA_SC_VPORT_SCISSOR_12_TL
|
||||
0x000282B4 PA_SC_VPORT_SCISSOR_12_BR
|
||||
0x000282B8 PA_SC_VPORT_SCISSOR_13_TL
|
||||
0x000282BC PA_SC_VPORT_SCISSOR_13_BR
|
||||
0x000282C0 PA_SC_VPORT_SCISSOR_14_TL
|
||||
0x000282C4 PA_SC_VPORT_SCISSOR_14_BR
|
||||
0x000282C8 PA_SC_VPORT_SCISSOR_15_TL
|
||||
0x000282CC PA_SC_VPORT_SCISSOR_15_BR
|
||||
0x000282D0 PA_SC_VPORT_ZMIN_0
|
||||
0x000282D4 PA_SC_VPORT_ZMAX_0
|
||||
0x000282D8 PA_SC_VPORT_ZMIN_1
|
||||
0x000282DC PA_SC_VPORT_ZMAX_1
|
||||
0x000282E0 PA_SC_VPORT_ZMIN_2
|
||||
0x000282E4 PA_SC_VPORT_ZMAX_2
|
||||
0x000282E8 PA_SC_VPORT_ZMIN_3
|
||||
0x000282EC PA_SC_VPORT_ZMAX_3
|
||||
0x000282F0 PA_SC_VPORT_ZMIN_4
|
||||
0x000282F4 PA_SC_VPORT_ZMAX_4
|
||||
0x000282F8 PA_SC_VPORT_ZMIN_5
|
||||
0x000282FC PA_SC_VPORT_ZMAX_5
|
||||
0x00028300 PA_SC_VPORT_ZMIN_6
|
||||
0x00028304 PA_SC_VPORT_ZMAX_6
|
||||
0x00028308 PA_SC_VPORT_ZMIN_7
|
||||
0x0002830C PA_SC_VPORT_ZMAX_7
|
||||
0x00028310 PA_SC_VPORT_ZMIN_8
|
||||
0x00028314 PA_SC_VPORT_ZMAX_8
|
||||
0x00028318 PA_SC_VPORT_ZMIN_9
|
||||
0x0002831C PA_SC_VPORT_ZMAX_9
|
||||
0x00028320 PA_SC_VPORT_ZMIN_10
|
||||
0x00028324 PA_SC_VPORT_ZMAX_10
|
||||
0x00028328 PA_SC_VPORT_ZMIN_11
|
||||
0x0002832C PA_SC_VPORT_ZMAX_11
|
||||
0x00028330 PA_SC_VPORT_ZMIN_12
|
||||
0x00028334 PA_SC_VPORT_ZMAX_12
|
||||
0x00028338 PA_SC_VPORT_ZMIN_13
|
||||
0x0002833C PA_SC_VPORT_ZMAX_13
|
||||
0x00028340 PA_SC_VPORT_ZMIN_14
|
||||
0x00028344 PA_SC_VPORT_ZMAX_14
|
||||
0x00028348 PA_SC_VPORT_ZMIN_15
|
||||
0x0002834C PA_SC_VPORT_ZMAX_15
|
||||
0x00028350 SX_MISC
|
||||
0x00028354 SX_SURFACE_SYNC
|
||||
0x00028380 SQ_VTX_SEMANTIC_0
|
||||
0x00028384 SQ_VTX_SEMANTIC_1
|
||||
0x00028388 SQ_VTX_SEMANTIC_2
|
||||
0x0002838C SQ_VTX_SEMANTIC_3
|
||||
0x00028390 SQ_VTX_SEMANTIC_4
|
||||
0x00028394 SQ_VTX_SEMANTIC_5
|
||||
0x00028398 SQ_VTX_SEMANTIC_6
|
||||
0x0002839C SQ_VTX_SEMANTIC_7
|
||||
0x000283A0 SQ_VTX_SEMANTIC_8
|
||||
0x000283A4 SQ_VTX_SEMANTIC_9
|
||||
0x000283A8 SQ_VTX_SEMANTIC_10
|
||||
0x000283AC SQ_VTX_SEMANTIC_11
|
||||
0x000283B0 SQ_VTX_SEMANTIC_12
|
||||
0x000283B4 SQ_VTX_SEMANTIC_13
|
||||
0x000283B8 SQ_VTX_SEMANTIC_14
|
||||
0x000283BC SQ_VTX_SEMANTIC_15
|
||||
0x000283C0 SQ_VTX_SEMANTIC_16
|
||||
0x000283C4 SQ_VTX_SEMANTIC_17
|
||||
0x000283C8 SQ_VTX_SEMANTIC_18
|
||||
0x000283CC SQ_VTX_SEMANTIC_19
|
||||
0x000283D0 SQ_VTX_SEMANTIC_20
|
||||
0x000283D4 SQ_VTX_SEMANTIC_21
|
||||
0x000283D8 SQ_VTX_SEMANTIC_22
|
||||
0x000283DC SQ_VTX_SEMANTIC_23
|
||||
0x000283E0 SQ_VTX_SEMANTIC_24
|
||||
0x000283E4 SQ_VTX_SEMANTIC_25
|
||||
0x000283E8 SQ_VTX_SEMANTIC_26
|
||||
0x000283EC SQ_VTX_SEMANTIC_27
|
||||
0x000283F0 SQ_VTX_SEMANTIC_28
|
||||
0x000283F4 SQ_VTX_SEMANTIC_29
|
||||
0x000283F8 SQ_VTX_SEMANTIC_30
|
||||
0x000283FC SQ_VTX_SEMANTIC_31
|
||||
0x00028400 VGT_MAX_VTX_INDX
|
||||
0x00028404 VGT_MIN_VTX_INDX
|
||||
0x00028408 VGT_INDX_OFFSET
|
||||
0x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
|
||||
0x00028410 SX_ALPHA_TEST_CONTROL
|
||||
0x00028414 CB_BLEND_RED
|
||||
0x00028418 CB_BLEND_GREEN
|
||||
0x0002841C CB_BLEND_BLUE
|
||||
0x00028420 CB_BLEND_ALPHA
|
||||
0x00028430 DB_STENCILREFMASK
|
||||
0x00028434 DB_STENCILREFMASK_BF
|
||||
0x00028438 SX_ALPHA_REF
|
||||
0x0002843C PA_CL_VPORT_XSCALE_0
|
||||
0x00028440 PA_CL_VPORT_XOFFSET_0
|
||||
0x00028444 PA_CL_VPORT_YSCALE_0
|
||||
0x00028448 PA_CL_VPORT_YOFFSET_0
|
||||
0x0002844C PA_CL_VPORT_ZSCALE_0
|
||||
0x00028450 PA_CL_VPORT_ZOFFSET_0
|
||||
0x00028454 PA_CL_VPORT_XSCALE_1
|
||||
0x00028458 PA_CL_VPORT_XOFFSET_1
|
||||
0x0002845C PA_CL_VPORT_YSCALE_1
|
||||
0x00028460 PA_CL_VPORT_YOFFSET_1
|
||||
0x00028464 PA_CL_VPORT_ZSCALE_1
|
||||
0x00028468 PA_CL_VPORT_ZOFFSET_1
|
||||
0x0002846C PA_CL_VPORT_XSCALE_2
|
||||
0x00028470 PA_CL_VPORT_XOFFSET_2
|
||||
0x00028474 PA_CL_VPORT_YSCALE_2
|
||||
0x00028478 PA_CL_VPORT_YOFFSET_2
|
||||
0x0002847C PA_CL_VPORT_ZSCALE_2
|
||||
0x00028480 PA_CL_VPORT_ZOFFSET_2
|
||||
0x00028484 PA_CL_VPORT_XSCALE_3
|
||||
0x00028488 PA_CL_VPORT_XOFFSET_3
|
||||
0x0002848C PA_CL_VPORT_YSCALE_3
|
||||
0x00028490 PA_CL_VPORT_YOFFSET_3
|
||||
0x00028494 PA_CL_VPORT_ZSCALE_3
|
||||
0x00028498 PA_CL_VPORT_ZOFFSET_3
|
||||
0x0002849C PA_CL_VPORT_XSCALE_4
|
||||
0x000284A0 PA_CL_VPORT_XOFFSET_4
|
||||
0x000284A4 PA_CL_VPORT_YSCALE_4
|
||||
0x000284A8 PA_CL_VPORT_YOFFSET_4
|
||||
0x000284AC PA_CL_VPORT_ZSCALE_4
|
||||
0x000284B0 PA_CL_VPORT_ZOFFSET_4
|
||||
0x000284B4 PA_CL_VPORT_XSCALE_5
|
||||
0x000284B8 PA_CL_VPORT_XOFFSET_5
|
||||
0x000284BC PA_CL_VPORT_YSCALE_5
|
||||
0x000284C0 PA_CL_VPORT_YOFFSET_5
|
||||
0x000284C4 PA_CL_VPORT_ZSCALE_5
|
||||
0x000284C8 PA_CL_VPORT_ZOFFSET_5
|
||||
0x000284CC PA_CL_VPORT_XSCALE_6
|
||||
0x000284D0 PA_CL_VPORT_XOFFSET_6
|
||||
0x000284D4 PA_CL_VPORT_YSCALE_6
|
||||
0x000284D8 PA_CL_VPORT_YOFFSET_6
|
||||
0x000284DC PA_CL_VPORT_ZSCALE_6
|
||||
0x000284E0 PA_CL_VPORT_ZOFFSET_6
|
||||
0x000284E4 PA_CL_VPORT_XSCALE_7
|
||||
0x000284E8 PA_CL_VPORT_XOFFSET_7
|
||||
0x000284EC PA_CL_VPORT_YSCALE_7
|
||||
0x000284F0 PA_CL_VPORT_YOFFSET_7
|
||||
0x000284F4 PA_CL_VPORT_ZSCALE_7
|
||||
0x000284F8 PA_CL_VPORT_ZOFFSET_7
|
||||
0x000284FC PA_CL_VPORT_XSCALE_8
|
||||
0x00028500 PA_CL_VPORT_XOFFSET_8
|
||||
0x00028504 PA_CL_VPORT_YSCALE_8
|
||||
0x00028508 PA_CL_VPORT_YOFFSET_8
|
||||
0x0002850C PA_CL_VPORT_ZSCALE_8
|
||||
0x00028510 PA_CL_VPORT_ZOFFSET_8
|
||||
0x00028514 PA_CL_VPORT_XSCALE_9
|
||||
0x00028518 PA_CL_VPORT_XOFFSET_9
|
||||
0x0002851C PA_CL_VPORT_YSCALE_9
|
||||
0x00028520 PA_CL_VPORT_YOFFSET_9
|
||||
0x00028524 PA_CL_VPORT_ZSCALE_9
|
||||
0x00028528 PA_CL_VPORT_ZOFFSET_9
|
||||
0x0002852C PA_CL_VPORT_XSCALE_10
|
||||
0x00028530 PA_CL_VPORT_XOFFSET_10
|
||||
0x00028534 PA_CL_VPORT_YSCALE_10
|
||||
0x00028538 PA_CL_VPORT_YOFFSET_10
|
||||
0x0002853C PA_CL_VPORT_ZSCALE_10
|
||||
0x00028540 PA_CL_VPORT_ZOFFSET_10
|
||||
0x00028544 PA_CL_VPORT_XSCALE_11
|
||||
0x00028548 PA_CL_VPORT_XOFFSET_11
|
||||
0x0002854C PA_CL_VPORT_YSCALE_11
|
||||
0x00028550 PA_CL_VPORT_YOFFSET_11
|
||||
0x00028554 PA_CL_VPORT_ZSCALE_11
|
||||
0x00028558 PA_CL_VPORT_ZOFFSET_11
|
||||
0x0002855C PA_CL_VPORT_XSCALE_12
|
||||
0x00028560 PA_CL_VPORT_XOFFSET_12
|
||||
0x00028564 PA_CL_VPORT_YSCALE_12
|
||||
0x00028568 PA_CL_VPORT_YOFFSET_12
|
||||
0x0002856C PA_CL_VPORT_ZSCALE_12
|
||||
0x00028570 PA_CL_VPORT_ZOFFSET_12
|
||||
0x00028574 PA_CL_VPORT_XSCALE_13
|
||||
0x00028578 PA_CL_VPORT_XOFFSET_13
|
||||
0x0002857C PA_CL_VPORT_YSCALE_13
|
||||
0x00028580 PA_CL_VPORT_YOFFSET_13
|
||||
0x00028584 PA_CL_VPORT_ZSCALE_13
|
||||
0x00028588 PA_CL_VPORT_ZOFFSET_13
|
||||
0x0002858C PA_CL_VPORT_XSCALE_14
|
||||
0x00028590 PA_CL_VPORT_XOFFSET_14
|
||||
0x00028594 PA_CL_VPORT_YSCALE_14
|
||||
0x00028598 PA_CL_VPORT_YOFFSET_14
|
||||
0x0002859C PA_CL_VPORT_ZSCALE_14
|
||||
0x000285A0 PA_CL_VPORT_ZOFFSET_14
|
||||
0x000285A4 PA_CL_VPORT_XSCALE_15
|
||||
0x000285A8 PA_CL_VPORT_XOFFSET_15
|
||||
0x000285AC PA_CL_VPORT_YSCALE_15
|
||||
0x000285B0 PA_CL_VPORT_YOFFSET_15
|
||||
0x000285B4 PA_CL_VPORT_ZSCALE_15
|
||||
0x000285B8 PA_CL_VPORT_ZOFFSET_15
|
||||
0x000285BC PA_CL_UCP_0_X
|
||||
0x000285C0 PA_CL_UCP_0_Y
|
||||
0x000285C4 PA_CL_UCP_0_Z
|
||||
0x000285C8 PA_CL_UCP_0_W
|
||||
0x000285CC PA_CL_UCP_1_X
|
||||
0x000285D0 PA_CL_UCP_1_Y
|
||||
0x000285D4 PA_CL_UCP_1_Z
|
||||
0x000285D8 PA_CL_UCP_1_W
|
||||
0x000285DC PA_CL_UCP_2_X
|
||||
0x000285E0 PA_CL_UCP_2_Y
|
||||
0x000285E4 PA_CL_UCP_2_Z
|
||||
0x000285E8 PA_CL_UCP_2_W
|
||||
0x000285EC PA_CL_UCP_3_X
|
||||
0x000285F0 PA_CL_UCP_3_Y
|
||||
0x000285F4 PA_CL_UCP_3_Z
|
||||
0x000285F8 PA_CL_UCP_3_W
|
||||
0x000285FC PA_CL_UCP_4_X
|
||||
0x00028600 PA_CL_UCP_4_Y
|
||||
0x00028604 PA_CL_UCP_4_Z
|
||||
0x00028608 PA_CL_UCP_4_W
|
||||
0x0002860C PA_CL_UCP_5_X
|
||||
0x00028610 PA_CL_UCP_5_Y
|
||||
0x00028614 PA_CL_UCP_5_Z
|
||||
0x00028618 PA_CL_UCP_5_W
|
||||
0x0002861C SPI_VS_OUT_ID_0
|
||||
0x00028620 SPI_VS_OUT_ID_1
|
||||
0x00028624 SPI_VS_OUT_ID_2
|
||||
0x00028628 SPI_VS_OUT_ID_3
|
||||
0x0002862C SPI_VS_OUT_ID_4
|
||||
0x00028630 SPI_VS_OUT_ID_5
|
||||
0x00028634 SPI_VS_OUT_ID_6
|
||||
0x00028638 SPI_VS_OUT_ID_7
|
||||
0x0002863C SPI_VS_OUT_ID_8
|
||||
0x00028640 SPI_VS_OUT_ID_9
|
||||
0x00028644 SPI_PS_INPUT_CNTL_0
|
||||
0x00028648 SPI_PS_INPUT_CNTL_1
|
||||
0x0002864C SPI_PS_INPUT_CNTL_2
|
||||
0x00028650 SPI_PS_INPUT_CNTL_3
|
||||
0x00028654 SPI_PS_INPUT_CNTL_4
|
||||
0x00028658 SPI_PS_INPUT_CNTL_5
|
||||
0x0002865C SPI_PS_INPUT_CNTL_6
|
||||
0x00028660 SPI_PS_INPUT_CNTL_7
|
||||
0x00028664 SPI_PS_INPUT_CNTL_8
|
||||
0x00028668 SPI_PS_INPUT_CNTL_9
|
||||
0x0002866C SPI_PS_INPUT_CNTL_10
|
||||
0x00028670 SPI_PS_INPUT_CNTL_11
|
||||
0x00028674 SPI_PS_INPUT_CNTL_12
|
||||
0x00028678 SPI_PS_INPUT_CNTL_13
|
||||
0x0002867C SPI_PS_INPUT_CNTL_14
|
||||
0x00028680 SPI_PS_INPUT_CNTL_15
|
||||
0x00028684 SPI_PS_INPUT_CNTL_16
|
||||
0x00028688 SPI_PS_INPUT_CNTL_17
|
||||
0x0002868C SPI_PS_INPUT_CNTL_18
|
||||
0x00028690 SPI_PS_INPUT_CNTL_19
|
||||
0x00028694 SPI_PS_INPUT_CNTL_20
|
||||
0x00028698 SPI_PS_INPUT_CNTL_21
|
||||
0x0002869C SPI_PS_INPUT_CNTL_22
|
||||
0x000286A0 SPI_PS_INPUT_CNTL_23
|
||||
0x000286A4 SPI_PS_INPUT_CNTL_24
|
||||
0x000286A8 SPI_PS_INPUT_CNTL_25
|
||||
0x000286AC SPI_PS_INPUT_CNTL_26
|
||||
0x000286B0 SPI_PS_INPUT_CNTL_27
|
||||
0x000286B4 SPI_PS_INPUT_CNTL_28
|
||||
0x000286B8 SPI_PS_INPUT_CNTL_29
|
||||
0x000286BC SPI_PS_INPUT_CNTL_30
|
||||
0x000286C0 SPI_PS_INPUT_CNTL_31
|
||||
0x000286C4 SPI_VS_OUT_CONFIG
|
||||
0x000286C8 SPI_THREAD_GROUPING
|
||||
0x000286CC SPI_PS_IN_CONTROL_0
|
||||
0x000286D0 SPI_PS_IN_CONTROL_1
|
||||
0x000286D4 SPI_INTERP_CONTROL_0
|
||||
0x000286D8 SPI_INPUT_Z
|
||||
0x000286DC SPI_FOG_CNTL
|
||||
0x000286E0 SPI_BARYC_CNTL
|
||||
0x000286E4 SPI_PS_IN_CONTROL_2
|
||||
0x000286E8 SPI_COMPUTE_INPUT_CNTL
|
||||
0x000286EC SPI_COMPUTE_NUM_THREAD_X
|
||||
0x000286F0 SPI_COMPUTE_NUM_THREAD_Y
|
||||
0x000286F4 SPI_COMPUTE_NUM_THREAD_Z
|
||||
0x000286F8 SPI_GPR_MGMT
|
||||
0x000286FC SPI_LDS_MGMT
|
||||
0x00028700 SPI_STACK_MGMT
|
||||
0x00028704 SPI_WAVE_MGMT_1
|
||||
0x00028708 SPI_WAVE_MGMT_2
|
||||
0x00028724 GDS_ADDR_SIZE
|
||||
0x00028780 CB_BLEND0_CONTROL
|
||||
0x00028784 CB_BLEND1_CONTROL
|
||||
0x00028788 CB_BLEND2_CONTROL
|
||||
0x0002878C CB_BLEND3_CONTROL
|
||||
0x00028790 CB_BLEND4_CONTROL
|
||||
0x00028794 CB_BLEND5_CONTROL
|
||||
0x00028798 CB_BLEND6_CONTROL
|
||||
0x0002879C CB_BLEND7_CONTROL
|
||||
0x000287CC CS_COPY_STATE
|
||||
0x000287D0 GFX_COPY_STATE
|
||||
0x000287D4 PA_CL_POINT_X_RAD
|
||||
0x000287D8 PA_CL_POINT_Y_RAD
|
||||
0x000287DC PA_CL_POINT_SIZE
|
||||
0x000287E0 PA_CL_POINT_CULL_RAD
|
||||
0x00028808 CB_COLOR_CONTROL
|
||||
0x0002880C DB_SHADER_CONTROL
|
||||
0x00028810 PA_CL_CLIP_CNTL
|
||||
0x00028814 PA_SU_SC_MODE_CNTL
|
||||
0x00028818 PA_CL_VTE_CNTL
|
||||
0x0002881C PA_CL_VS_OUT_CNTL
|
||||
0x00028820 PA_CL_NANINF_CNTL
|
||||
0x00028824 PA_SU_LINE_STIPPLE_CNTL
|
||||
0x00028828 PA_SU_LINE_STIPPLE_SCALE
|
||||
0x0002882C PA_SU_PRIM_FILTER_CNTL
|
||||
0x00028844 SQ_PGM_RESOURCES_PS
|
||||
0x00028848 SQ_PGM_RESOURCES_2_PS
|
||||
0x0002884C SQ_PGM_EXPORTS_PS
|
||||
0x00028860 SQ_PGM_RESOURCES_VS
|
||||
0x00028864 SQ_PGM_RESOURCES_2_VS
|
||||
0x00028878 SQ_PGM_RESOURCES_GS
|
||||
0x0002887C SQ_PGM_RESOURCES_2_GS
|
||||
0x00028890 SQ_PGM_RESOURCES_ES
|
||||
0x00028894 SQ_PGM_RESOURCES_2_ES
|
||||
0x000288A8 SQ_PGM_RESOURCES_FS
|
||||
0x000288BC SQ_PGM_RESOURCES_HS
|
||||
0x000288C0 SQ_PGM_RESOURCES_2_HS
|
||||
0x000288D4 SQ_PGM_RESOURCES_LS
|
||||
0x000288D8 SQ_PGM_RESOURCES_2_LS
|
||||
0x000288E8 SQ_LDS_ALLOC
|
||||
0x000288EC SQ_LDS_ALLOC_PS
|
||||
0x000288F0 SQ_VTX_SEMANTIC_CLEAR
|
||||
0x00028A00 PA_SU_POINT_SIZE
|
||||
0x00028A04 PA_SU_POINT_MINMAX
|
||||
0x00028A08 PA_SU_LINE_CNTL
|
||||
0x00028A0C PA_SC_LINE_STIPPLE
|
||||
0x00028A10 VGT_OUTPUT_PATH_CNTL
|
||||
0x00028A14 VGT_HOS_CNTL
|
||||
0x00028A18 VGT_HOS_MAX_TESS_LEVEL
|
||||
0x00028A1C VGT_HOS_MIN_TESS_LEVEL
|
||||
0x00028A20 VGT_HOS_REUSE_DEPTH
|
||||
0x00028A24 VGT_GROUP_PRIM_TYPE
|
||||
0x00028A28 VGT_GROUP_FIRST_DECR
|
||||
0x00028A2C VGT_GROUP_DECR
|
||||
0x00028A30 VGT_GROUP_VECT_0_CNTL
|
||||
0x00028A34 VGT_GROUP_VECT_1_CNTL
|
||||
0x00028A38 VGT_GROUP_VECT_0_FMT_CNTL
|
||||
0x00028A3C VGT_GROUP_VECT_1_FMT_CNTL
|
||||
0x00028A40 VGT_GS_MODE
|
||||
0x00028A48 PA_SC_MODE_CNTL_0
|
||||
0x00028A4C PA_SC_MODE_CNTL_1
|
||||
0x00028A50 VGT_ENHANCE
|
||||
0x00028A54 VGT_GS_PER_ES
|
||||
0x00028A58 VGT_ES_PER_GS
|
||||
0x00028A5C VGT_GS_PER_VS
|
||||
0x00028A6C VGT_GS_OUT_PRIM_TYPE
|
||||
0x00028A70 IA_ENHANCE
|
||||
0x00028A84 VGT_PRIMITIVEID_EN
|
||||
0x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
|
||||
0x00028AA0 VGT_INSTANCE_STEP_RATE_0
|
||||
0x00028AA4 VGT_INSTANCE_STEP_RATE_1
|
||||
0x00028AA8 IA_MULTI_VGT_PARAM
|
||||
0x00028AB4 VGT_REUSE_OFF
|
||||
0x00028AB8 VGT_VTX_CNT_EN
|
||||
0x00028ABC DB_HTILE_SURFACE
|
||||
0x00028AC0 DB_SRESULTS_COMPARE_STATE0
|
||||
0x00028AC4 DB_SRESULTS_COMPARE_STATE1
|
||||
0x00028AC8 DB_PRELOAD_CONTROL
|
||||
0x00028B38 VGT_GS_MAX_VERT_OUT
|
||||
0x00028B54 VGT_SHADER_STAGES_EN
|
||||
0x00028B58 VGT_LS_HS_CONFIG
|
||||
0x00028B6C VGT_TF_PARAM
|
||||
0x00028B70 DB_ALPHA_TO_MASK
|
||||
0x00028B74 VGT_DISPATCH_INITIATOR
|
||||
0x00028B78 PA_SU_POLY_OFFSET_DB_FMT_CNTL
|
||||
0x00028B7C PA_SU_POLY_OFFSET_CLAMP
|
||||
0x00028B80 PA_SU_POLY_OFFSET_FRONT_SCALE
|
||||
0x00028B84 PA_SU_POLY_OFFSET_FRONT_OFFSET
|
||||
0x00028B88 PA_SU_POLY_OFFSET_BACK_SCALE
|
||||
0x00028B8C PA_SU_POLY_OFFSET_BACK_OFFSET
|
||||
0x00028B74 VGT_GS_INSTANCE_CNT
|
||||
0x00028BD4 PA_SC_CENTROID_PRIORITY_0
|
||||
0x00028BD8 PA_SC_CENTROID_PRIORITY_1
|
||||
0x00028BDC PA_SC_LINE_CNTL
|
||||
0x00028BE4 PA_SU_VTX_CNTL
|
||||
0x00028BE8 PA_CL_GB_VERT_CLIP_ADJ
|
||||
0x00028BEC PA_CL_GB_VERT_DISC_ADJ
|
||||
0x00028BF0 PA_CL_GB_HORZ_CLIP_ADJ
|
||||
0x00028BF4 PA_CL_GB_HORZ_DISC_ADJ
|
||||
0x00028BF8 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_0
|
||||
0x00028BFC PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_1
|
||||
0x00028C00 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_2
|
||||
0x00028C04 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y0_3
|
||||
0x00028C08 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_0
|
||||
0x00028C0C PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_1
|
||||
0x00028C10 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_2
|
||||
0x00028C14 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y0_3
|
||||
0x00028C18 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_0
|
||||
0x00028C1C PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_1
|
||||
0x00028C20 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_2
|
||||
0x00028C24 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0_Y1_3
|
||||
0x00028C28 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_0
|
||||
0x00028C2C PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_1
|
||||
0x00028C30 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_2
|
||||
0x00028C34 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_3
|
||||
0x00028C38 PA_SC_AA_MASK_X0_Y0_X1_Y0
|
||||
0x00028C3C PA_SC_AA_MASK_X0_Y1_X1_Y1
|
||||
0x00028C8C CB_COLOR0_CLEAR_WORD0
|
||||
0x00028C90 CB_COLOR0_CLEAR_WORD1
|
||||
0x00028C94 CB_COLOR0_CLEAR_WORD2
|
||||
0x00028C98 CB_COLOR0_CLEAR_WORD3
|
||||
0x00028CC8 CB_COLOR1_CLEAR_WORD0
|
||||
0x00028CCC CB_COLOR1_CLEAR_WORD1
|
||||
0x00028CD0 CB_COLOR1_CLEAR_WORD2
|
||||
0x00028CD4 CB_COLOR1_CLEAR_WORD3
|
||||
0x00028D04 CB_COLOR2_CLEAR_WORD0
|
||||
0x00028D08 CB_COLOR2_CLEAR_WORD1
|
||||
0x00028D0C CB_COLOR2_CLEAR_WORD2
|
||||
0x00028D10 CB_COLOR2_CLEAR_WORD3
|
||||
0x00028D40 CB_COLOR3_CLEAR_WORD0
|
||||
0x00028D44 CB_COLOR3_CLEAR_WORD1
|
||||
0x00028D48 CB_COLOR3_CLEAR_WORD2
|
||||
0x00028D4C CB_COLOR3_CLEAR_WORD3
|
||||
0x00028D7C CB_COLOR4_CLEAR_WORD0
|
||||
0x00028D80 CB_COLOR4_CLEAR_WORD1
|
||||
0x00028D84 CB_COLOR4_CLEAR_WORD2
|
||||
0x00028D88 CB_COLOR4_CLEAR_WORD3
|
||||
0x00028DB8 CB_COLOR5_CLEAR_WORD0
|
||||
0x00028DBC CB_COLOR5_CLEAR_WORD1
|
||||
0x00028DC0 CB_COLOR5_CLEAR_WORD2
|
||||
0x00028DC4 CB_COLOR5_CLEAR_WORD3
|
||||
0x00028DF4 CB_COLOR6_CLEAR_WORD0
|
||||
0x00028DF8 CB_COLOR6_CLEAR_WORD1
|
||||
0x00028DFC CB_COLOR6_CLEAR_WORD2
|
||||
0x00028E00 CB_COLOR6_CLEAR_WORD3
|
||||
0x00028E30 CB_COLOR7_CLEAR_WORD0
|
||||
0x00028E34 CB_COLOR7_CLEAR_WORD1
|
||||
0x00028E38 CB_COLOR7_CLEAR_WORD2
|
||||
0x00028E3C CB_COLOR7_CLEAR_WORD3
|
||||
0x00028F80 SQ_ALU_CONST_BUFFER_SIZE_HS_0
|
||||
0x00028F84 SQ_ALU_CONST_BUFFER_SIZE_HS_1
|
||||
0x00028F88 SQ_ALU_CONST_BUFFER_SIZE_HS_2
|
||||
0x00028F8C SQ_ALU_CONST_BUFFER_SIZE_HS_3
|
||||
0x00028F90 SQ_ALU_CONST_BUFFER_SIZE_HS_4
|
||||
0x00028F94 SQ_ALU_CONST_BUFFER_SIZE_HS_5
|
||||
0x00028F98 SQ_ALU_CONST_BUFFER_SIZE_HS_6
|
||||
0x00028F9C SQ_ALU_CONST_BUFFER_SIZE_HS_7
|
||||
0x00028FA0 SQ_ALU_CONST_BUFFER_SIZE_HS_8
|
||||
0x00028FA4 SQ_ALU_CONST_BUFFER_SIZE_HS_9
|
||||
0x00028FA8 SQ_ALU_CONST_BUFFER_SIZE_HS_10
|
||||
0x00028FAC SQ_ALU_CONST_BUFFER_SIZE_HS_11
|
||||
0x00028FB0 SQ_ALU_CONST_BUFFER_SIZE_HS_12
|
||||
0x00028FB4 SQ_ALU_CONST_BUFFER_SIZE_HS_13
|
||||
0x00028FB8 SQ_ALU_CONST_BUFFER_SIZE_HS_14
|
||||
0x00028FBC SQ_ALU_CONST_BUFFER_SIZE_HS_15
|
||||
0x00028FC0 SQ_ALU_CONST_BUFFER_SIZE_LS_0
|
||||
0x00028FC4 SQ_ALU_CONST_BUFFER_SIZE_LS_1
|
||||
0x00028FC8 SQ_ALU_CONST_BUFFER_SIZE_LS_2
|
||||
0x00028FCC SQ_ALU_CONST_BUFFER_SIZE_LS_3
|
||||
0x00028FD0 SQ_ALU_CONST_BUFFER_SIZE_LS_4
|
||||
0x00028FD4 SQ_ALU_CONST_BUFFER_SIZE_LS_5
|
||||
0x00028FD8 SQ_ALU_CONST_BUFFER_SIZE_LS_6
|
||||
0x00028FDC SQ_ALU_CONST_BUFFER_SIZE_LS_7
|
||||
0x00028FE0 SQ_ALU_CONST_BUFFER_SIZE_LS_8
|
||||
0x00028FE4 SQ_ALU_CONST_BUFFER_SIZE_LS_9
|
||||
0x00028FE8 SQ_ALU_CONST_BUFFER_SIZE_LS_10
|
||||
0x00028FEC SQ_ALU_CONST_BUFFER_SIZE_LS_11
|
||||
0x00028FF0 SQ_ALU_CONST_BUFFER_SIZE_LS_12
|
||||
0x00028FF4 SQ_ALU_CONST_BUFFER_SIZE_LS_13
|
||||
0x00028FF8 SQ_ALU_CONST_BUFFER_SIZE_LS_14
|
||||
0x00028FFC SQ_ALU_CONST_BUFFER_SIZE_LS_15
|
||||
0x0003CFF0 SQ_VTX_BASE_VTX_LOC
|
||||
0x0003CFF4 SQ_VTX_START_INST_LOC
|
||||
0x0003FF00 SQ_TEX_SAMPLER_CLEAR
|
||||
0x0003FF04 SQ_TEX_RESOURCE_CLEAR
|
||||
0x0003FF08 SQ_LOOP_BOOL_CLEAR
|
||||
@ -1,4 +1,5 @@
|
||||
evergreen 0x9400
|
||||
0x0000802C GRBM_GFX_INDEX
|
||||
0x00008040 WAIT_UNTIL
|
||||
0x00008044 WAIT_UNTIL_POLL_CNTL
|
||||
0x00008048 WAIT_UNTIL_POLL_MASK
|
||||
@ -220,6 +221,7 @@ evergreen 0x9400
|
||||
0x00028348 PA_SC_VPORT_ZMIN_15
|
||||
0x0002834C PA_SC_VPORT_ZMAX_15
|
||||
0x00028350 SX_MISC
|
||||
0x00028354 SX_SURFACE_SYNC
|
||||
0x00028380 SQ_VTX_SEMANTIC_0
|
||||
0x00028384 SQ_VTX_SEMANTIC_1
|
||||
0x00028388 SQ_VTX_SEMANTIC_2
|
||||
|
||||
@ -141,6 +141,20 @@
|
||||
{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6703, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6704, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6705, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6706, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6707, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6708, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6709, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6718, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6719, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x671c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x671d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user