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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cxgb4 : Improve IEEE DCBx support, other minor open-lldp fixes
* Add support for IEEE ets & pfc api. * Fix bug that resulted in incorrect bandwidth percentage being returned for CEE peers * Convert pfc enabled info from firmware format to what dcbnl expects before returning Signed-off-by: Anish Bhatt <anish@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -428,7 +428,10 @@ static void cxgb4_getpgtccfg(struct net_device *dev, int tc,
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}
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*pgid = (be32_to_cpu(pcmd.u.dcb.pgid.pgid) >> (tc * 4)) & 0xf;
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INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
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if (local)
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INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
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else
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INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
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pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
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err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
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if (err != FW_PORT_DCB_CFG_SUCCESS) {
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@ -900,6 +903,88 @@ cxgb4_ieee_negotiation_complete(struct net_device *dev,
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(dcb->supported & DCB_CAP_DCBX_VER_IEEE));
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}
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static int cxgb4_ieee_read_ets(struct net_device *dev, struct ieee_ets *ets,
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int local)
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{
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struct port_info *pi = netdev2pinfo(dev);
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struct port_dcb_info *dcb = &pi->dcb;
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struct adapter *adap = pi->adapter;
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uint32_t tc_info;
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struct fw_port_cmd pcmd;
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int i, bwg, err;
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if (!(dcb->msgs & (CXGB4_DCB_FW_PGID | CXGB4_DCB_FW_PGRATE)))
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return 0;
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ets->ets_cap = dcb->pg_num_tcs_supported;
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if (local) {
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ets->willing = 1;
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INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
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} else {
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INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
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}
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pcmd.u.dcb.pgid.type = FW_PORT_DCB_TYPE_PGID;
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err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
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if (err != FW_PORT_DCB_CFG_SUCCESS) {
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dev_err(adap->pdev_dev, "DCB read PGID failed with %d\n", -err);
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return err;
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}
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tc_info = be32_to_cpu(pcmd.u.dcb.pgid.pgid);
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if (local)
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INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
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else
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INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
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pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
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err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
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if (err != FW_PORT_DCB_CFG_SUCCESS) {
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dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
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-err);
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return err;
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}
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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bwg = (tc_info >> ((7 - i) * 4)) & 0xF;
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ets->prio_tc[i] = bwg;
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ets->tc_tx_bw[i] = pcmd.u.dcb.pgrate.pgrate[i];
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ets->tc_rx_bw[i] = ets->tc_tx_bw[i];
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ets->tc_tsa[i] = pcmd.u.dcb.pgrate.tsa[i];
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}
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return 0;
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}
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static int cxgb4_ieee_get_ets(struct net_device *dev, struct ieee_ets *ets)
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{
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return cxgb4_ieee_read_ets(dev, ets, 1);
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}
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/* We reuse this for peer PFC as well, as we can't have it enabled one way */
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static int cxgb4_ieee_get_pfc(struct net_device *dev, struct ieee_pfc *pfc)
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{
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struct port_info *pi = netdev2pinfo(dev);
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struct port_dcb_info *dcb = &pi->dcb;
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memset(pfc, 0, sizeof(struct ieee_pfc));
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if (!(dcb->msgs & CXGB4_DCB_FW_PFC))
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return 0;
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pfc->pfc_cap = dcb->pfc_num_tcs_supported;
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pfc->pfc_en = bitswap_1(dcb->pfcen);
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return 0;
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}
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static int cxgb4_ieee_peer_ets(struct net_device *dev, struct ieee_ets *ets)
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{
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return cxgb4_ieee_read_ets(dev, ets, 0);
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}
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/* Fill in the Application User Priority Map associated with the
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* specified Application.
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* Priority for IEEE dcb_app is an integer, with 0 being a valid value
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@ -1106,14 +1191,23 @@ static int cxgb4_cee_peer_getpfc(struct net_device *dev, struct cee_pfc *pfc)
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struct port_info *pi = netdev2pinfo(dev);
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cxgb4_getnumtcs(dev, DCB_NUMTCS_ATTR_PFC, &(pfc->tcs_supported));
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pfc->pfc_en = pi->dcb.pfcen;
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/* Firmware sends this to us in a formwat that is a bit flipped version
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* of spec, correct it before we send it to host. This is taken care of
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* by bit shifting in other uses of pfcen
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*/
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pfc->pfc_en = bitswap_1(pi->dcb.pfcen);
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return 0;
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}
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const struct dcbnl_rtnl_ops cxgb4_dcb_ops = {
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.ieee_getets = cxgb4_ieee_get_ets,
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.ieee_getpfc = cxgb4_ieee_get_pfc,
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.ieee_getapp = cxgb4_ieee_getapp,
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.ieee_setapp = cxgb4_ieee_setapp,
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.ieee_peer_getets = cxgb4_ieee_peer_ets,
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.ieee_peer_getpfc = cxgb4_ieee_get_pfc,
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/* CEE std */
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.getstate = cxgb4_getstate,
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@ -136,6 +136,17 @@ void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
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void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
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extern const struct dcbnl_rtnl_ops cxgb4_dcb_ops;
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static inline __u8 bitswap_1(unsigned char val)
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{
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return ((val & 0x80) >> 7) |
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((val & 0x40) >> 5) |
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((val & 0x20) >> 3) |
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((val & 0x10) >> 1) |
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((val & 0x08) << 1) |
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((val & 0x04) << 3) |
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((val & 0x02) << 5) |
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((val & 0x01) << 7);
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}
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#define CXGB4_DCB_ENABLED true
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#else /* !CONFIG_CHELSIO_T4_DCB */
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