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ARM: dts: qcom: Update msm8974/apq8074 device trees

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* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
* Move spi pinctrl into board file
* Cleanup cpu node to match binding spec, enable-method and compatible
  should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
  binding spec
* Move timer node out of SoC container

Signed-off-by: Kumar Gala <galak@codeaurora.org>
This commit is contained in:
Kumar Gala 2014-05-28 12:01:29 -05:00
parent 08f9234ad6
commit ba08220aa8
2 changed files with 45 additions and 32 deletions
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28
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
View File

@ -4,7 +4,11 @@ / {
model = "Qualcomm APQ8074 Dragonboard";
compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
soc: soc {
soc {
serial@f991e000 {
status = "ok";
};
sdhci@f9824900 {
bus-width = <8>;
non-removable;
@ -15,5 +19,27 @@ sdhci@f98a4900 {
cd-gpios = <&msmgpio 62 0x1>;
bus-width = <4>;
};
pinctrl@fd510000 {
spi8_default: spi8_default {
mosi {
pins = "gpio45";
function = "blsp_spi8";
};
miso {
pins = "gpio46";
function = "blsp_spi8";
};
cs {
pins = "gpio47";
function = "blsp_spi8";
};
clk {
pins = "gpio48";
function = "blsp_spi8";
};
};
};
};
};

49
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@ -13,10 +13,10 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 9 0xf04>;
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
@ -24,6 +24,8 @@ cpu@0 {
};
cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
@ -31,6 +33,8 @@ cpu@1 {
};
cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
@ -38,6 +42,8 @@ cpu@2 {
};
cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
@ -47,7 +53,6 @@ cpu@3 {
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
interrupts = <0 2 0x4>;
qcom,saw = <&saw_l2>;
};
};
@ -57,6 +62,15 @@ cpu-pmu {
interrupts = <1 7 0xf04>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <19200000>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@ -71,15 +85,6 @@ intc: interrupt-controller@f9000000 {
<0xf9002000 0x1000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <19200000>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@ -190,6 +195,7 @@ serial@f991e000 {
interrupts = <0 108 0x0>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
sdhci@f9824900 {
@ -229,25 +235,6 @@ msmgpio: pinctrl@fd510000 {
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
spi8_default: spi8_default {
mosi {
pins = "gpio45";
function = "blsp_spi8";
};
miso {
pins = "gpio46";
function = "blsp_spi8";
};
cs {
pins = "gpio47";
function = "blsp_spi8";
};
clk {
pins = "gpio48";
function = "blsp_spi8";
};
};
};
};
};