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RTC fixes for 5.5
- cmos: revert AltCentury support on AMD/Hygon - mt6397: fix alarm register overwrite - sun6i: ensure clock is working on R40 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEycoQi/giopmpPgB12wIijOdRNOUFAl4SecUACgkQ2wIijOdR NOV+9BAAmgkn7E1l1vc2JHfeb/X0WS3X5nfOhKl021EbZpoo2U44TCB3onCy3E/p eWwQ3nrG1u3mzgv6/7+MWkIkJFxVwTLBrNgh/NW8S1/GBCqVEuwnJlSUEguKXB+R 5nn3mdtJTEKb5aopSXvmO53YRr6YytGn5o9hZwv6bQCkHB3IFYH4H4gZgR2FZEvI i+uYXCkWtlXHuE6g4jrDx6LUNEKPauGMoL6+i93lDtkJMTm4B/nAOXbPNWpwmx6H uidq0rlLMHPWYRCpn81jJ8n0eN87/kS3ozNWTgaFH27cRVrW61KHSWe2j7yl+FCq Yc+ETNuDetNAMPRfcJmvo1xrd+bR7CFV7eSBvvHmVQCltIWqEyj1Lc6xQJnAhnDx b3LfKvTAcrjeR6YwqyahWsZ4gJAhhDASoxsOZE0seKEl4v0DepOj5BD9iKg1WEkP M7+oMeT4z7Z+jcYVv36GpBkrTKjPJzcsRHYNjrx84UWm3G3FDZVC2586CMmgYvyO cDWFWBqOOGq+39YfFCH/mejLwCsXjOkbfOfnpfJIXe8n+ozwtyzAVG4tsfEVrM7B zkIDE3M+/IrGPheeP3ugDkQeSnwKC0t5uExH38Q6uDVFsv7PjqJD1Ry7fyR5X0VL HjeBEpxUYBGpixIv5qNIqMIVPX1tDJ8v48kE8jWHEW1jJkb/DqI= =3S3X -----END PGP SIGNATURE----- Merge tag 'rtc-5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux Pull RTC fixes from Alexandre Belloni: "A few fixes for this cycle. The CMOS AltCentury support broke a few platforms with a recent BIOS so I reverted it. The mt6397 fix is not that critical but good to have. And finally, the sun6i fix repairs WiFi and BT on a few platforms. Summary: - cmos: revert AltCentury support on AMD/Hygon - mt6397: fix alarm register overwrite - sun6i: ensure clock is working on R40" * tag 'rtc-5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: rtc: cmos: Revert "rtc: Fix the AltCentury value on AMD/Hygon platform" rtc: mt6397: fix alarm register overwrite rtc: sun6i: Add support for RTC clocks on R40
This commit is contained in:
Linus Torvalds
commit
b967793c96
@ -172,20 +172,7 @@ int mc146818_set_time(struct rtc_time *time)
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save_control = CMOS_READ(RTC_CONTROL);
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CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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#ifdef CONFIG_X86
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 == 0x17) ||
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boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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CMOS_WRITE((save_freq_select & (~RTC_DIV_RESET2)),
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RTC_FREQ_SELECT);
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save_freq_select &= ~RTC_DIV_RESET2;
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} else
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CMOS_WRITE((save_freq_select | RTC_DIV_RESET2),
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RTC_FREQ_SELECT);
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#else
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CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
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#endif
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CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
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#ifdef CONFIG_MACH_DECSTATION
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CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
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@ -47,7 +47,7 @@ static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
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irqen = irqsta & ~RTC_IRQ_EN_AL;
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mutex_lock(&rtc->lock);
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if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
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irqen) < 0)
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irqen) == 0)
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mtk_rtc_write_trigger(rtc);
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mutex_unlock(&rtc->lock);
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@ -169,12 +169,12 @@ static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
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mutex_unlock(&rtc->lock);
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tm->tm_sec = data[RTC_OFFSET_SEC];
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tm->tm_min = data[RTC_OFFSET_MIN];
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tm->tm_hour = data[RTC_OFFSET_HOUR];
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tm->tm_mday = data[RTC_OFFSET_DOM];
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tm->tm_mon = data[RTC_OFFSET_MTH];
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tm->tm_year = data[RTC_OFFSET_YEAR];
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tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
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tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
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tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
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tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
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tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
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tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
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tm->tm_year += RTC_MIN_YEAR_OFFSET;
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tm->tm_mon--;
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@ -195,14 +195,25 @@ static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
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tm->tm_year -= RTC_MIN_YEAR_OFFSET;
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tm->tm_mon++;
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data[RTC_OFFSET_SEC] = tm->tm_sec;
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data[RTC_OFFSET_MIN] = tm->tm_min;
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data[RTC_OFFSET_HOUR] = tm->tm_hour;
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data[RTC_OFFSET_DOM] = tm->tm_mday;
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data[RTC_OFFSET_MTH] = tm->tm_mon;
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data[RTC_OFFSET_YEAR] = tm->tm_year;
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mutex_lock(&rtc->lock);
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ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
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data, RTC_OFFSET_COUNT);
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if (ret < 0)
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goto exit;
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data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
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(tm->tm_sec & RTC_AL_SEC_MASK));
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data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
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(tm->tm_min & RTC_AL_MIN_MASK));
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data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
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(tm->tm_hour & RTC_AL_HOU_MASK));
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data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
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(tm->tm_mday & RTC_AL_DOM_MASK));
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data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
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(tm->tm_mon & RTC_AL_MTH_MASK));
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data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
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(tm->tm_year & RTC_AL_YEA_MASK));
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if (alm->enabled) {
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ret = regmap_bulk_write(rtc->regmap,
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rtc->addr_base + RTC_AL_SEC,
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@ -379,6 +379,22 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
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CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
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sun50i_h6_rtc_clk_init);
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/*
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* The R40 user manual is self-conflicting on whether the prescaler is
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* fixed or configurable. The clock diagram shows it as fixed, but there
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* is also a configurable divider in the RTC block.
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*/
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static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
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.rc_osc_rate = 16000000,
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.fixed_prescaler = 512,
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};
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static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
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{
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sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
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}
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CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
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sun8i_r40_rtc_clk_init);
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static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
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.rc_osc_rate = 32000,
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.has_out_clk = 1,
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@ -46,6 +46,14 @@
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#define RTC_AL_SEC 0x0018
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#define RTC_AL_SEC_MASK 0x003f
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#define RTC_AL_MIN_MASK 0x003f
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#define RTC_AL_HOU_MASK 0x001f
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#define RTC_AL_DOM_MASK 0x001f
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#define RTC_AL_DOW_MASK 0x0007
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#define RTC_AL_MTH_MASK 0x000f
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#define RTC_AL_YEA_MASK 0x007f
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#define RTC_PDN2 0x002e
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#define RTC_PDN2_PWRON_ALARM BIT(4)
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