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ARM: dts: Add Broadcom Hurricane 2 DTS include file
Describe the Broadcom Hurricane 2 SoC comprised of a Cortex-A9 CPU complex along with standard iProc peripherals: * timers * SPI controller * NAND controller * a single AMAC (Ethernet MAC controller) * dual PCIe controllers The design is largely similar to existing iProc-based SoCs such as Northstar Plus. Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Florian Fainelli
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c6d2efd127
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368
arch/arm/boot/dts/bcm-hr2.dtsi
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368
arch/arm/boot/dts/bcm-hr2.dtsi
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,hr2";
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model = "Broadcom Hurricane 2 SoC";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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mpcore@19000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x00023000>;
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#address-cells = <1>;
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#size-cells = <1>;
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a9pll: arm_clk@0 {
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#clock-cells = <0>;
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compatible = "brcm,hr2-armpll";
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clocks = <&osc>;
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reg = <0x0 0x1000>;
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};
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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twd-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&periph_clk>;
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};
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twd-watchdog@20620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x20620 0x20>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: l2-cache@22000 {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&a9pll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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axi@18000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x0011c40c>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@300 {
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compatible = "ns16550a";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart1: serial@400 {
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compatible = "ns16550a";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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dma@20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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status = "disabled";
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};
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amac0: ethernet@22000 {
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compatible = "brcm,nsp-amac";
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reg = <0x22000 0x1000>,
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<0x110000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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nand: nand@26000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x26000 0x600>,
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<0x11b408 0x600>,
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<0x026f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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gpiob: gpio@30000 {
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compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
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reg = <0x30000 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <4>;
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interrupt-controller;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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};
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pwm: pwm@31000 {
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compatible = "brcm,iproc-pwm";
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reg = <0x31000 0x28>;
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clocks = <&osc>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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rng: rng@33000 {
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compatible = "brcm,bcm-nsp-rng";
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reg = <0x33000 0x14>;
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};
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qspi: qspi@27200 {
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compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
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reg = <0x027200 0x184>,
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<0x027000 0x124>,
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<0x11c408 0x004>,
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<0x0273a0 0x01c>;
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reg-names = "mspi", "bspi", "intr_regs",
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"intr_status_reg";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overhead",
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"mspi_done",
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"mspi_halted";
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* partitions defined in board DTS */
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};
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ccbtimer0: timer@34000 {
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compatible = "arm,sp804";
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reg = <0x34000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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ccbtimer1: timer@35000 {
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compatible = "arm,sp804";
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reg = <0x35000 0x1000>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c0: i2c@38000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x38000 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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};
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watchdog@39000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x39000 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c1: i2c@3b000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x3b000 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
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clock-frequency = <100000>;
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};
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};
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pflash: nor@20000000 {
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compatible = "cfi-flash", "jedec-flash";
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reg = <0x20000000 0x04000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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/* partitions defined in board DTS */
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};
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* Note: The HW does not support I/O resources. So,
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* only the memory resource range is being specified.
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*/
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ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
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status = "disabled";
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msi-parent = <&msi0>;
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msi0: msi-controller {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>,
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<GIC_SPI 183 IRQ_TYPE_NONE>,
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<GIC_SPI 184 IRQ_TYPE_NONE>,
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<GIC_SPI 185 IRQ_TYPE_NONE>;
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brcm,pcie-msi-inten;
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};
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};
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pcie1: pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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/* Note: The HW does not support I/O resources. So,
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* only the memory resource range is being specified.
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*/
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ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
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status = "disabled";
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msi-parent = <&msi1>;
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msi1: msi-controller {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>,
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<GIC_SPI 189 IRQ_TYPE_NONE>,
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<GIC_SPI 190 IRQ_TYPE_NONE>,
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<GIC_SPI 191 IRQ_TYPE_NONE>;
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brcm,pcie-msi-inten;
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};
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};
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};
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