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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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regulator: rtmv20: Adds support for Richtek RTMV20 load switch regulator
Add support for Richtek RTMV20 load switch regulator. Signed-off-by: ChiYuan Huang <cy_huang@richtek.com> Link: https://lore.kernel.org/r/1601277584-5526-1-git-send-email-u0084500@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
ChiYuan Huang
Mark Brown
parent
8d23b0b8fc
commit
b8c054a5ea
@ -939,6 +939,15 @@ config REGULATOR_RT5033
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RT5033 PMIC. The device supports multiple regulators like
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current source, LDO and Buck.
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config REGULATOR_RTMV20
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tristate "RTMV20 Laser Diode Regulator"
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depends on I2C
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select REGMAP_I2C
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help
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This driver adds support for the load switch current regulator on
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the Richtek RTMV20. It can support the load current up to 6A and
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integrate strobe/vsync/fsin signal to synchronize the IR camera.
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config REGULATOR_S2MPA01
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tristate "Samsung S2MPA01 voltage regulator"
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depends on MFD_SEC_CORE || COMPILE_TEST
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@ -116,6 +116,7 @@ obj-$(CONFIG_REGULATOR_RN5T618) += rn5t618-regulator.o
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obj-$(CONFIG_REGULATOR_ROHM) += rohm-regulator.o
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obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o
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obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o
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obj-$(CONFIG_REGULATOR_RTMV20) += rtmv20-regulator.o
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obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
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obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
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obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
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392
drivers/regulator/rtmv20-regulator.c
Normal file
392
drivers/regulator/rtmv20-regulator.c
Normal file
@ -0,0 +1,392 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#define RTMV20_REG_DEVINFO 0x00
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#define RTMV20_REG_PULSEDELAY 0x01
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#define RTMV20_REG_PULSEWIDTH 0x03
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#define RTMV20_REG_LDCTRL1 0x05
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#define RTMV20_REG_ESPULSEWIDTH 0x06
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#define RTMV20_REG_ESLDCTRL1 0x08
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#define RTMV20_REG_LBP 0x0A
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#define RTMV20_REG_LDCTRL2 0x0B
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#define RTMV20_REG_FSIN1CTRL1 0x0D
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#define RTMV20_REG_FSIN1CTRL3 0x0F
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#define RTMV20_REG_FSIN2CTRL1 0x10
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#define RTMV20_REG_FSIN2CTRL3 0x12
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#define RTMV20_REG_ENCTRL 0x13
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#define RTMV20_REG_STRBVSYNDLYL 0x29
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#define RTMV20_REG_LDIRQ 0x30
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#define RTMV20_REG_LDSTAT 0x40
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#define RTMV20_REG_LDMASK 0x50
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#define RTMV20_VID_MASK GENMASK(7, 4)
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#define RICHTEK_VID 0x80
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#define RTMV20_LDCURR_MASK GENMASK(7, 0)
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#define RTMV20_DELAY_MASK GENMASK(9, 0)
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#define RTMV20_WIDTH_MASK GENMASK(13, 0)
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#define RTMV20_WIDTH2_MASK GENMASK(7, 0)
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#define RTMV20_LBPLVL_MASK GENMASK(3, 0)
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#define RTMV20_LBPEN_MASK BIT(7)
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#define RTMV20_STROBEPOL_MASK BIT(1)
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#define RTMV20_VSYNPOL_MASK BIT(1)
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#define RTMV20_FSINEN_MASK BIT(7)
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#define RTMV20_ESEN_MASK BIT(6)
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#define RTMV20_FSINOUT_MASK BIT(2)
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#define LDENABLE_MASK (BIT(3) | BIT(0))
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#define OTPEVT_MASK BIT(4)
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#define SHORTEVT_MASK BIT(3)
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#define OPENEVT_MASK BIT(2)
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#define LBPEVT_MASK BIT(1)
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#define OCPEVT_MASK BIT(0)
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#define FAILEVT_MASK (SHORTEVT_MASK | OPENEVT_MASK | LBPEVT_MASK)
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#define RTMV20_LSW_MINUA 0
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#define RTMV20_LSW_MAXUA 6000000
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#define RTMV20_LSW_STEPUA 30000
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#define RTMV20_LSW_DEFAULTUA 3000000
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#define RTMV20_I2CRDY_TIMEUS 200
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#define RTMV20_CSRDY_TIMEUS 2000
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struct rtmv20_priv {
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struct device *dev;
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struct regmap *regmap;
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struct gpio_desc *enable_gpio;
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struct regulator_dev *rdev;
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};
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static int rtmv20_lsw_enable(struct regulator_dev *rdev)
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{
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struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
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int ret;
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gpiod_set_value(priv->enable_gpio, 1);
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/* Wait for I2C can be accessed */
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usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
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/* HW re-enable, disable cache only and sync regcache here */
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regcache_cache_only(priv->regmap, false);
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ret = regcache_sync(priv->regmap);
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if (ret)
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return ret;
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return regulator_enable_regmap(rdev);
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}
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static int rtmv20_lsw_disable(struct regulator_dev *rdev)
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{
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struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
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int ret;
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ret = regulator_disable_regmap(rdev);
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if (ret)
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return ret;
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/* Mark the regcache as dirty and cache only before HW disabled */
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regcache_cache_only(priv->regmap, true);
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regcache_mark_dirty(priv->regmap);
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gpiod_set_value(priv->enable_gpio, 0);
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return 0;
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}
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static const struct regulator_ops rtmv20_regulator_ops = {
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.set_current_limit = regulator_set_current_limit_regmap,
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.get_current_limit = regulator_get_current_limit_regmap,
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.enable = rtmv20_lsw_enable,
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.disable = rtmv20_lsw_disable,
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.is_enabled = regulator_is_enabled_regmap,
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};
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static const struct regulator_desc rtmv20_lsw_desc = {
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.name = "rtmv20,lsw",
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.of_match = of_match_ptr("lsw"),
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.type = REGULATOR_CURRENT,
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.owner = THIS_MODULE,
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.ops = &rtmv20_regulator_ops,
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.csel_reg = RTMV20_REG_LDCTRL1,
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.csel_mask = RTMV20_LDCURR_MASK,
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.enable_reg = RTMV20_REG_ENCTRL,
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.enable_mask = LDENABLE_MASK,
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.enable_time = RTMV20_CSRDY_TIMEUS,
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};
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static irqreturn_t rtmv20_irq_handler(int irq, void *data)
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{
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struct rtmv20_priv *priv = data;
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unsigned int val;
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int ret;
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ret = regmap_read(priv->regmap, RTMV20_REG_LDIRQ, &val);
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if (ret) {
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dev_err(priv->dev, "Failed to get irq flags\n");
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return IRQ_NONE;
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}
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if (val & OTPEVT_MASK)
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regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_TEMP, NULL);
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if (val & OCPEVT_MASK)
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regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
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if (val & FAILEVT_MASK)
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regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_FAIL, NULL);
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return IRQ_HANDLED;
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}
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static u32 clamp_to_selector(u32 val, u32 min, u32 max, u32 step)
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{
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u32 retval = clamp_val(val, min, max);
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return (retval - min) / step;
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}
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static int rtmv20_properties_init(struct rtmv20_priv *priv)
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{
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const struct {
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const char *name;
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u32 def;
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u32 min;
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u32 max;
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u32 step;
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u32 addr;
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u32 mask;
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} props[] = {
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{ "ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
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RTMV20_DELAY_MASK },
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{ "ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
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RTMV20_WIDTH_MASK },
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{ "fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
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RTMV20_DELAY_MASK },
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{ "fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3, RTMV20_WIDTH2_MASK },
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{ "fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
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RTMV20_DELAY_MASK },
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{ "fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3, RTMV20_WIDTH2_MASK },
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{ "es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
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RTMV20_WIDTH_MASK },
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{ "es-ld-current-microamp", 3000000, 0, 6000000, 30000, RTMV20_REG_ESLDCTRL1,
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RTMV20_LDCURR_MASK },
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{ "lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
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RTMV20_LBPLVL_MASK },
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{ "lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
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{ "strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_STROBEPOL_MASK },
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{ "vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2, RTMV20_VSYNPOL_MASK },
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{ "fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
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{ "fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
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{ "es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
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};
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(props); i++) {
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__be16 bval16;
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u16 val16;
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u32 temp;
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int significant_bit = fls(props[i].mask);
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int shift = ffs(props[i].mask) - 1;
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if (props[i].max > 1) {
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ret = device_property_read_u32(priv->dev, props[i].name, &temp);
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if (ret)
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temp = props[i].def;
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} else
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temp = device_property_read_bool(priv->dev, props[i].name);
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temp = clamp_to_selector(temp, props[i].min, props[i].max, props[i].step);
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/* If significant bit is over 8, two byte access, others one */
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if (significant_bit > 8) {
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ret = regmap_raw_read(priv->regmap, props[i].addr, &bval16, sizeof(bval16));
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if (ret)
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return ret;
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val16 = be16_to_cpu(bval16);
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val16 &= ~props[i].mask;
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val16 |= (temp << shift);
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bval16 = cpu_to_be16(val16);
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ret = regmap_raw_write(priv->regmap, props[i].addr, &bval16,
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sizeof(bval16));
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} else {
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ret = regmap_update_bits(priv->regmap, props[i].addr, props[i].mask,
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temp << shift);
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}
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if (ret)
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return ret;
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}
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return 0;
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}
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static int rtmv20_check_chip_exist(struct rtmv20_priv *priv)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(priv->regmap, RTMV20_REG_DEVINFO, &val);
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if (ret)
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return ret;
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if ((val & RTMV20_VID_MASK) != RICHTEK_VID)
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return -ENODEV;
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return 0;
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}
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static bool rtmv20_is_accessible_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case RTMV20_REG_DEVINFO ... RTMV20_REG_STRBVSYNDLYL:
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case RTMV20_REG_LDIRQ:
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case RTMV20_REG_LDSTAT:
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case RTMV20_REG_LDMASK:
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return true;
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}
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return false;
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}
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static bool rtmv20_is_volatile_reg(struct device *dev, unsigned int reg)
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{
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if (reg == RTMV20_REG_LDIRQ || reg == RTMV20_REG_LDSTAT)
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return true;
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return false;
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}
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static const struct regmap_config rtmv20_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.max_register = RTMV20_REG_LDMASK,
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.writeable_reg = rtmv20_is_accessible_reg,
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.readable_reg = rtmv20_is_accessible_reg,
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.volatile_reg = rtmv20_is_volatile_reg,
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};
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static int rtmv20_probe(struct i2c_client *i2c)
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{
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struct rtmv20_priv *priv;
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struct regulator_config config = {};
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int ret;
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priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = &i2c->dev;
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/* Before regmap register, configure HW enable to make I2C accessible */
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priv->enable_gpio = devm_gpiod_get(&i2c->dev, "enable", GPIOD_OUT_HIGH);
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if (IS_ERR(priv->enable_gpio)) {
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dev_err(&i2c->dev, "Failed to get enable gpio\n");
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return PTR_ERR(priv->enable_gpio);
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}
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/* Wait for I2C can be accessed */
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usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
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priv->regmap = devm_regmap_init_i2c(i2c, &rtmv20_regmap_config);
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if (IS_ERR(priv->regmap)) {
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dev_err(&i2c->dev, "Failed to allocate register map\n");
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return PTR_ERR(priv->regmap);
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}
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ret = rtmv20_check_chip_exist(priv);
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if (ret) {
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dev_err(&i2c->dev, "Chip vendor info is not matched\n");
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return ret;
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}
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ret = rtmv20_properties_init(priv);
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if (ret) {
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dev_err(&i2c->dev, "Failed to init properties\n");
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return ret;
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}
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/*
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* keep in shutdown mode to minimize the current consumption
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* and also mark regcache as dirty
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*/
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regcache_mark_dirty(priv->regmap);
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gpiod_set_value(priv->enable_gpio, 0);
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config.dev = &i2c->dev;
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config.regmap = priv->regmap;
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config.driver_data = priv;
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priv->rdev = devm_regulator_register(&i2c->dev, &rtmv20_lsw_desc, &config);
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if (IS_ERR(priv->rdev)) {
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dev_err(&i2c->dev, "Failed to register regulator\n");
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return PTR_ERR(priv->rdev);
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}
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/* Unmask all events before IRQ registered */
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ret = regmap_write(priv->regmap, RTMV20_REG_LDMASK, 0);
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if (ret)
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return ret;
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return devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rtmv20_irq_handler,
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IRQF_ONESHOT, dev_name(&i2c->dev), priv);
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}
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static int __maybe_unused rtmv20_suspend(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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/*
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* When system suspend, disable irq to prevent interrupt trigger
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* during I2C bus suspend
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*/
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disable_irq(i2c->irq);
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if (device_may_wakeup(dev))
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enable_irq_wake(i2c->irq);
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return 0;
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}
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static int __maybe_unused rtmv20_resume(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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/* Enable irq after I2C bus already resume */
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enable_irq(i2c->irq);
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if (device_may_wakeup(dev))
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disable_irq_wake(i2c->irq);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(rtmv20_pm, rtmv20_suspend, rtmv20_resume);
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static const struct of_device_id __maybe_unused rtmv20_of_id[] = {
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{ .compatible = "richtek,rtmv20", },
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{}
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};
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MODULE_DEVICE_TABLE(of, rtmv20_of_id);
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static struct i2c_driver rtmv20_driver = {
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.driver = {
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.name = "rtmv20",
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.of_match_table = of_match_ptr(rtmv20_of_id),
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.pm = &rtmv20_pm,
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},
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.probe_new = rtmv20_probe,
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};
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module_i2c_driver(rtmv20_driver);
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MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
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MODULE_DESCRIPTION("Richtek RTMV20 Regulator Driver");
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MODULE_LICENSE("GPL v2");
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