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kbuild: remove extra ifdef/endif of top Makefile
The GNU make's origin function know undefined variable well, so the outer ifdef/endif conditional checking is unneeded. From `info make` documentation, origin will return `undefined' if VARIABLE was never defined. `command line' if VARIABLE was defined on the command line. ... Therefore, $(origin V) will get a value anyway, killing ifdef/endif is viable and safe. Furthermore, I've checked the minimal requirements from Documentation/Changes is GNU make 3.79.1, and that version of GNU make has support of origin function well already, so now it's safe to kill the outer conditional checking, without upgrading the minimal requirements. Signed-off-by: Cheng Renquan <crq@kernel.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
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10
Makefile
10
Makefile
@ -35,11 +35,9 @@ MAKEFLAGS += -rR --no-print-directory
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# To put more focus on warnings, be less verbose as default
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# Use 'make V=1' to see the full commands
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ifdef V
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ifeq ("$(origin V)", "command line")
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KBUILD_VERBOSE = $(V)
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endif
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endif
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ifndef KBUILD_VERBOSE
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KBUILD_VERBOSE = 0
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endif
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@ -54,11 +52,9 @@ endif
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# See the file "Documentation/sparse.txt" for more details, including
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# where to get the "sparse" utility.
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ifdef C
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ifeq ("$(origin C)", "command line")
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KBUILD_CHECKSRC = $(C)
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endif
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endif
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ifndef KBUILD_CHECKSRC
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KBUILD_CHECKSRC = 0
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endif
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@ -69,12 +65,10 @@ endif
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ifdef SUBDIRS
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KBUILD_EXTMOD ?= $(SUBDIRS)
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endif
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ifdef M
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ifeq ("$(origin M)", "command line")
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KBUILD_EXTMOD := $(M)
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endif
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endif
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# kbuild supports saving output files in a separate directory.
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# To locate output files in a separate directory two syntaxes are supported.
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@ -98,11 +92,9 @@ ifeq ($(KBUILD_SRC),)
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# OK, Make called in directory where kernel src resides
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# Do we want to locate output files in a separate directory?
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ifdef O
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ifeq ("$(origin O)", "command line")
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KBUILD_OUTPUT := $(O)
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endif
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endif
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# That's our default target when none is given on the command line
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PHONY := _all
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