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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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crypto: bfin_crc - CRC hardware driver for BF60x family processors.
The CRC peripheral is a hardware block used to compute the CRC of the block of data. This is based on a CRC32 engine which computes the CRC value of 32b data words presented to it. For data words of < 32b in size, this driver pack 0 automatically into 32b data units. This driver implements the async hash crypto framework API. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Sonic Zhang
Herbert Xu
parent
a482b081a2
commit
b8840098b7
@ -325,4 +325,11 @@ if CRYPTO_DEV_UX500
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source "drivers/crypto/ux500/Kconfig"
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endif # if CRYPTO_DEV_UX500
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config CRYPTO_DEV_BFIN_CRC
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tristate "Support for Blackfin CRC hardware"
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depends on BF60x
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help
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Newer Blackfin processors have CRC hardware. Select this if you
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want to use the Blackfin CRC module.
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endif # CRYPTO_HW
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@ -14,4 +14,5 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
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obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
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obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
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obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
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obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
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obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
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780
drivers/crypto/bfin_crc.c
Normal file
780
drivers/crypto/bfin_crc.c
Normal file
@ -0,0 +1,780 @@
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/*
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* Cryptographic API.
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*
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* Support Blackfin CRC HW acceleration.
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/unaligned/access_ok.h>
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#include <linux/crypto.h>
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#include <linux/cryptohash.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/algapi.h>
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#include <crypto/hash.h>
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#include <crypto/internal/hash.h>
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#include <asm/blackfin.h>
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#include <asm/bfin_crc.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#define CRC_CCRYPTO_QUEUE_LENGTH 5
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#define DRIVER_NAME "bfin-hmac-crc"
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#define CHKSUM_DIGEST_SIZE 4
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#define CHKSUM_BLOCK_SIZE 1
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#define CRC_MAX_DMA_DESC 100
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#define CRC_CRYPTO_STATE_UPDATE 1
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#define CRC_CRYPTO_STATE_FINALUPDATE 2
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#define CRC_CRYPTO_STATE_FINISH 3
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struct bfin_crypto_crc {
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struct list_head list;
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struct device *dev;
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spinlock_t lock;
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int irq;
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int dma_ch;
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u32 poly;
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volatile struct crc_register *regs;
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struct ahash_request *req; /* current request in operation */
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struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */
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dma_addr_t sg_dma; /* phy addr of sg dma descriptors */
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u8 *sg_mid_buf;
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struct tasklet_struct done_task;
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struct crypto_queue queue; /* waiting requests */
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u8 busy:1; /* crc device in operation flag */
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};
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static struct bfin_crypto_crc_list {
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struct list_head dev_list;
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spinlock_t lock;
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} crc_list;
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struct bfin_crypto_crc_reqctx {
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struct bfin_crypto_crc *crc;
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unsigned int total; /* total request bytes */
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size_t sg_buflen; /* bytes for this update */
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unsigned int sg_nents;
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struct scatterlist *sg; /* sg list head for this update*/
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struct scatterlist bufsl[2]; /* chained sg list */
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size_t bufnext_len;
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size_t buflast_len;
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u8 bufnext[CHKSUM_DIGEST_SIZE]; /* extra bytes for next udpate */
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u8 buflast[CHKSUM_DIGEST_SIZE]; /* extra bytes from last udpate */
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u8 flag;
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};
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struct bfin_crypto_crc_ctx {
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struct bfin_crypto_crc *crc;
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u32 key;
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};
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/*
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* derive number of elements in scatterlist
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*/
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static int sg_count(struct scatterlist *sg_list)
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{
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struct scatterlist *sg = sg_list;
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int sg_nents = 1;
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if (sg_list == NULL)
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return 0;
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while (!sg_is_last(sg)) {
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sg_nents++;
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sg = scatterwalk_sg_next(sg);
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}
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return sg_nents;
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}
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/*
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* get element in scatter list by given index
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*/
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static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nents,
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unsigned int index)
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{
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struct scatterlist *sg = NULL;
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int i;
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for_each_sg(sg_list, sg, nents, i)
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if (i == index)
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break;
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return sg;
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}
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static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key)
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{
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crc->regs->datacntrld = 0;
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crc->regs->control = MODE_CALC_CRC << OPMODE_OFFSET;
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crc->regs->curresult = key;
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/* setup CRC interrupts */
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crc->regs->status = CMPERRI | DCNTEXPI;
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crc->regs->intrenset = CMPERRI | DCNTEXPI;
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SSYNC();
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return 0;
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}
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static int bfin_crypto_crc_init(struct ahash_request *req)
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{
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
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struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
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struct bfin_crypto_crc *crc;
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dev_dbg(crc->dev, "crc_init\n");
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spin_lock_bh(&crc_list.lock);
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list_for_each_entry(crc, &crc_list.dev_list, list) {
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crc_ctx->crc = crc;
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break;
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}
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spin_unlock_bh(&crc_list.lock);
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if (sg_count(req->src) > CRC_MAX_DMA_DESC) {
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dev_dbg(crc->dev, "init: requested sg list is too big > %d\n",
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CRC_MAX_DMA_DESC);
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return -EINVAL;
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}
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ctx->crc = crc;
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ctx->bufnext_len = 0;
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ctx->buflast_len = 0;
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ctx->sg_buflen = 0;
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ctx->total = 0;
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ctx->flag = 0;
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/* init crc results */
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put_unaligned_le32(crc_ctx->key, req->result);
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dev_dbg(crc->dev, "init: digest size: %d\n",
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crypto_ahash_digestsize(tfm));
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return bfin_crypto_crc_init_hw(crc, crc_ctx->key);
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}
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static void bfin_crypto_crc_config_dma(struct bfin_crypto_crc *crc)
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{
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struct scatterlist *sg;
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struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(crc->req);
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int i = 0, j = 0;
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unsigned long dma_config;
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unsigned int dma_count;
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unsigned int dma_addr;
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unsigned int mid_dma_count = 0;
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int dma_mod;
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dma_map_sg(crc->dev, ctx->sg, ctx->sg_nents, DMA_TO_DEVICE);
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for_each_sg(ctx->sg, sg, ctx->sg_nents, j) {
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dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32;
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dma_addr = sg_dma_address(sg);
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/* deduce extra bytes in last sg */
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if (sg_is_last(sg))
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dma_count = sg_dma_len(sg) - ctx->bufnext_len;
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else
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dma_count = sg_dma_len(sg);
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if (mid_dma_count) {
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/* Append last middle dma buffer to 4 bytes with first
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bytes in current sg buffer. Move addr of current
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sg and deduce the length of current sg.
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*/
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memcpy(crc->sg_mid_buf +((i-1) << 2) + mid_dma_count,
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(void *)dma_addr,
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CHKSUM_DIGEST_SIZE - mid_dma_count);
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dma_addr += CHKSUM_DIGEST_SIZE - mid_dma_count;
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dma_count -= CHKSUM_DIGEST_SIZE - mid_dma_count;
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}
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/* chop current sg dma len to multiple of 32 bits */
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mid_dma_count = dma_count % 4;
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dma_count &= ~0x3;
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if (dma_addr % 4 == 0) {
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dma_config |= WDSIZE_32;
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dma_count >>= 2;
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dma_mod = 4;
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} else if (dma_addr % 2 == 0) {
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dma_config |= WDSIZE_16;
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dma_count >>= 1;
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dma_mod = 2;
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} else {
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dma_config |= WDSIZE_8;
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dma_mod = 1;
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}
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crc->sg_cpu[i].start_addr = dma_addr;
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crc->sg_cpu[i].cfg = dma_config;
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crc->sg_cpu[i].x_count = dma_count;
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crc->sg_cpu[i].x_modify = dma_mod;
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dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
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"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
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i, crc->sg_cpu[i].start_addr,
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crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
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crc->sg_cpu[i].x_modify);
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i++;
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if (mid_dma_count) {
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/* copy extra bytes to next middle dma buffer */
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dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 |
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DMAEN | PSIZE_32 | WDSIZE_32;
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memcpy(crc->sg_mid_buf + (i << 2),
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(void *)(dma_addr + (dma_count << 2)),
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mid_dma_count);
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/* setup new dma descriptor for next middle dma */
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crc->sg_cpu[i].start_addr = dma_map_single(crc->dev,
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crc->sg_mid_buf + (i << 2),
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CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
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crc->sg_cpu[i].cfg = dma_config;
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crc->sg_cpu[i].x_count = 1;
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crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
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dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
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"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
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i, crc->sg_cpu[i].start_addr,
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crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
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crc->sg_cpu[i].x_modify);
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i++;
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}
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}
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dma_config = DMAFLOW_ARRAY | RESTART | NDSIZE_3 | DMAEN | PSIZE_32 | WDSIZE_32;
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/* For final update req, append the buffer for next update as well*/
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if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
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ctx->flag == CRC_CRYPTO_STATE_FINISH)) {
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crc->sg_cpu[i].start_addr = dma_map_single(crc->dev, ctx->bufnext,
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CHKSUM_DIGEST_SIZE, DMA_TO_DEVICE);
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crc->sg_cpu[i].cfg = dma_config;
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crc->sg_cpu[i].x_count = 1;
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crc->sg_cpu[i].x_modify = CHKSUM_DIGEST_SIZE;
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dev_dbg(crc->dev, "%d: crc_dma: start_addr:0x%lx, "
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"cfg:0x%lx, x_count:0x%lx, x_modify:0x%lx\n",
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i, crc->sg_cpu[i].start_addr,
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crc->sg_cpu[i].cfg, crc->sg_cpu[i].x_count,
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crc->sg_cpu[i].x_modify);
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i++;
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}
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if (i == 0)
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return;
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flush_dcache_range((unsigned int)crc->sg_cpu,
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(unsigned int)crc->sg_cpu +
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i * sizeof(struct dma_desc_array));
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/* Set the last descriptor to stop mode */
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crc->sg_cpu[i - 1].cfg &= ~(DMAFLOW | NDSIZE);
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crc->sg_cpu[i - 1].cfg |= DI_EN;
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set_dma_curr_desc_addr(crc->dma_ch, (unsigned long *)crc->sg_dma);
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set_dma_x_count(crc->dma_ch, 0);
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set_dma_x_modify(crc->dma_ch, 0);
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SSYNC();
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set_dma_config(crc->dma_ch, dma_config);
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}
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static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc,
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struct ahash_request *req)
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{
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struct crypto_async_request *async_req, *backlog;
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struct bfin_crypto_crc_reqctx *ctx;
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struct scatterlist *sg;
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int ret = 0;
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int nsg, i, j;
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unsigned int nextlen;
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unsigned long flags;
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spin_lock_irqsave(&crc->lock, flags);
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if (req)
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ret = ahash_enqueue_request(&crc->queue, req);
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if (crc->busy) {
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spin_unlock_irqrestore(&crc->lock, flags);
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return ret;
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}
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backlog = crypto_get_backlog(&crc->queue);
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async_req = crypto_dequeue_request(&crc->queue);
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if (async_req)
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crc->busy = 1;
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spin_unlock_irqrestore(&crc->lock, flags);
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if (!async_req)
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return ret;
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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req = ahash_request_cast(async_req);
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crc->req = req;
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ctx = ahash_request_ctx(req);
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ctx->sg = NULL;
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ctx->sg_buflen = 0;
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ctx->sg_nents = 0;
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dev_dbg(crc->dev, "handling new req, flag=%u, nbytes: %d\n",
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ctx->flag, req->nbytes);
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if (ctx->flag == CRC_CRYPTO_STATE_FINISH) {
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if (ctx->bufnext_len == 0) {
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crc->busy = 0;
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return 0;
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}
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/* Pack last crc update buffer to 32bit */
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memset(ctx->bufnext + ctx->bufnext_len, 0,
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CHKSUM_DIGEST_SIZE - ctx->bufnext_len);
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} else {
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/* Pack small data which is less than 32bit to buffer for next update. */
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if (ctx->bufnext_len + req->nbytes < CHKSUM_DIGEST_SIZE) {
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memcpy(ctx->bufnext + ctx->bufnext_len,
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sg_virt(req->src), req->nbytes);
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ctx->bufnext_len += req->nbytes;
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if (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE &&
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ctx->bufnext_len) {
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goto finish_update;
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} else {
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crc->busy = 0;
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return 0;
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}
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}
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if (ctx->bufnext_len) {
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/* Chain in extra bytes of last update */
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ctx->buflast_len = ctx->bufnext_len;
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memcpy(ctx->buflast, ctx->bufnext, ctx->buflast_len);
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nsg = ctx->sg_buflen ? 2 : 1;
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sg_init_table(ctx->bufsl, nsg);
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sg_set_buf(ctx->bufsl, ctx->buflast, ctx->buflast_len);
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if (nsg > 1)
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scatterwalk_sg_chain(ctx->bufsl, nsg,
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req->src);
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ctx->sg = ctx->bufsl;
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} else
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ctx->sg = req->src;
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/* Chop crc buffer size to multiple of 32 bit */
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nsg = ctx->sg_nents = sg_count(ctx->sg);
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ctx->sg_buflen = ctx->buflast_len + req->nbytes;
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ctx->bufnext_len = ctx->sg_buflen % 4;
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ctx->sg_buflen &= ~0x3;
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if (ctx->bufnext_len) {
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/* copy extra bytes to buffer for next update */
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memset(ctx->bufnext, 0, CHKSUM_DIGEST_SIZE);
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nextlen = ctx->bufnext_len;
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for (i = nsg - 1; i >= 0; i--) {
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sg = sg_get(ctx->sg, nsg, i);
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j = min(nextlen, sg_dma_len(sg));
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memcpy(ctx->bufnext + nextlen - j,
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sg_virt(sg) + sg_dma_len(sg) - j, j);
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if (j == sg_dma_len(sg))
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ctx->sg_nents--;
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nextlen -= j;
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if (nextlen == 0)
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break;
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}
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}
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}
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finish_update:
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if (ctx->bufnext_len && (ctx->flag == CRC_CRYPTO_STATE_FINALUPDATE ||
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ctx->flag == CRC_CRYPTO_STATE_FINISH))
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ctx->sg_buflen += CHKSUM_DIGEST_SIZE;
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/* set CRC data count before start DMA */
|
||||
crc->regs->datacnt = ctx->sg_buflen >> 2;
|
||||
|
||||
/* setup and enable CRC DMA */
|
||||
bfin_crypto_crc_config_dma(crc);
|
||||
|
||||
/* finally kick off CRC operation */
|
||||
crc->regs->control |= BLKEN;
|
||||
SSYNC();
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_update(struct ahash_request *req)
|
||||
{
|
||||
struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
|
||||
|
||||
if (!req->nbytes)
|
||||
return 0;
|
||||
|
||||
dev_dbg(ctx->crc->dev, "crc_update\n");
|
||||
ctx->total += req->nbytes;
|
||||
ctx->flag = CRC_CRYPTO_STATE_UPDATE;
|
||||
|
||||
return bfin_crypto_crc_handle_queue(ctx->crc, req);
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_final(struct ahash_request *req)
|
||||
{
|
||||
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
||||
struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
|
||||
struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
|
||||
|
||||
dev_dbg(ctx->crc->dev, "crc_final\n");
|
||||
ctx->flag = CRC_CRYPTO_STATE_FINISH;
|
||||
crc_ctx->key = 0;
|
||||
|
||||
return bfin_crypto_crc_handle_queue(ctx->crc, req);
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_finup(struct ahash_request *req)
|
||||
{
|
||||
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
||||
struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
|
||||
struct bfin_crypto_crc_reqctx *ctx = ahash_request_ctx(req);
|
||||
|
||||
dev_dbg(ctx->crc->dev, "crc_finishupdate\n");
|
||||
ctx->total += req->nbytes;
|
||||
ctx->flag = CRC_CRYPTO_STATE_FINALUPDATE;
|
||||
crc_ctx->key = 0;
|
||||
|
||||
return bfin_crypto_crc_handle_queue(ctx->crc, req);
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_digest(struct ahash_request *req)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = bfin_crypto_crc_init(req);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return bfin_crypto_crc_finup(req);
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_setkey(struct crypto_ahash *tfm, const u8 *key,
|
||||
unsigned int keylen)
|
||||
{
|
||||
struct bfin_crypto_crc_ctx *crc_ctx = crypto_ahash_ctx(tfm);
|
||||
|
||||
dev_dbg(crc_ctx->crc->dev, "crc_setkey\n");
|
||||
if (keylen != CHKSUM_DIGEST_SIZE) {
|
||||
crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
crc_ctx->key = get_unaligned_le32(key);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bfin_crypto_crc_cra_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct bfin_crypto_crc_ctx *crc_ctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
crc_ctx->key = 0;
|
||||
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
||||
sizeof(struct bfin_crypto_crc_reqctx));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bfin_crypto_crc_cra_exit(struct crypto_tfm *tfm)
|
||||
{
|
||||
}
|
||||
|
||||
static struct ahash_alg algs = {
|
||||
.init = bfin_crypto_crc_init,
|
||||
.update = bfin_crypto_crc_update,
|
||||
.final = bfin_crypto_crc_final,
|
||||
.finup = bfin_crypto_crc_finup,
|
||||
.digest = bfin_crypto_crc_digest,
|
||||
.setkey = bfin_crypto_crc_setkey,
|
||||
.halg.digestsize = CHKSUM_DIGEST_SIZE,
|
||||
.halg.base = {
|
||||
.cra_name = "hmac(crc32)",
|
||||
.cra_driver_name = DRIVER_NAME,
|
||||
.cra_priority = 100,
|
||||
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
||||
CRYPTO_ALG_ASYNC,
|
||||
.cra_blocksize = CHKSUM_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct bfin_crypto_crc_ctx),
|
||||
.cra_alignmask = 3,
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = bfin_crypto_crc_cra_init,
|
||||
.cra_exit = bfin_crypto_crc_cra_exit,
|
||||
}
|
||||
};
|
||||
|
||||
static void bfin_crypto_crc_done_task(unsigned long data)
|
||||
{
|
||||
struct bfin_crypto_crc *crc = (struct bfin_crypto_crc *)data;
|
||||
|
||||
bfin_crypto_crc_handle_queue(crc, NULL);
|
||||
}
|
||||
|
||||
static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct bfin_crypto_crc *crc = dev_id;
|
||||
|
||||
if (crc->regs->status & DCNTEXP) {
|
||||
crc->regs->status = DCNTEXP;
|
||||
SSYNC();
|
||||
|
||||
/* prepare results */
|
||||
put_unaligned_le32(crc->regs->result, crc->req->result);
|
||||
|
||||
crc->regs->control &= ~BLKEN;
|
||||
crc->busy = 0;
|
||||
|
||||
if (crc->req->base.complete)
|
||||
crc->req->base.complete(&crc->req->base, 0);
|
||||
|
||||
tasklet_schedule(&crc->done_task);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
} else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/**
|
||||
* bfin_crypto_crc_suspend - suspend crc device
|
||||
* @pdev: device being suspended
|
||||
* @state: requested suspend state
|
||||
*/
|
||||
static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
|
||||
int i = 100000;
|
||||
|
||||
while ((crc->regs->control & BLKEN) && --i)
|
||||
cpu_relax();
|
||||
|
||||
if (i == 0)
|
||||
return -EBUSY;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
# define bfin_crypto_crc_suspend NULL
|
||||
#endif
|
||||
|
||||
#define bfin_crypto_crc_resume NULL
|
||||
|
||||
/**
|
||||
* bfin_crypto_crc_probe - Initialize module
|
||||
*
|
||||
*/
|
||||
static int __devinit bfin_crypto_crc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
struct bfin_crypto_crc *crc;
|
||||
unsigned int timeout = 100000;
|
||||
int ret;
|
||||
|
||||
crc = kzalloc(sizeof(*crc), GFP_KERNEL);
|
||||
if (!crc) {
|
||||
dev_err(&pdev->dev, "fail to malloc bfin_crypto_crc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
crc->dev = dev;
|
||||
|
||||
INIT_LIST_HEAD(&crc->list);
|
||||
spin_lock_init(&crc->lock);
|
||||
tasklet_init(&crc->done_task, bfin_crypto_crc_done_task, (unsigned long)crc);
|
||||
crypto_init_queue(&crc->queue, CRC_CCRYPTO_QUEUE_LENGTH);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_free_mem;
|
||||
}
|
||||
|
||||
crc->regs = ioremap(res->start, resource_size(res));
|
||||
if (!crc->regs) {
|
||||
dev_err(&pdev->dev, "Cannot map CRC IO\n");
|
||||
ret = -ENXIO;
|
||||
goto out_error_free_mem;
|
||||
}
|
||||
|
||||
crc->irq = platform_get_irq(pdev, 0);
|
||||
if (crc->irq < 0) {
|
||||
dev_err(&pdev->dev, "No CRC DCNTEXP IRQ specified\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_unmap;
|
||||
}
|
||||
|
||||
ret = request_irq(crc->irq, bfin_crypto_crc_handler, IRQF_SHARED, dev_name(dev), crc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to request blackfin crc irq\n");
|
||||
goto out_error_unmap;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(&pdev->dev, "No CRC DMA channel specified\n");
|
||||
ret = -ENOENT;
|
||||
goto out_error_irq;
|
||||
}
|
||||
crc->dma_ch = res->start;
|
||||
|
||||
ret = request_dma(crc->dma_ch, dev_name(dev));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Unable to attach Blackfin CRC DMA channel\n");
|
||||
goto out_error_irq;
|
||||
}
|
||||
|
||||
crc->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &crc->sg_dma, GFP_KERNEL);
|
||||
if (crc->sg_cpu == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto out_error_dma;
|
||||
}
|
||||
/*
|
||||
* need at most CRC_MAX_DMA_DESC sg + CRC_MAX_DMA_DESC middle +
|
||||
* 1 last + 1 next dma descriptors
|
||||
*/
|
||||
crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1));
|
||||
|
||||
crc->regs->control = 0;
|
||||
SSYNC();
|
||||
crc->regs->poly = crc->poly = (u32)pdev->dev.platform_data;
|
||||
SSYNC();
|
||||
|
||||
while (!(crc->regs->status & LUTDONE) && (--timeout) > 0)
|
||||
cpu_relax();
|
||||
|
||||
if (timeout == 0)
|
||||
dev_info(&pdev->dev, "init crc poly timeout\n");
|
||||
|
||||
spin_lock(&crc_list.lock);
|
||||
list_add(&crc->list, &crc_list.dev_list);
|
||||
spin_unlock(&crc_list.lock);
|
||||
|
||||
platform_set_drvdata(pdev, crc);
|
||||
|
||||
ret = crypto_register_ahash(&algs);
|
||||
if (ret) {
|
||||
spin_lock(&crc_list.lock);
|
||||
list_del(&crc->list);
|
||||
spin_unlock(&crc_list.lock);
|
||||
dev_err(&pdev->dev, "Cann't register crypto ahash device\n");
|
||||
goto out_error_dma;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "initialized\n");
|
||||
|
||||
return 0;
|
||||
|
||||
out_error_dma:
|
||||
if (crc->sg_cpu)
|
||||
dma_free_coherent(&pdev->dev, PAGE_SIZE, crc->sg_cpu, crc->sg_dma);
|
||||
free_dma(crc->dma_ch);
|
||||
out_error_irq:
|
||||
free_irq(crc->irq, crc->dev);
|
||||
out_error_unmap:
|
||||
iounmap((void *)crc->regs);
|
||||
out_error_free_mem:
|
||||
kfree(crc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* bfin_crypto_crc_remove - Initialize module
|
||||
*
|
||||
*/
|
||||
static int __devexit bfin_crypto_crc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bfin_crypto_crc *crc = platform_get_drvdata(pdev);
|
||||
|
||||
if (!crc)
|
||||
return -ENODEV;
|
||||
|
||||
spin_lock(&crc_list.lock);
|
||||
list_del(&crc->list);
|
||||
spin_unlock(&crc_list.lock);
|
||||
|
||||
crypto_unregister_ahash(&algs);
|
||||
tasklet_kill(&crc->done_task);
|
||||
iounmap((void *)crc->regs);
|
||||
free_dma(crc->dma_ch);
|
||||
if (crc->irq > 0)
|
||||
free_irq(crc->irq, crc->dev);
|
||||
kfree(crc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver bfin_crypto_crc_driver = {
|
||||
.probe = bfin_crypto_crc_probe,
|
||||
.remove = __devexit_p(bfin_crypto_crc_remove),
|
||||
.suspend = bfin_crypto_crc_suspend,
|
||||
.resume = bfin_crypto_crc_resume,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* bfin_crypto_crc_mod_init - Initialize module
|
||||
*
|
||||
* Checks the module params and registers the platform driver.
|
||||
* Real work is in the platform probe function.
|
||||
*/
|
||||
static int __init bfin_crypto_crc_mod_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pr_info("Blackfin hardware CRC crypto driver\n");
|
||||
|
||||
INIT_LIST_HEAD(&crc_list.dev_list);
|
||||
spin_lock_init(&crc_list.lock);
|
||||
|
||||
ret = platform_driver_register(&bfin_crypto_crc_driver);
|
||||
if (ret) {
|
||||
pr_info(KERN_ERR "unable to register driver\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* bfin_crypto_crc_mod_exit - Deinitialize module
|
||||
*/
|
||||
static void __exit bfin_crypto_crc_mod_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&bfin_crypto_crc_driver);
|
||||
}
|
||||
|
||||
module_init(bfin_crypto_crc_mod_init);
|
||||
module_exit(bfin_crypto_crc_mod_exit);
|
||||
|
||||
MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
|
||||
MODULE_DESCRIPTION("Blackfin CRC hardware crypto driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user