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usb: gadget: add Faraday fotg210_udc driver
Faraday fotg210 udc driver supports only Bulk transfer so far. fotg210 could be configured as an USB2.0 peripheral. This driver is tested with mass storage gadget driver on Faraday EVB a369. Signed-off-by: Yuan-Hsin Chen <yhchen@faraday-tech.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Yuan-Hsin Chen
Felipe Balbi
parent
b3df2faacb
commit
b84a8dee23
@ -192,6 +192,16 @@ config USB_FUSB300
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help
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Faraday usb device controller FUSB300 driver
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config USB_FOTG210_UDC
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tristate "Faraday FOTG210 USB Peripheral Controller"
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help
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Faraday USB2.0 OTG controller which can be configured as
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high speed or full speed USB device. This driver supppors
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Bulk Transfer so far.
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Say "y" to link the driver statically, or "m" to build a
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dynamically linked module called "fotg210_udc".
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config USB_OMAP
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tristate "OMAP USB Device Controller"
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depends on ARCH_OMAP1
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@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EG20T) += pch_udc.o
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obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
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mv_udc-y := mv_udc_core.o
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obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
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obj-$(CONFIG_USB_FOTG210_UDC) += fotg210-udc.o
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obj-$(CONFIG_USB_MV_U3D) += mv_u3d_core.o
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# USB Functions
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1219
drivers/usb/gadget/fotg210-udc.c
Normal file
1219
drivers/usb/gadget/fotg210-udc.c
Normal file
File diff suppressed because it is too large
Load Diff
253
drivers/usb/gadget/fotg210.h
Normal file
253
drivers/usb/gadget/fotg210.h
Normal file
@ -0,0 +1,253 @@
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/*
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* Faraday FOTG210 USB OTG controller
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*
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* Copyright (C) 2013 Faraday Technology Corporation
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* Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */
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#define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */
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/* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
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#define FOTG210_GMIR 0xC4
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#define GMIR_INT_POLARITY 0x8 /*Active High*/
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#define GMIR_MHC_INT 0x4
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#define GMIR_MOTG_INT 0x2
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#define GMIR_MDEV_INT 0x1
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/* Device Main Control Register(0x100) */
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#define FOTG210_DMCR 0x100
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#define DMCR_HS_EN (1 << 6)
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#define DMCR_CHIP_EN (1 << 5)
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#define DMCR_SFRST (1 << 4)
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#define DMCR_GOSUSP (1 << 3)
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#define DMCR_GLINT_EN (1 << 2)
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#define DMCR_HALF_SPEED (1 << 1)
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#define DMCR_CAP_RMWAKUP (1 << 0)
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/* Device Address Register(0x104) */
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#define FOTG210_DAR 0x104
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#define DAR_AFT_CONF (1 << 7)
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/* Device Test Register(0x108) */
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#define FOTG210_DTR 0x108
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#define DTR_TST_CLRFF (1 << 0)
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/* PHY Test Mode Selector register(0x114) */
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#define FOTG210_PHYTMSR 0x114
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#define PHYTMSR_TST_PKT (1 << 4)
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#define PHYTMSR_TST_SE0NAK (1 << 3)
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#define PHYTMSR_TST_KSTA (1 << 2)
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#define PHYTMSR_TST_JSTA (1 << 1)
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#define PHYTMSR_UNPLUG (1 << 0)
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/* Cx configuration and FIFO Empty Status register(0x120) */
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#define FOTG210_DCFESR 0x120
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#define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo))
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#define DCFESR_CX_EMP (1 << 5)
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#define DCFESR_CX_CLR (1 << 3)
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#define DCFESR_CX_STL (1 << 2)
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#define DCFESR_TST_PKDONE (1 << 1)
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#define DCFESR_CX_DONE (1 << 0)
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/* Device IDLE Counter Register(0x124) */
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#define FOTG210_DICR 0x124
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/* Device Mask of Interrupt Group Register (0x130) */
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#define FOTG210_DMIGR 0x130
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#define DMIGR_MINT_G0 (1 << 0)
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/* Device Mask of Interrupt Source Group 0(0x134) */
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#define FOTG210_DMISGR0 0x134
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#define DMISGR0_MCX_COMEND (1 << 3)
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#define DMISGR0_MCX_OUT_INT (1 << 2)
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#define DMISGR0_MCX_IN_INT (1 << 1)
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#define DMISGR0_MCX_SETUP_INT (1 << 0)
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/* Device Mask of Interrupt Source Group 1 Register(0x138)*/
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#define FOTG210_DMISGR1 0x138
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#define DMISGR1_MF3_IN_INT (1 << 19)
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#define DMISGR1_MF2_IN_INT (1 << 18)
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#define DMISGR1_MF1_IN_INT (1 << 17)
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#define DMISGR1_MF0_IN_INT (1 << 16)
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#define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo)))
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#define DMISGR1_MF3_SPK_INT (1 << 7)
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#define DMISGR1_MF3_OUT_INT (1 << 6)
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#define DMISGR1_MF2_SPK_INT (1 << 5)
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#define DMISGR1_MF2_OUT_INT (1 << 4)
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#define DMISGR1_MF1_SPK_INT (1 << 3)
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#define DMISGR1_MF1_OUT_INT (1 << 2)
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#define DMISGR1_MF0_SPK_INT (1 << 1)
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#define DMISGR1_MF0_OUT_INT (1 << 0)
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#define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2)
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/* Device Mask of Interrupt Source Group 2 Register (0x13C) */
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#define FOTG210_DMISGR2 0x13C
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#define DMISGR2_MDMA_ERROR (1 << 8)
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#define DMISGR2_MDMA_CMPLT (1 << 7)
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/* Device Interrupt group Register (0x140) */
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#define FOTG210_DIGR 0x140
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#define DIGR_INT_G2 (1 << 2)
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#define DIGR_INT_G1 (1 << 1)
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#define DIGR_INT_G0 (1 << 0)
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/* Device Interrupt Source Group 0 Register (0x144) */
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#define FOTG210_DISGR0 0x144
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#define DISGR0_CX_COMABT_INT (1 << 5)
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#define DISGR0_CX_COMFAIL_INT (1 << 4)
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#define DISGR0_CX_COMEND_INT (1 << 3)
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#define DISGR0_CX_OUT_INT (1 << 2)
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#define DISGR0_CX_IN_INT (1 << 1)
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#define DISGR0_CX_SETUP_INT (1 << 0)
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/* Device Interrupt Source Group 1 Register (0x148) */
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#define FOTG210_DISGR1 0x148
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#define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2))
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#define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2))
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#define DISGR1_IN_INT(fifo) (1 << 16 << (fifo))
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/* Device Interrupt Source Group 2 Register (0x14C) */
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#define FOTG210_DISGR2 0x14C
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#define DISGR2_DMA_ERROR (1 << 8)
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#define DISGR2_DMA_CMPLT (1 << 7)
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#define DISGR2_RX0BYTE_INT (1 << 6)
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#define DISGR2_TX0BYTE_INT (1 << 5)
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#define DISGR2_ISO_SEQ_ABORT_INT (1 << 4)
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#define DISGR2_ISO_SEQ_ERR_INT (1 << 3)
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#define DISGR2_RESM_INT (1 << 2)
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#define DISGR2_SUSP_INT (1 << 1)
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#define DISGR2_USBRST_INT (1 << 0)
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/* Device Receive Zero-Length Data Packet Register (0x150)*/
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#define FOTG210_RX0BYTE 0x150
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#define RX0BYTE_EP8 (1 << 7)
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#define RX0BYTE_EP7 (1 << 6)
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#define RX0BYTE_EP6 (1 << 5)
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#define RX0BYTE_EP5 (1 << 4)
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#define RX0BYTE_EP4 (1 << 3)
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#define RX0BYTE_EP3 (1 << 2)
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#define RX0BYTE_EP2 (1 << 1)
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#define RX0BYTE_EP1 (1 << 0)
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/* Device Transfer Zero-Length Data Packet Register (0x154)*/
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#define FOTG210_TX0BYTE 0x154
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#define TX0BYTE_EP8 (1 << 7)
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#define TX0BYTE_EP7 (1 << 6)
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#define TX0BYTE_EP6 (1 << 5)
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#define TX0BYTE_EP5 (1 << 4)
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#define TX0BYTE_EP4 (1 << 3)
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#define TX0BYTE_EP3 (1 << 2)
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#define TX0BYTE_EP2 (1 << 1)
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#define TX0BYTE_EP1 (1 << 0)
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/* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
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#define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1))
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#define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF)
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#define INOUTEPMPSR_STL_EP (1 << 11)
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#define INOUTEPMPSR_RESET_TSEQ (1 << 12)
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/* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
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#define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1))
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/* Device Endpoint 1~4 Map Register (0x1A0) */
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#define FOTG210_EPMAP 0x1A0
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#define EPMAP_FIFONO(ep, dir) \
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((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
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#define EPMAP_FIFONOMSK(ep, dir) \
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((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
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/* Device FIFO Map Register (0x1A8) */
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#define FOTG210_FIFOMAP 0x1A8
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#define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8)
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#define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8)
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#define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8)
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#define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8)
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#define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8)
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#define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8)
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/* Device FIFO Confuguration Register (0x1AC) */
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#define FOTG210_FIFOCF 0x1AC
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#define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8)
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#define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2)
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#define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2)
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#define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2)
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#define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4)
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#define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4)
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#define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5)
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/* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
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#define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4)
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#define FIBCR_BCFX 0x7FF
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#define FIBCR_FFRST (1 << 12)
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/* Device DMA Target FIFO Number Register (0x1C0) */
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#define FOTG210_DMATFNR 0x1C0
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#define DMATFNR_ACC_CXF (1 << 4)
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#define DMATFNR_ACC_F3 (1 << 3)
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#define DMATFNR_ACC_F2 (1 << 2)
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#define DMATFNR_ACC_F1 (1 << 1)
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#define DMATFNR_ACC_F0 (1 << 0)
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#define DMATFNR_ACC_FN(fifo) (1 << (fifo))
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#define DMATFNR_DISDMA 0
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/* Device DMA Controller Parameter setting 1 Register (0x1C8) */
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#define FOTG210_DMACPSR1 0x1C8
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#define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8)
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#define DMACPSR1_DMA_ABORT (1 << 3)
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#define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1)
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#define DMACPSR1_DMA_START (1 << 0)
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/* Device DMA Controller Parameter setting 2 Register (0x1CC) */
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#define FOTG210_DMACPSR2 0x1CC
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/* Device DMA Controller Parameter setting 3 Register (0x1CC) */
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#define FOTG210_CXPORT 0x1D0
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struct fotg210_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct fotg210_ep {
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struct usb_ep ep;
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struct fotg210_udc *fotg210;
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struct list_head queue;
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unsigned stall:1;
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unsigned wedged:1;
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unsigned use_dma:1;
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unsigned char epnum;
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unsigned char type;
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unsigned char dir_in;
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unsigned int maxp;
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const struct usb_endpoint_descriptor *desc;
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};
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struct fotg210_udc {
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spinlock_t lock; /* protect the struct */
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void __iomem *reg;
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unsigned long irq_trigger;
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct fotg210_ep *ep[FOTG210_MAX_NUM_EP];
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struct usb_request *ep0_req; /* for internal request */
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__le16 ep0_data;
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u8 ep0_dir; /* 0/0x80 out/in */
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u8 reenum; /* if re-enumeration */
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};
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#define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget)
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