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ASoC: rt5670: redefine ASRC control registers 0x84 and 0x85
The previous definition of registers 0x84 and 0x85 doesn't match the datasheet. So this patch removes the wrong definition and writes a new one for the two registers. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -1023,50 +1023,33 @@
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#define RT5670_DMIC_2_M_NOR (0x0 << 8)
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#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
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/* ASRC clock source selection (0x84, 0x85) */
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#define RT5670_CLK_SEL_SYS (0x0)
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#define RT5670_CLK_SEL_I2S1_ASRC (0x1)
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#define RT5670_CLK_SEL_I2S2_ASRC (0x2)
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#define RT5670_CLK_SEL_I2S3_ASRC (0x3)
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#define RT5670_CLK_SEL_SYS2 (0x5)
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#define RT5670_CLK_SEL_SYS3 (0x6)
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/* ASRC Control 2 (0x84) */
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#define RT5670_MDA_L_M_MASK (0x1 << 15)
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#define RT5670_MDA_L_M_SFT 15
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#define RT5670_MDA_L_M_NOR (0x0 << 15)
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#define RT5670_MDA_L_M_ASYN (0x1 << 15)
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#define RT5670_MDA_R_M_MASK (0x1 << 14)
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#define RT5670_MDA_R_M_SFT 14
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#define RT5670_MDA_R_M_NOR (0x0 << 14)
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#define RT5670_MDA_R_M_ASYN (0x1 << 14)
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#define RT5670_MAD_L_M_MASK (0x1 << 13)
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#define RT5670_MAD_L_M_SFT 13
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#define RT5670_MAD_L_M_NOR (0x0 << 13)
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#define RT5670_MAD_L_M_ASYN (0x1 << 13)
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#define RT5670_MAD_R_M_MASK (0x1 << 12)
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#define RT5670_MAD_R_M_SFT 12
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#define RT5670_MAD_R_M_NOR (0x0 << 12)
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#define RT5670_MAD_R_M_ASYN (0x1 << 12)
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#define RT5670_ADC_M_MASK (0x1 << 11)
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#define RT5670_ADC_M_SFT 11
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#define RT5670_ADC_M_NOR (0x0 << 11)
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#define RT5670_ADC_M_ASYN (0x1 << 11)
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#define RT5670_STO_DAC_M_MASK (0x1 << 5)
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#define RT5670_STO_DAC_M_SFT 5
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#define RT5670_STO_DAC_M_NOR (0x0 << 5)
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#define RT5670_STO_DAC_M_ASYN (0x1 << 5)
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#define RT5670_I2S1_R_D_MASK (0x1 << 4)
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#define RT5670_I2S1_R_D_SFT 4
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#define RT5670_I2S1_R_D_DIS (0x0 << 4)
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#define RT5670_I2S1_R_D_EN (0x1 << 4)
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#define RT5670_I2S2_R_D_MASK (0x1 << 3)
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#define RT5670_I2S2_R_D_SFT 3
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#define RT5670_I2S2_R_D_DIS (0x0 << 3)
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#define RT5670_I2S2_R_D_EN (0x1 << 3)
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#define RT5670_PRE_SCLK_MASK (0x3)
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#define RT5670_PRE_SCLK_SFT 0
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#define RT5670_PRE_SCLK_512 (0x0)
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#define RT5670_PRE_SCLK_1024 (0x1)
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#define RT5670_PRE_SCLK_2048 (0x2)
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#define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
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#define RT5670_DA_STO_CLK_SEL_SFT 12
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#define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
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#define RT5670_DA_MONOL_CLK_SEL_SFT 8
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#define RT5670_DA_MONOR_CLK_SEL_MASK (0xf << 4)
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#define RT5670_DA_MONOR_CLK_SEL_SFT 4
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#define RT5670_AD_STO1_CLK_SEL_MASK (0xf << 0)
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#define RT5670_AD_STO1_CLK_SEL_SFT 0
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/* ASRC Control 3 (0x85) */
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#define RT5670_I2S1_RATE_MASK (0xf << 12)
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#define RT5670_I2S1_RATE_SFT 12
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#define RT5670_I2S2_RATE_MASK (0xf << 8)
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#define RT5670_I2S2_RATE_SFT 8
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#define RT5670_UP_CLK_SEL_MASK (0xf << 12)
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#define RT5670_UP_CLK_SEL_SFT 12
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#define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
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#define RT5670_DOWN_CLK_SEL_SFT 8
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#define RT5670_AD_MONOL_CLK_SEL_MASK (0xf << 4)
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#define RT5670_AD_MONOL_CLK_SEL_SFT 4
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#define RT5670_AD_MONOR_CLK_SEL_MASK (0xf << 0)
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#define RT5670_AD_MONOR_CLK_SEL_SFT 0
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/* ASRC Control 4 (0x89) */
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#define RT5670_I2S1_PD_MASK (0x7 << 12)
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